2 * Device Tree Source for the r8a77970 SoC
4 * Copyright (C) 2016-2017 Renesas Electronics Corp.
5 * Copyright (C) 2017 Cogent Embedded, Inc.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/power/r8a77970-sysc.h>
18 compatible = "renesas,r8a77970";
23 compatible = "arm,psci-1.0", "arm,psci-0.2";
33 compatible = "arm,cortex-a53", "arm,armv8";
35 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
36 power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
37 next-level-cache = <&L2_CA53>;
38 enable-method = "psci";
41 L2_CA53: cache-controller {
43 power-domains = <&sysc R8A77970_PD_CA53_SCU>;
50 compatible = "fixed-clock";
52 /* This value must be overridden by the board */
53 clock-frequency = <0>;
57 compatible = "fixed-clock";
59 /* This value must be overridden by the board */
60 clock-frequency = <0>;
63 /* External SCIF clock - to be overridden by boards that provide it */
65 compatible = "fixed-clock";
67 clock-frequency = <0>;
71 compatible = "simple-bus";
72 interrupt-parent = <&gic>;
78 gic: interrupt-controller@f1010000 {
79 compatible = "arm,gic-400";
80 #interrupt-cells = <3>;
83 reg = <0 0xf1010000 0 0x1000>,
84 <0 0xf1020000 0 0x20000>,
85 <0 0xf1040000 0 0x20000>,
86 <0 0xf1060000 0 0x20000>;
87 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
88 IRQ_TYPE_LEVEL_HIGH)>;
89 clocks = <&cpg CPG_MOD 408>;
91 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
96 compatible = "arm,armv8-timer";
97 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
100 IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
102 IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
104 IRQ_TYPE_LEVEL_LOW)>;
107 rwdt: watchdog@e6020000 {
108 compatible = "renesas,r8a77970-wdt",
109 "renesas,rcar-gen3-wdt";
110 reg = <0 0xe6020000 0 0x0c>;
111 clocks = <&cpg CPG_MOD 402>;
112 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
117 cpg: clock-controller@e6150000 {
118 compatible = "renesas,r8a77970-cpg-mssr";
119 reg = <0 0xe6150000 0 0x1000>;
120 clocks = <&extal_clk>, <&extalr_clk>;
121 clock-names = "extal", "extalr";
123 #power-domain-cells = <0>;
127 rst: reset-controller@e6160000 {
128 compatible = "renesas,r8a77970-rst";
129 reg = <0 0xe6160000 0 0x200>;
132 sysc: system-controller@e6180000 {
133 compatible = "renesas,r8a77970-sysc";
134 reg = <0 0xe6180000 0 0x440>;
135 #power-domain-cells = <1>;
138 ipmmu_vi0: mmu@febd0000 {
139 compatible = "renesas,ipmmu-r8a77970";
140 reg = <0 0xfebd0000 0 0x1000>;
141 renesas,ipmmu-main = <&ipmmu_mm 9>;
142 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
147 ipmmu_ir: mmu@ff8b0000 {
148 compatible = "renesas,ipmmu-r8a77970";
149 reg = <0 0xff8b0000 0 0x1000>;
150 renesas,ipmmu-main = <&ipmmu_mm 3>;
151 power-domains = <&sysc R8A77970_PD_A3IR>;
156 ipmmu_rt: mmu@ffc80000 {
157 compatible = "renesas,ipmmu-r8a77970";
158 reg = <0 0xffc80000 0 0x1000>;
159 renesas,ipmmu-main = <&ipmmu_mm 7>;
160 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
164 ipmmu_ds1: mmu@e7740000 {
165 compatible = "renesas,ipmmu-r8a77970";
166 reg = <0 0xe7740000 0 0x1000>;
167 renesas,ipmmu-main = <&ipmmu_mm 1>;
168 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
172 ipmmu_mm: mmu@e67b0000 {
173 compatible = "renesas,ipmmu-r8a77970";
174 reg = <0 0xe67b0000 0 0x1000>;
175 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
177 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
181 intc_ex: interrupt-controller@e61c0000 {
182 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
183 #interrupt-cells = <2>;
184 interrupt-controller;
185 reg = <0 0xe61c0000 0 0x200>;
186 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
187 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
188 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
189 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
190 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
191 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&cpg CPG_MOD 407>;
193 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
197 prr: chipid@fff00044 {
198 compatible = "renesas,prr";
199 reg = <0 0xfff00044 0 4>;
202 dmac1: dma-controller@e7300000 {
203 compatible = "renesas,dmac-r8a77970",
205 reg = <0 0xe7300000 0 0x10000>;
206 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
207 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
208 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
209 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
210 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
211 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
212 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
213 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
214 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
215 interrupt-names = "error",
216 "ch0", "ch1", "ch2", "ch3",
217 "ch4", "ch5", "ch6", "ch7";
218 clocks = <&cpg CPG_MOD 218>;
220 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
224 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
225 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
226 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
227 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
230 dmac2: dma-controller@e7310000 {
231 compatible = "renesas,dmac-r8a77970",
233 reg = <0 0xe7310000 0 0x10000>;
234 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
235 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
236 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
237 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
238 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
239 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
240 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
241 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
242 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-names = "error",
244 "ch0", "ch1", "ch2", "ch3",
245 "ch4", "ch5", "ch6", "ch7";
246 clocks = <&cpg CPG_MOD 217>;
248 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
252 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
253 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
254 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
255 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
258 hscif0: serial@e6540000 {
259 compatible = "renesas,hscif-r8a77970",
260 "renesas,rcar-gen3-hscif",
262 reg = <0 0xe6540000 0 96>;
263 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&cpg CPG_MOD 520>,
265 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
267 clock-names = "fck", "brg_int", "scif_clk";
268 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
269 <&dmac2 0x31>, <&dmac2 0x30>;
270 dma-names = "tx", "rx", "tx", "rx";
271 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
276 hscif1: serial@e6550000 {
277 compatible = "renesas,hscif-r8a77970",
278 "renesas,rcar-gen3-hscif",
280 reg = <0 0xe6550000 0 96>;
281 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&cpg CPG_MOD 519>,
283 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
285 clock-names = "fck", "brg_int", "scif_clk";
286 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
287 <&dmac2 0x33>, <&dmac2 0x32>;
288 dma-names = "tx", "rx", "tx", "rx";
289 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
294 hscif2: serial@e6560000 {
295 compatible = "renesas,hscif-r8a77970",
296 "renesas,rcar-gen3-hscif",
298 reg = <0 0xe6560000 0 96>;
299 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cpg CPG_MOD 518>,
301 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
303 clock-names = "fck", "brg_int", "scif_clk";
304 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
305 <&dmac2 0x35>, <&dmac2 0x34>;
306 dma-names = "tx", "rx", "tx", "rx";
307 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
312 hscif3: serial@e66a0000 {
313 compatible = "renesas,hscif-r8a77970",
314 "renesas,rcar-gen3-hscif", "renesas,hscif";
315 reg = <0 0xe66a0000 0 96>;
316 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&cpg CPG_MOD 517>,
318 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
320 clock-names = "fck", "brg_int", "scif_clk";
321 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
322 <&dmac2 0x37>, <&dmac2 0x36>;
323 dma-names = "tx", "rx", "tx", "rx";
324 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
329 scif0: serial@e6e60000 {
330 compatible = "renesas,scif-r8a77970",
331 "renesas,rcar-gen3-scif",
333 reg = <0 0xe6e60000 0 64>;
334 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&cpg CPG_MOD 207>,
336 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
338 clock-names = "fck", "brg_int", "scif_clk";
339 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
340 <&dmac2 0x51>, <&dmac2 0x50>;
341 dma-names = "tx", "rx", "tx", "rx";
342 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
347 scif1: serial@e6e68000 {
348 compatible = "renesas,scif-r8a77970",
349 "renesas,rcar-gen3-scif",
351 reg = <0 0xe6e68000 0 64>;
352 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cpg CPG_MOD 206>,
354 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
356 clock-names = "fck", "brg_int", "scif_clk";
357 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
358 <&dmac2 0x53>, <&dmac2 0x52>;
359 dma-names = "tx", "rx", "tx", "rx";
360 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
365 scif3: serial@e6c50000 {
366 compatible = "renesas,scif-r8a77970",
367 "renesas,rcar-gen3-scif",
369 reg = <0 0xe6c50000 0 64>;
370 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cpg CPG_MOD 204>,
372 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
374 clock-names = "fck", "brg_int", "scif_clk";
375 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
376 <&dmac2 0x57>, <&dmac2 0x56>;
377 dma-names = "tx", "rx", "tx", "rx";
378 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
383 scif4: serial@e6c40000 {
384 compatible = "renesas,scif-r8a77970",
385 "renesas,rcar-gen3-scif", "renesas,scif";
386 reg = <0 0xe6c40000 0 64>;
387 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&cpg CPG_MOD 203>,
389 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
391 clock-names = "fck", "brg_int", "scif_clk";
392 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
393 <&dmac2 0x59>, <&dmac2 0x58>;
394 dma-names = "tx", "rx", "tx", "rx";
395 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
400 avb: ethernet@e6800000 {
401 compatible = "renesas,etheravb-r8a77970",
402 "renesas,etheravb-rcar-gen3";
403 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
404 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "ch0", "ch1", "ch2", "ch3",
430 "ch4", "ch5", "ch6", "ch7",
431 "ch8", "ch9", "ch10", "ch11",
432 "ch12", "ch13", "ch14", "ch15",
433 "ch16", "ch17", "ch18", "ch19",
434 "ch20", "ch21", "ch22", "ch23",
436 clocks = <&cpg CPG_MOD 812>;
437 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
439 phy-mode = "rgmii-id";
440 iommus = <&ipmmu_rt 3>;
441 #address-cells = <1>;