| blob | 8a3276ba2da1addb36a1362734ce198c3b4d6daf |
1 /*
2 * Device Tree Source for UniPhier LD20 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/gpio/uniphier-gpio.h>
12 #include <dt-bindings/thermal/thermal.h>
14 /memreserve/ 0x80000000 0x02000000;
16 / {
17 compatible = "socionext,uniphier-ld20";
18 #address-cells = <2>;
19 #size-cells = <2>;
20 interrupt-parent = <&gic>;
22 cpus {
23 #address-cells = <2>;
24 #size-cells = <0>;
26 cpu-map {
27 cluster0 {
28 core0 {
29 cpu = <&cpu0>;
30 };
31 core1 {
32 cpu = <&cpu1>;
33 };
34 };
36 cluster1 {
37 core0 {
38 cpu = <&cpu2>;
39 };
40 core1 {
41 cpu = <&cpu3>;
42 };
43 };
44 };
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a72", "arm,armv8";
49 reg = <0 0x000>;
50 clocks = <&sys_clk 32>;
51 enable-method = "psci";
52 operating-points-v2 = <&cluster0_opp>;
53 #cooling-cells = <2>;
54 };
56 cpu1: cpu@1 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a72", "arm,armv8";
59 reg = <0 0x001>;
60 clocks = <&sys_clk 32>;
61 enable-method = "psci";
62 operating-points-v2 = <&cluster0_opp>;
63 };
65 cpu2: cpu@100 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a53", "arm,armv8";
68 reg = <0 0x100>;
69 clocks = <&sys_clk 33>;
70 enable-method = "psci";
71 operating-points-v2 = <&cluster1_opp>;
72 #cooling-cells = <2>;
73 };
75 cpu3: cpu@101 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a53", "arm,armv8";
78 reg = <0 0x101>;
79 clocks = <&sys_clk 33>;
80 enable-method = "psci";
81 operating-points-v2 = <&cluster1_opp>;
82 };
83 };
85 cluster0_opp: opp-table0 {
86 compatible = "operating-points-v2";
87 opp-shared;
89 opp-250000000 {
90 opp-hz = /bits/ 64 <250000000>;
91 clock-latency-ns = <300>;
92 };
93 opp-275000000 {
94 opp-hz = /bits/ 64 <275000000>;
95 clock-latency-ns = <300>;
96 };
97 opp-500000000 {
98 opp-hz = /bits/ 64 <500000000>;
99 clock-latency-ns = <300>;
100 };
101 opp-550000000 {
102 opp-hz = /bits/ 64 <550000000>;
103 clock-latency-ns = <300>;
104 };
105 opp-666667000 {
106 opp-hz = /bits/ 64 <666667000>;
107 clock-latency-ns = <300>;
108 };
109 opp-733334000 {
110 opp-hz = /bits/ 64 <733334000>;
111 clock-latency-ns = <300>;
112 };
113 opp-1000000000 {
114 opp-hz = /bits/ 64 <1000000000>;
115 clock-latency-ns = <300>;
116 };
117 opp-1100000000 {
118 opp-hz = /bits/ 64 <1100000000>;
119 clock-latency-ns = <300>;
120 };
121 };
123 cluster1_opp: opp-table1 {
124 compatible = "operating-points-v2";
125 opp-shared;
127 opp-250000000 {
128 opp-hz = /bits/ 64 <250000000>;
129 clock-latency-ns = <300>;
130 };
131 opp-275000000 {
132 opp-hz = /bits/ 64 <275000000>;
133 clock-latency-ns = <300>;
134 };
135 opp-500000000 {
136 opp-hz = /bits/ 64 <500000000>;
137 clock-latency-ns = <300>;
138 };
139 opp-550000000 {
140 opp-hz = /bits/ 64 <550000000>;
141 clock-latency-ns = <300>;
142 };
143 opp-666667000 {
144 opp-hz = /bits/ 64 <666667000>;
145 clock-latency-ns = <300>;
146 };
147 opp-733334000 {
148 opp-hz = /bits/ 64 <733334000>;
149 clock-latency-ns = <300>;
150 };
151 opp-1000000000 {
152 opp-hz = /bits/ 64 <1000000000>;
153 clock-latency-ns = <300>;
154 };
155 opp-1100000000 {
156 opp-hz = /bits/ 64 <1100000000>;
157 clock-latency-ns = <300>;
158 };
159 };
161 psci {
162 compatible = "arm,psci-1.0";
163 method = "smc";
164 };
166 clocks {
167 refclk: ref {
168 compatible = "fixed-clock";
169 #clock-cells = <0>;
170 clock-frequency = <25000000>;
171 };
172 };
174 emmc_pwrseq: emmc-pwrseq {
175 compatible = "mmc-pwrseq-emmc";
176 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
177 };
179 timer {
180 compatible = "arm,armv8-timer";
181 interrupts = <1 13 4>,
182 <1 14 4>,
183 <1 11 4>,
184 <1 10 4>;
185 };
187 thermal-zones {
188 cpu-thermal {
189 polling-delay-passive = <250>; /* 250ms */
190 polling-delay = <1000>; /* 1000ms */
191 thermal-sensors = <&pvtctl>;
193 trips {
194 cpu_crit: cpu-crit {
195 temperature = <110000>; /* 110C */
196 hysteresis = <2000>;
197 type = "critical";
198 };
199 cpu_alert: cpu-alert {
200 temperature = <100000>; /* 100C */
201 hysteresis = <2000>;
202 type = "passive";
203 };
204 };
206 cooling-maps {
207 map0 {
208 trip = <&cpu_alert>;
209 cooling-device = <&cpu0
210 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211 };
212 map1 {
213 trip = <&cpu_alert>;
214 cooling-device = <&cpu2
215 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
216 };
217 };
218 };
219 };
221 soc@0 {
222 compatible = "simple-bus";
223 #address-cells = <1>;
224 #size-cells = <1>;
225 ranges = <0 0 0 0xffffffff>;
227 serial0: serial@54006800 {
228 compatible = "socionext,uniphier-uart";
229 status = "disabled";
230 reg = <0x54006800 0x40>;
231 interrupts = <0 33 4>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart0>;
234 clocks = <&peri_clk 0>;
235 resets = <&peri_rst 0>;
236 };
238 serial1: serial@54006900 {
239 compatible = "socionext,uniphier-uart";
240 status = "disabled";
241 reg = <0x54006900 0x40>;
242 interrupts = <0 35 4>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_uart1>;
245 clocks = <&peri_clk 1>;
246 resets = <&peri_rst 1>;
247 };
249 serial2: serial@54006a00 {
250 compatible = "socionext,uniphier-uart";
251 status = "disabled";
252 reg = <0x54006a00 0x40>;
253 interrupts = <0 37 4>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart2>;
256 clocks = <&peri_clk 2>;
257 resets = <&peri_rst 2>;
258 };
260 serial3: serial@54006b00 {
261 compatible = "socionext,uniphier-uart";
262 status = "disabled";
263 reg = <0x54006b00 0x40>;
264 interrupts = <0 177 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart3>;
267 clocks = <&peri_clk 3>;
268 resets = <&peri_rst 3>;
269 };
271 gpio: gpio@55000000 {
272 compatible = "socionext,uniphier-gpio";
273 reg = <0x55000000 0x200>;
274 interrupt-parent = <&aidet>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 gpio-controller;
278 #gpio-cells = <2>;
279 gpio-ranges = <&pinctrl 0 0 0>,
280 <&pinctrl 96 0 0>,
281 <&pinctrl 160 0 0>;
282 gpio-ranges-group-names = "gpio_range0",
283 "gpio_range1",
284 "gpio_range2";
285 ngpios = <205>;
286 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
287 <21 217 3>;
288 };
290 adamv@57920000 {
291 compatible = "socionext,uniphier-ld20-adamv",
292 "simple-mfd", "syscon";
293 reg = <0x57920000 0x1000>;
295 adamv_rst: reset {
296 compatible = "socionext,uniphier-ld20-adamv-reset";
297 #reset-cells = <1>;
298 };
299 };
301 i2c0: i2c@58780000 {
302 compatible = "socionext,uniphier-fi2c";
303 status = "disabled";
304 reg = <0x58780000 0x80>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 interrupts = <0 41 4>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_i2c0>;
310 clocks = <&peri_clk 4>;
311 resets = <&peri_rst 4>;
312 clock-frequency = <100000>;
313 };
315 i2c1: i2c@58781000 {
316 compatible = "socionext,uniphier-fi2c";
317 status = "disabled";
318 reg = <0x58781000 0x80>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321 interrupts = <0 42 4>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_i2c1>;
324 clocks = <&peri_clk 5>;
325 resets = <&peri_rst 5>;
326 clock-frequency = <100000>;
327 };
329 i2c2: i2c@58782000 {
330 compatible = "socionext,uniphier-fi2c";
331 reg = <0x58782000 0x80>;
332 #address-cells = <1>;
333 #size-cells = <0>;
334 interrupts = <0 43 4>;
335 clocks = <&peri_clk 6>;
336 resets = <&peri_rst 6>;
337 clock-frequency = <400000>;
338 };
340 i2c3: i2c@58783000 {
341 compatible = "socionext,uniphier-fi2c";
342 status = "disabled";
343 reg = <0x58783000 0x80>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 interrupts = <0 44 4>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_i2c3>;
349 clocks = <&peri_clk 7>;
350 resets = <&peri_rst 7>;
351 clock-frequency = <100000>;
352 };
354 i2c4: i2c@58784000 {
355 compatible = "socionext,uniphier-fi2c";
356 status = "disabled";
357 reg = <0x58784000 0x80>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 interrupts = <0 45 4>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_i2c4>;
363 clocks = <&peri_clk 8>;
364 resets = <&peri_rst 8>;
365 clock-frequency = <100000>;
366 };
368 i2c5: i2c@58785000 {
369 compatible = "socionext,uniphier-fi2c";
370 reg = <0x58785000 0x80>;
371 #address-cells = <1>;
372 #size-cells = <0>;
373 interrupts = <0 25 4>;
374 clocks = <&peri_clk 9>;
375 resets = <&peri_rst 9>;
376 clock-frequency = <400000>;
377 };
379 system_bus: system-bus@58c00000 {
380 compatible = "socionext,uniphier-system-bus";
381 status = "disabled";
382 reg = <0x58c00000 0x400>;
383 #address-cells = <2>;
384 #size-cells = <1>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_system_bus>;
387 };
389 smpctrl@59801000 {
390 compatible = "socionext,uniphier-smpctrl";
391 reg = <0x59801000 0x400>;
392 };
394 sdctrl@59810000 {
395 compatible = "socionext,uniphier-ld20-sdctrl",
396 "simple-mfd", "syscon";
397 reg = <0x59810000 0x400>;
399 sd_clk: clock {
400 compatible = "socionext,uniphier-ld20-sd-clock";
401 #clock-cells = <1>;
402 };
404 sd_rst: reset {
405 compatible = "socionext,uniphier-ld20-sd-reset";
406 #reset-cells = <1>;
407 };
408 };
410 perictrl@59820000 {
411 compatible = "socionext,uniphier-ld20-perictrl",
412 "simple-mfd", "syscon";
413 reg = <0x59820000 0x200>;
415 peri_clk: clock {
416 compatible = "socionext,uniphier-ld20-peri-clock";
417 #clock-cells = <1>;
418 };
420 peri_rst: reset {
421 compatible = "socionext,uniphier-ld20-peri-reset";
422 #reset-cells = <1>;
423 };
424 };
426 emmc: sdhc@5a000000 {
427 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
428 reg = <0x5a000000 0x400>;
429 interrupts = <0 78 4>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_emmc>;
432 clocks = <&sys_clk 4>;
433 resets = <&sys_rst 4>;
434 bus-width = <8>;
435 mmc-ddr-1_8v;
436 mmc-hs200-1_8v;
437 mmc-pwrseq = <&emmc_pwrseq>;
438 cdns,phy-input-delay-legacy = <4>;
439 cdns,phy-input-delay-mmc-highspeed = <2>;
440 cdns,phy-input-delay-mmc-ddr = <3>;
441 cdns,phy-dll-delay-sdclk = <21>;
442 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
443 };
445 soc-glue@5f800000 {
446 compatible = "socionext,uniphier-ld20-soc-glue",
447 "simple-mfd", "syscon";
448 reg = <0x5f800000 0x2000>;
450 pinctrl: pinctrl {
451 compatible = "socionext,uniphier-ld20-pinctrl";
452 };
453 };
455 soc-glue@5f900000 {
456 compatible = "socionext,uniphier-ld20-soc-glue-debug",
457 "simple-mfd";
458 #address-cells = <1>;
459 #size-cells = <1>;
460 ranges = <0 0x5f900000 0x2000>;
462 efuse@100 {
463 compatible = "socionext,uniphier-efuse";
464 reg = <0x100 0x28>;
465 };
467 efuse@200 {
468 compatible = "socionext,uniphier-efuse";
469 reg = <0x200 0x68>;
470 };
471 };
473 aidet: aidet@5fc20000 {
474 compatible = "socionext,uniphier-ld20-aidet";
475 reg = <0x5fc20000 0x200>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 };
480 gic: interrupt-controller@5fe00000 {
481 compatible = "arm,gic-v3";
482 reg = <0x5fe00000 0x10000>, /* GICD */
483 <0x5fe80000 0x80000>; /* GICR */
484 interrupt-controller;
485 #interrupt-cells = <3>;
486 interrupts = <1 9 4>;
487 };
489 sysctrl@61840000 {
490 compatible = "socionext,uniphier-ld20-sysctrl",
491 "simple-mfd", "syscon";
492 reg = <0x61840000 0x10000>;
494 sys_clk: clock {
495 compatible = "socionext,uniphier-ld20-clock";
496 #clock-cells = <1>;
497 };
499 sys_rst: reset {
500 compatible = "socionext,uniphier-ld20-reset";
501 #reset-cells = <1>;
502 };
504 watchdog {
505 compatible = "socionext,uniphier-wdt";
506 };
508 pvtctl: pvtctl {
509 compatible = "socionext,uniphier-ld20-thermal";
510 interrupts = <0 3 4>;
511 #thermal-sensor-cells = <0>;
512 socionext,tmod-calibration = <0x0f22 0x68ee>;
513 };
514 };
516 nand: nand@68000000 {
517 compatible = "socionext,uniphier-denali-nand-v5b";
518 status = "disabled";
519 reg-names = "nand_data", "denali_reg";
520 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
521 interrupts = <0 65 4>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_nand>;
524 clocks = <&sys_clk 2>;
525 resets = <&sys_rst 2>;
526 };
527 };
528 };
530 #include "uniphier-pinctrl.dtsi"