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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / arch / arm64 / include / asm / sysreg.h
blob0e1960c59197aa581c4c0e1ee4fb1f5558f902f6
1 /*
2 * Macros for accessing system registers with older binutils.
3 *
4 * Copyright (C) 2014 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef __ASM_SYSREG_H
21 #define __ASM_SYSREG_H
22
23 #include <asm/compiler.h>
24 #include <linux/stringify.h>
25
26 /*
27 * ARMv8 ARM reserves the following encoding for system registers:
28 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
29 * C5.2, version:ARM DDI 0487A.f)
30 * [20-19] : Op0
31 * [18-16] : Op1
32 * [15-12] : CRn
33 * [11-8] : CRm
34 * [7-5] : Op2
35 */
36 #define Op0_shift 19
37 #define Op0_mask 0x3
38 #define Op1_shift 16
39 #define Op1_mask 0x7
40 #define CRn_shift 12
41 #define CRn_mask 0xf
42 #define CRm_shift 8
43 #define CRm_mask 0xf
44 #define Op2_shift 5
45 #define Op2_mask 0x7
46
47 #define sys_reg(op0, op1, crn, crm, op2) \
48 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
49 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
50 ((op2) << Op2_shift))
51
52 #define sys_insn sys_reg
53
54 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
55 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
56 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
57 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
58 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
59
60 #ifndef CONFIG_BROKEN_GAS_INST
61
62 #ifdef __ASSEMBLY__
63 #define __emit_inst(x) .inst (x)
64 #else
65 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
66 #endif
67
68 #else /* CONFIG_BROKEN_GAS_INST */
69
70 #ifndef CONFIG_CPU_BIG_ENDIAN
71 #define __INSTR_BSWAP(x) (x)
72 #else /* CONFIG_CPU_BIG_ENDIAN */
73 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
74 (((x) << 8) & 0x00ff0000) | \
75 (((x) >> 8) & 0x0000ff00) | \
76 (((x) >> 24) & 0x000000ff))
77 #endif /* CONFIG_CPU_BIG_ENDIAN */
78
79 #ifdef __ASSEMBLY__
80 #define __emit_inst(x) .long __INSTR_BSWAP(x)
81 #else /* __ASSEMBLY__ */
82 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
83 #endif /* __ASSEMBLY__ */
84
85 #endif /* CONFIG_BROKEN_GAS_INST */
86
87 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
88 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
89
90 #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
91 (!!x)<<8 | 0x1f)
92 #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
93 (!!x)<<8 | 0x1f)
94
95 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
96 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
97 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
98
99 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
100 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
101 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
102 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
103 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
104 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
105 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
106 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
107 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
108 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
109 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
110 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
111 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
112 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
113 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
114 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
115 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
116 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
117 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
118 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
119 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
120 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
121
122 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
123 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
124 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
125
126 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
127 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
128 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
129 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
130 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
131 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
132 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
133 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
134
135 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
136 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
137 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
138 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
139 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
140 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
141 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
142
143 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
144 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
145 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
146
147 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
148 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
149 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
150
151 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
152 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
153
154 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
155 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
156
157 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
158 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
159
160 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
161 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
162 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
163
164 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
165 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
166 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
167
168 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
169
170 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
171 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
172 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
173
174 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
175
176 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
177 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
178 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
179
180 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
181 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
182 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
183 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
184 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
185 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
186 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
187 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
188
189 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
190 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
191
192 /*** Statistical Profiling Extension ***/
193 /* ID registers */
194 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
195 #define SYS_PMSIDR_EL1_FE_SHIFT 0
196 #define SYS_PMSIDR_EL1_FT_SHIFT 1
197 #define SYS_PMSIDR_EL1_FL_SHIFT 2
198 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3
199 #define SYS_PMSIDR_EL1_LDS_SHIFT 4
200 #define SYS_PMSIDR_EL1_ERND_SHIFT 5
201 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8
202 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL
203 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
204 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL
205 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16
206 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL
207
208 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
209 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0
210 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU
211 #define SYS_PMBIDR_EL1_P_SHIFT 4
212 #define SYS_PMBIDR_EL1_F_SHIFT 5
213
214 /* Sampling controls */
215 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
216 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0
217 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1
218 #define SYS_PMSCR_EL1_CX_SHIFT 3
219 #define SYS_PMSCR_EL1_PA_SHIFT 4
220 #define SYS_PMSCR_EL1_TS_SHIFT 5
221 #define SYS_PMSCR_EL1_PCT_SHIFT 6
222
223 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
224 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0
225 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1
226 #define SYS_PMSCR_EL2_CX_SHIFT 3
227 #define SYS_PMSCR_EL2_PA_SHIFT 4
228 #define SYS_PMSCR_EL2_TS_SHIFT 5
229 #define SYS_PMSCR_EL2_PCT_SHIFT 6
230
231 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
232
233 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
234 #define SYS_PMSIRR_EL1_RND_SHIFT 0
235 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8
236 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL
237
238 /* Filtering controls */
239 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
240 #define SYS_PMSFCR_EL1_FE_SHIFT 0
241 #define SYS_PMSFCR_EL1_FT_SHIFT 1
242 #define SYS_PMSFCR_EL1_FL_SHIFT 2
243 #define SYS_PMSFCR_EL1_B_SHIFT 16
244 #define SYS_PMSFCR_EL1_LD_SHIFT 17
245 #define SYS_PMSFCR_EL1_ST_SHIFT 18
246
247 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
248 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL
249
250 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
251 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
252
253 /* Buffer controls */
254 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
255 #define SYS_PMBLIMITR_EL1_E_SHIFT 0
256 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1
257 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL
258 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
259
260 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
261
262 /* Buffer error reporting */
263 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
264 #define SYS_PMBSR_EL1_COLL_SHIFT 16
265 #define SYS_PMBSR_EL1_S_SHIFT 17
266 #define SYS_PMBSR_EL1_EA_SHIFT 18
267 #define SYS_PMBSR_EL1_DL_SHIFT 19
268 #define SYS_PMBSR_EL1_EC_SHIFT 26
269 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL
270
271 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
272 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
273 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
274
275 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0
276 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
277
278 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0
279 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL
280
281 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
282
283 /*** End of Statistical Profiling Extension ***/
284
285 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
286 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
287
288 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
289 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
290
291 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
292 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
293
294 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
295 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
296 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
297 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
298 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
299 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
300 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
301 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
302 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
303 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
304 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
305 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
306 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
307 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
308 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
309 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
310 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
311 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
312 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
313 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
314 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
315 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
316 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
317 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
318 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
319
320 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
321 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
322
323 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
324
325 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
326 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
327
328 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
329
330 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
331 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
332
333 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
334 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
335 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
336 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
337 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
338 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
339 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
340 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
341 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
342 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
343 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
344 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
345 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
346
347 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
348 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
349
350 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
351
352 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
353 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
354 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
355
356 #define __PMEV_op2(n) ((n) & 0x7)
357 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
358 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
359 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
360 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
361
362 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7)
363
364 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
365
366 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
367 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
368 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
369 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
370
371 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
372 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
373 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
374 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
375 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
376 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
377
378 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
379 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
380 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
381 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
382 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
383
384 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
385 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
386 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
387 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
388 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
389 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
390 #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
391 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
392
393 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
394 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
395 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
396 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
397 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
398 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
399 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
400 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
401 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
402
403 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
404 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
405 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
406 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
407 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
408 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
409 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
410 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
411 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
412
413 /* Common SCTLR_ELx flags. */
414 #define SCTLR_ELx_EE (1 << 25)
415 #define SCTLR_ELx_IESB (1 << 21)
416 #define SCTLR_ELx_WXN (1 << 19)
417 #define SCTLR_ELx_I (1 << 12)
418 #define SCTLR_ELx_SA (1 << 3)
419 #define SCTLR_ELx_C (1 << 2)
420 #define SCTLR_ELx_A (1 << 1)
421 #define SCTLR_ELx_M 1
422
423 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
424 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
425
426 /* SCTLR_EL2 specific flags. */
427 #define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \
428 (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \
429 (1 << 29))
430 #define SCTLR_EL2_RES0 ((1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | \
431 (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \
432 (1 << 17) | (1 << 20) | (1 << 24) | (1 << 26) | \
433 (1 << 27) | (1 << 30) | (1 << 31))
434
435 #ifdef CONFIG_CPU_BIG_ENDIAN
436 #define ENDIAN_SET_EL2 SCTLR_ELx_EE
437 #define ENDIAN_CLEAR_EL2 0
438 #else
439 #define ENDIAN_SET_EL2 0
440 #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE
441 #endif
442
443 /* SCTLR_EL2 value used for the hyp-stub */
444 #define SCTLR_EL2_SET (SCTLR_ELx_IESB | ENDIAN_SET_EL2 | SCTLR_EL2_RES1)
445 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
446 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \
447 ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
448
449 /* Check all the bits are accounted for */
450 #define SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS BUILD_BUG_ON((SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != ~0)
451
452
453 /* SCTLR_EL1 specific flags. */
454 #define SCTLR_EL1_UCI (1 << 26)
455 #define SCTLR_EL1_E0E (1 << 24)
456 #define SCTLR_EL1_SPAN (1 << 23)
457 #define SCTLR_EL1_NTWE (1 << 18)
458 #define SCTLR_EL1_NTWI (1 << 16)
459 #define SCTLR_EL1_UCT (1 << 15)
460 #define SCTLR_EL1_DZE (1 << 14)
461 #define SCTLR_EL1_UMA (1 << 9)
462 #define SCTLR_EL1_SED (1 << 8)
463 #define SCTLR_EL1_ITD (1 << 7)
464 #define SCTLR_EL1_CP15BEN (1 << 5)
465 #define SCTLR_EL1_SA0 (1 << 4)
466
467 #define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \
468 (1 << 29))
469 #define SCTLR_EL1_RES0 ((1 << 6) | (1 << 10) | (1 << 13) | (1 << 17) | \
470 (1 << 27) | (1 << 30) | (1 << 31))
471
472 #ifdef CONFIG_CPU_BIG_ENDIAN
473 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
474 #define ENDIAN_CLEAR_EL1 0
475 #else
476 #define ENDIAN_SET_EL1 0
477 #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
478 #endif
479
480 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\
481 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\
482 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_NTWI |\
483 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
484 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1)
485 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\
486 SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\
487 SCTLR_EL1_RES0)
488
489 /* Check all the bits are accounted for */
490 #define SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS BUILD_BUG_ON((SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != ~0)
491
492 /* id_aa64isar0 */
493 #define ID_AA64ISAR0_FHM_SHIFT 48
494 #define ID_AA64ISAR0_DP_SHIFT 44
495 #define ID_AA64ISAR0_SM4_SHIFT 40
496 #define ID_AA64ISAR0_SM3_SHIFT 36
497 #define ID_AA64ISAR0_SHA3_SHIFT 32
498 #define ID_AA64ISAR0_RDM_SHIFT 28
499 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
500 #define ID_AA64ISAR0_CRC32_SHIFT 16
501 #define ID_AA64ISAR0_SHA2_SHIFT 12
502 #define ID_AA64ISAR0_SHA1_SHIFT 8
503 #define ID_AA64ISAR0_AES_SHIFT 4
504
505 /* id_aa64isar1 */
506 #define ID_AA64ISAR1_LRCPC_SHIFT 20
507 #define ID_AA64ISAR1_FCMA_SHIFT 16
508 #define ID_AA64ISAR1_JSCVT_SHIFT 12
509 #define ID_AA64ISAR1_DPB_SHIFT 0
510
511 /* id_aa64pfr0 */
512 #define ID_AA64PFR0_CSV3_SHIFT 60
513 #define ID_AA64PFR0_CSV2_SHIFT 56
514 #define ID_AA64PFR0_SVE_SHIFT 32
515 #define ID_AA64PFR0_RAS_SHIFT 28
516 #define ID_AA64PFR0_GIC_SHIFT 24
517 #define ID_AA64PFR0_ASIMD_SHIFT 20
518 #define ID_AA64PFR0_FP_SHIFT 16
519 #define ID_AA64PFR0_EL3_SHIFT 12
520 #define ID_AA64PFR0_EL2_SHIFT 8
521 #define ID_AA64PFR0_EL1_SHIFT 4
522 #define ID_AA64PFR0_EL0_SHIFT 0
523
524 #define ID_AA64PFR0_SVE 0x1
525 #define ID_AA64PFR0_RAS_V1 0x1
526 #define ID_AA64PFR0_FP_NI 0xf
527 #define ID_AA64PFR0_FP_SUPPORTED 0x0
528 #define ID_AA64PFR0_ASIMD_NI 0xf
529 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
530 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
531 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
532 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
533
534 /* id_aa64mmfr0 */
535 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
536 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
537 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
538 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
539 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
540 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
541 #define ID_AA64MMFR0_ASID_SHIFT 4
542 #define ID_AA64MMFR0_PARANGE_SHIFT 0
543
544 #define ID_AA64MMFR0_TGRAN4_NI 0xf
545 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
546 #define ID_AA64MMFR0_TGRAN64_NI 0xf
547 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
548 #define ID_AA64MMFR0_TGRAN16_NI 0x0
549 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
550 #define ID_AA64MMFR0_PARANGE_48 0x5
551 #define ID_AA64MMFR0_PARANGE_52 0x6
552
553 #ifdef CONFIG_ARM64_PA_BITS_52
554 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52
555 #else
556 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48
557 #endif
558
559 /* id_aa64mmfr1 */
560 #define ID_AA64MMFR1_PAN_SHIFT 20
561 #define ID_AA64MMFR1_LOR_SHIFT 16
562 #define ID_AA64MMFR1_HPD_SHIFT 12
563 #define ID_AA64MMFR1_VHE_SHIFT 8
564 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
565 #define ID_AA64MMFR1_HADBS_SHIFT 0
566
567 #define ID_AA64MMFR1_VMIDBITS_8 0
568 #define ID_AA64MMFR1_VMIDBITS_16 2
569
570 /* id_aa64mmfr2 */
571 #define ID_AA64MMFR2_LVA_SHIFT 16
572 #define ID_AA64MMFR2_IESB_SHIFT 12
573 #define ID_AA64MMFR2_LSM_SHIFT 8
574 #define ID_AA64MMFR2_UAO_SHIFT 4
575 #define ID_AA64MMFR2_CNP_SHIFT 0
576
577 /* id_aa64dfr0 */
578 #define ID_AA64DFR0_PMSVER_SHIFT 32
579 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
580 #define ID_AA64DFR0_WRPS_SHIFT 20
581 #define ID_AA64DFR0_BRPS_SHIFT 12
582 #define ID_AA64DFR0_PMUVER_SHIFT 8
583 #define ID_AA64DFR0_TRACEVER_SHIFT 4
584 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
585
586 #define ID_ISAR5_RDM_SHIFT 24
587 #define ID_ISAR5_CRC32_SHIFT 16
588 #define ID_ISAR5_SHA2_SHIFT 12
589 #define ID_ISAR5_SHA1_SHIFT 8
590 #define ID_ISAR5_AES_SHIFT 4
591 #define ID_ISAR5_SEVL_SHIFT 0
592
593 #define MVFR0_FPROUND_SHIFT 28
594 #define MVFR0_FPSHVEC_SHIFT 24
595 #define MVFR0_FPSQRT_SHIFT 20
596 #define MVFR0_FPDIVIDE_SHIFT 16
597 #define MVFR0_FPTRAP_SHIFT 12
598 #define MVFR0_FPDP_SHIFT 8
599 #define MVFR0_FPSP_SHIFT 4
600 #define MVFR0_SIMD_SHIFT 0
601
602 #define MVFR1_SIMDFMAC_SHIFT 28
603 #define MVFR1_FPHP_SHIFT 24
604 #define MVFR1_SIMDHP_SHIFT 20
605 #define MVFR1_SIMDSP_SHIFT 16
606 #define MVFR1_SIMDINT_SHIFT 12
607 #define MVFR1_SIMDLS_SHIFT 8
608 #define MVFR1_FPDNAN_SHIFT 4
609 #define MVFR1_FPFTZ_SHIFT 0
610
611
612 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
613 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
614 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
615
616 #define ID_AA64MMFR0_TGRAN4_NI 0xf
617 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
618 #define ID_AA64MMFR0_TGRAN64_NI 0xf
619 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
620 #define ID_AA64MMFR0_TGRAN16_NI 0x0
621 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
622
623 #if defined(CONFIG_ARM64_4K_PAGES)
624 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
625 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
626 #elif defined(CONFIG_ARM64_16K_PAGES)
627 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
628 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
629 #elif defined(CONFIG_ARM64_64K_PAGES)
630 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
631 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
632 #endif
633
634
635 /*
636 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
637 * are reserved by the SVE architecture for future expansion of the LEN
638 * field, with compatible semantics.
639 */
640 #define ZCR_ELx_LEN_SHIFT 0
641 #define ZCR_ELx_LEN_SIZE 9
642 #define ZCR_ELx_LEN_MASK 0x1ff
643
644 #define CPACR_EL1_ZEN_EL1EN (1 << 16) /* enable EL1 access */
645 #define CPACR_EL1_ZEN_EL0EN (1 << 17) /* enable EL0 access, if EL1EN set */
646 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
647
648
649 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
650 #define SYS_MPIDR_SAFE_VAL (1UL << 31)
651
652 #ifdef __ASSEMBLY__
653
654 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
655 .equ .L__reg_num_x\num, \num
656 .endr
657 .equ .L__reg_num_xzr, 31
658
659 .macro mrs_s, rt, sreg
660 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
661 .endm
662
663 .macro msr_s, sreg, rt
664 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
665 .endm
666
667 #else
668
669 #include <linux/build_bug.h>
670 #include <linux/types.h>
671
672 asm(
673 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
674 " .equ .L__reg_num_x\\num, \\num\n"
675 " .endr\n"
676 " .equ .L__reg_num_xzr, 31\n"
677 "\n"
678 " .macro mrs_s, rt, sreg\n"
679 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))
680 " .endm\n"
681 "\n"
682 " .macro msr_s, sreg, rt\n"
683 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))
684 " .endm\n"
685 );
686
687 /*
688 * Unlike read_cpuid, calls to read_sysreg are never expected to be
689 * optimized away or replaced with synthetic values.
690 */
691 #define read_sysreg(r) ({ \
692 u64 __val; \
693 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
694 __val; \
695 })
696
697 /*
698 * The "Z" constraint normally means a zero immediate, but when combined with
699 * the "%x0" template means XZR.
700 */
701 #define write_sysreg(v, r) do { \
702 u64 __val = (u64)(v); \
703 asm volatile("msr " __stringify(r) ", %x0" \
704 : : "rZ" (__val)); \
705 } while (0)
706
707 /*
708 * For registers without architectural names, or simply unsupported by
709 * GAS.
710 */
711 #define read_sysreg_s(r) ({ \
712 u64 __val; \
713 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \
714 __val; \
715 })
716
717 #define write_sysreg_s(v, r) do { \
718 u64 __val = (u64)(v); \
719 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \
720 } while (0)
721
722 static inline void config_sctlr_el1(u32 clear, u32 set)
723 {
724 u32 val;
725
726 SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS;
727 SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS;
728
729 val = read_sysreg(sctlr_el1);
730 val &= ~clear;
731 val |= set;
732 write_sysreg(val, sctlr_el1);
733 }
734
735 #endif
736
737 #endif /* __ASM_SYSREG_H */
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