2 * Blackfin architecture-dependent process handling
4 * Copyright 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later
9 #include <linux/module.h>
10 #include <linux/unistd.h>
11 #include <linux/user.h>
12 #include <linux/uaccess.h>
13 #include <linux/slab.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/task_stack.h>
18 #include <linux/mm_types.h>
19 #include <linux/tick.h>
21 #include <linux/err.h>
23 #include <asm/blackfin.h>
24 #include <asm/fixed_code.h>
25 #include <asm/mem_map.h>
28 asmlinkage
void ret_from_fork(void);
30 /* Points to the SDRAM backup memory for the stack that is currently in
31 * L1 scratchpad memory.
33 void *current_l1_stack_save
;
35 /* The number of tasks currently using a L1 stack area. The SRAM is
36 * allocated/deallocated whenever this changes from/to zero.
40 /* Start and length of the area in L1 scratchpad memory which we've allocated
44 unsigned long l1_stack_len
;
46 void (*pm_power_off
)(void) = NULL
;
47 EXPORT_SYMBOL(pm_power_off
);
50 * The idle loop on BFIN
53 void arch_cpu_idle(void)__attribute__((l1_text
));
57 * This is our default idle handler. We need to disable
58 * interrupts here to ensure we don't miss a wakeup call.
60 void arch_cpu_idle(void)
63 ipipe_suspend_domain();
65 hard_local_irq_disable();
67 idle_with_irq_disabled();
69 hard_local_irq_enable();
72 #ifdef CONFIG_HOTPLUG_CPU
73 void arch_cpu_idle_dead(void)
80 * Do necessary setup to start up a newly executed thread.
82 * pass the data segment into user programs if it exists,
83 * it can't hurt anything as far as I can tell
85 void start_thread(struct pt_regs
*regs
, unsigned long new_ip
, unsigned long new_sp
)
89 regs
->p5
= current
->mm
->start_data
;
91 task_thread_info(current
)->l1_task_info
.stack_start
=
92 (void *)current
->mm
->context
.stack_start
;
93 task_thread_info(current
)->l1_task_info
.lowest_sp
= (void *)new_sp
;
94 memcpy(L1_SCRATCH_TASK_INFO
, &task_thread_info(current
)->l1_task_info
,
95 sizeof(*L1_SCRATCH_TASK_INFO
));
99 EXPORT_SYMBOL_GPL(start_thread
);
101 void flush_thread(void)
105 asmlinkage
int bfin_clone(unsigned long clone_flags
, unsigned long newsp
)
107 #ifdef __ARCH_SYNC_CORE_DCACHE
108 if (current
->nr_cpus_allowed
== num_possible_cpus())
109 set_cpus_allowed_ptr(current
, cpumask_of(smp_processor_id()));
113 return do_fork(clone_flags
, newsp
, 0, NULL
, NULL
);
117 copy_thread(unsigned long clone_flags
,
118 unsigned long usp
, unsigned long topstk
,
119 struct task_struct
*p
)
121 struct pt_regs
*childregs
;
124 childregs
= (struct pt_regs
*) (task_stack_page(p
) + THREAD_SIZE
) - 1;
125 v
= ((unsigned long *)childregs
) - 2;
126 if (unlikely(p
->flags
& PF_KTHREAD
)) {
127 memset(childregs
, 0, sizeof(struct pt_regs
));
130 childregs
->orig_p0
= -1;
131 childregs
->ipend
= 0x8000;
132 __asm__
__volatile__("%0 = syscfg;":"=da"(childregs
->syscfg
):);
135 *childregs
= *current_pt_regs();
137 p
->thread
.usp
= usp
? : rdusp();
141 p
->thread
.ksp
= (unsigned long)v
;
142 p
->thread
.pc
= (unsigned long)ret_from_fork
;
147 unsigned long get_wchan(struct task_struct
*p
)
149 unsigned long fp
, pc
;
150 unsigned long stack_page
;
152 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
155 stack_page
= (unsigned long)p
;
158 if (fp
< stack_page
+ sizeof(struct thread_info
) ||
159 fp
>= 8184 + stack_page
)
161 pc
= ((unsigned long *)fp
)[1];
162 if (!in_sched_functions(pc
))
164 fp
= *(unsigned long *)fp
;
166 while (count
++ < 16);
170 void finish_atomic_sections (struct pt_regs
*regs
)
172 int __user
*up0
= (int __user
*)regs
->p0
;
176 /* not in middle of an atomic step, so resume like normal */
179 case ATOMIC_XCHG32
+ 2:
180 put_user(regs
->r1
, up0
);
183 case ATOMIC_CAS32
+ 2:
184 case ATOMIC_CAS32
+ 4:
185 if (regs
->r0
== regs
->r1
)
186 case ATOMIC_CAS32
+ 6:
187 put_user(regs
->r2
, up0
);
190 case ATOMIC_ADD32
+ 2:
191 regs
->r0
= regs
->r1
+ regs
->r0
;
193 case ATOMIC_ADD32
+ 4:
194 put_user(regs
->r0
, up0
);
197 case ATOMIC_SUB32
+ 2:
198 regs
->r0
= regs
->r1
- regs
->r0
;
200 case ATOMIC_SUB32
+ 4:
201 put_user(regs
->r0
, up0
);
204 case ATOMIC_IOR32
+ 2:
205 regs
->r0
= regs
->r1
| regs
->r0
;
207 case ATOMIC_IOR32
+ 4:
208 put_user(regs
->r0
, up0
);
211 case ATOMIC_AND32
+ 2:
212 regs
->r0
= regs
->r1
& regs
->r0
;
214 case ATOMIC_AND32
+ 4:
215 put_user(regs
->r0
, up0
);
218 case ATOMIC_XOR32
+ 2:
219 regs
->r0
= regs
->r1
^ regs
->r0
;
221 case ATOMIC_XOR32
+ 4:
222 put_user(regs
->r0
, up0
);
227 * We've finished the atomic section, and the only thing left for
228 * userspace is to do a RTS, so we might as well handle that too
229 * since we need to update the PC anyways.
231 regs
->pc
= regs
->rets
;
235 int in_mem(unsigned long addr
, unsigned long size
,
236 unsigned long start
, unsigned long end
)
238 return addr
>= start
&& addr
+ size
<= end
;
241 int in_mem_const_off(unsigned long addr
, unsigned long size
, unsigned long off
,
242 unsigned long const_addr
, unsigned long const_size
)
245 in_mem(addr
, size
, const_addr
+ off
, const_addr
+ const_size
);
248 int in_mem_const(unsigned long addr
, unsigned long size
,
249 unsigned long const_addr
, unsigned long const_size
)
251 return in_mem_const_off(addr
, size
, 0, const_addr
, const_size
);
254 #define ASYNC_ENABLED(bnum, bctlnum) 1
256 #define ASYNC_ENABLED(bnum, bctlnum) \
258 (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
259 bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
264 * We can't read EBIU banks that aren't enabled or we end up hanging
265 * on the access to the async space. Make sure we validate accesses
266 * that cross async banks too.
267 * 0 - found, but unusable
272 int in_async(unsigned long addr
, unsigned long size
)
274 if (addr
>= ASYNC_BANK0_BASE
&& addr
< ASYNC_BANK0_BASE
+ ASYNC_BANK0_SIZE
) {
275 if (!ASYNC_ENABLED(0, 0))
277 if (addr
+ size
<= ASYNC_BANK0_BASE
+ ASYNC_BANK0_SIZE
)
279 size
-= ASYNC_BANK0_BASE
+ ASYNC_BANK0_SIZE
- addr
;
280 addr
= ASYNC_BANK0_BASE
+ ASYNC_BANK0_SIZE
;
282 if (addr
>= ASYNC_BANK1_BASE
&& addr
< ASYNC_BANK1_BASE
+ ASYNC_BANK1_SIZE
) {
283 if (!ASYNC_ENABLED(1, 0))
285 if (addr
+ size
<= ASYNC_BANK1_BASE
+ ASYNC_BANK1_SIZE
)
287 size
-= ASYNC_BANK1_BASE
+ ASYNC_BANK1_SIZE
- addr
;
288 addr
= ASYNC_BANK1_BASE
+ ASYNC_BANK1_SIZE
;
290 if (addr
>= ASYNC_BANK2_BASE
&& addr
< ASYNC_BANK2_BASE
+ ASYNC_BANK2_SIZE
) {
291 if (!ASYNC_ENABLED(2, 1))
293 if (addr
+ size
<= ASYNC_BANK2_BASE
+ ASYNC_BANK2_SIZE
)
295 size
-= ASYNC_BANK2_BASE
+ ASYNC_BANK2_SIZE
- addr
;
296 addr
= ASYNC_BANK2_BASE
+ ASYNC_BANK2_SIZE
;
298 if (addr
>= ASYNC_BANK3_BASE
&& addr
< ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
) {
299 if (ASYNC_ENABLED(3, 1))
301 if (addr
+ size
<= ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
)
306 /* not within async bounds */
310 int bfin_mem_access_type(unsigned long addr
, unsigned long size
)
312 int cpu
= raw_smp_processor_id();
314 /* Check that things do not wrap around */
315 if (addr
> ULONG_MAX
- size
)
318 if (in_mem(addr
, size
, FIXED_CODE_START
, physical_mem_end
))
319 return BFIN_MEM_ACCESS_CORE
;
321 if (in_mem_const(addr
, size
, L1_CODE_START
, L1_CODE_LENGTH
))
322 return cpu
== 0 ? BFIN_MEM_ACCESS_ITEST
: BFIN_MEM_ACCESS_IDMA
;
323 if (in_mem_const(addr
, size
, L1_SCRATCH_START
, L1_SCRATCH_LENGTH
))
324 return cpu
== 0 ? BFIN_MEM_ACCESS_CORE_ONLY
: -EFAULT
;
325 if (in_mem_const(addr
, size
, L1_DATA_A_START
, L1_DATA_A_LENGTH
))
326 return cpu
== 0 ? BFIN_MEM_ACCESS_CORE
: BFIN_MEM_ACCESS_IDMA
;
327 if (in_mem_const(addr
, size
, L1_DATA_B_START
, L1_DATA_B_LENGTH
))
328 return cpu
== 0 ? BFIN_MEM_ACCESS_CORE
: BFIN_MEM_ACCESS_IDMA
;
329 #ifdef COREB_L1_CODE_START
330 if (in_mem_const(addr
, size
, COREB_L1_CODE_START
, COREB_L1_CODE_LENGTH
))
331 return cpu
== 1 ? BFIN_MEM_ACCESS_ITEST
: BFIN_MEM_ACCESS_IDMA
;
332 if (in_mem_const(addr
, size
, COREB_L1_SCRATCH_START
, L1_SCRATCH_LENGTH
))
333 return cpu
== 1 ? BFIN_MEM_ACCESS_CORE_ONLY
: -EFAULT
;
334 if (in_mem_const(addr
, size
, COREB_L1_DATA_A_START
, COREB_L1_DATA_A_LENGTH
))
335 return cpu
== 1 ? BFIN_MEM_ACCESS_CORE
: BFIN_MEM_ACCESS_IDMA
;
336 if (in_mem_const(addr
, size
, COREB_L1_DATA_B_START
, COREB_L1_DATA_B_LENGTH
))
337 return cpu
== 1 ? BFIN_MEM_ACCESS_CORE
: BFIN_MEM_ACCESS_IDMA
;
339 if (in_mem_const(addr
, size
, L2_START
, L2_LENGTH
))
340 return BFIN_MEM_ACCESS_CORE
;
342 if (addr
>= SYSMMR_BASE
)
343 return BFIN_MEM_ACCESS_CORE_ONLY
;
345 switch (in_async(addr
, size
)) {
346 case 0: return -EFAULT
;
347 case 1: return BFIN_MEM_ACCESS_CORE
;
348 case 2: /* fall through */;
351 if (in_mem_const(addr
, size
, BOOT_ROM_START
, BOOT_ROM_LENGTH
))
352 return BFIN_MEM_ACCESS_CORE
;
353 if (in_mem_const(addr
, size
, L1_ROM_START
, L1_ROM_LENGTH
))
354 return BFIN_MEM_ACCESS_DMA
;
359 #if defined(CONFIG_ACCESS_CHECK)
360 #ifdef CONFIG_ACCESS_OK_L1
361 __attribute__((l1_text
))
363 /* Return 1 if access to memory range is OK, 0 otherwise */
364 int _access_ok(unsigned long addr
, unsigned long size
)
370 /* Check that things do not wrap around */
371 if (addr
> ULONG_MAX
- size
)
373 if (uaccess_kernel())
375 #ifdef CONFIG_MTD_UCLINUX
381 if (in_mem(addr
, size
, memory_start
, memory_end
))
383 if (in_mem(addr
, size
, memory_mtd_end
, physical_mem_end
))
385 # ifndef CONFIG_ROMFS_ON_MTD
388 /* For XIP, allow user space to use pointers within the ROMFS. */
389 if (in_mem(addr
, size
, memory_mtd_start
, memory_mtd_end
))
392 if (in_mem(addr
, size
, memory_start
, physical_mem_end
))
396 if (in_mem(addr
, size
, (unsigned long)__init_begin
, (unsigned long)__init_end
))
399 if (in_mem_const(addr
, size
, L1_CODE_START
, L1_CODE_LENGTH
))
401 if (in_mem_const_off(addr
, size
, _etext_l1
- _stext_l1
, L1_CODE_START
, L1_CODE_LENGTH
))
403 if (in_mem_const_off(addr
, size
, _ebss_l1
- _sdata_l1
, L1_DATA_A_START
, L1_DATA_A_LENGTH
))
405 if (in_mem_const_off(addr
, size
, _ebss_b_l1
- _sdata_b_l1
, L1_DATA_B_START
, L1_DATA_B_LENGTH
))
407 #ifdef COREB_L1_CODE_START
408 if (in_mem_const(addr
, size
, COREB_L1_CODE_START
, COREB_L1_CODE_LENGTH
))
410 if (in_mem_const(addr
, size
, COREB_L1_SCRATCH_START
, L1_SCRATCH_LENGTH
))
412 if (in_mem_const(addr
, size
, COREB_L1_DATA_A_START
, COREB_L1_DATA_A_LENGTH
))
414 if (in_mem_const(addr
, size
, COREB_L1_DATA_B_START
, COREB_L1_DATA_B_LENGTH
))
418 #ifndef CONFIG_EXCEPTION_L1_SCRATCH
419 if (in_mem_const(addr
, size
, (unsigned long)l1_stack_base
, l1_stack_len
))
423 aret
= in_async(addr
, size
);
427 if (in_mem_const_off(addr
, size
, _ebss_l2
- _stext_l2
, L2_START
, L2_LENGTH
))
430 if (in_mem_const(addr
, size
, BOOT_ROM_START
, BOOT_ROM_LENGTH
))
432 if (in_mem_const(addr
, size
, L1_ROM_START
, L1_ROM_LENGTH
))
437 EXPORT_SYMBOL(_access_ok
);
438 #endif /* CONFIG_ACCESS_CHECK */