arch/cris/include/uapi/asm/etraxgpio.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * The following devices are accessible using this driver using
   4  * GPIO_MAJOR (120) and a couple of minor numbers.
   5  *
   6  * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):
   7  * /dev/gpioa  minor 0, 8 bit GPIO, each bit can change direction
   8  * /dev/gpiob  minor 1, 8 bit GPIO, each bit can change direction
   9  * /dev/leds   minor 2, Access to leds depending on kernelconfig
  10  * /dev/gpiog  minor 3
  11  *       g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG
  12  *       g1-g7 and g25-g31 is both input and outputs but on different pins
  13  *       Also note that some bits change pins depending on what interfaces
  14  *       are enabled.
  15  */
  16 #ifndef _ASM_ETRAXGPIO_H
  17 #define _ASM_ETRAXGPIO_H
  18
  19 #define GPIO_MINOR_FIRST 0
  20
  21 #define ETRAXGPIO_IOCTYPE 43
  22
  23 /* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
  24 #define GPIO_MINOR_A 0
  25 #define GPIO_MINOR_B 1
  26 #define GPIO_MINOR_LEDS 2
  27 #define GPIO_MINOR_G 3
  28 #define GPIO_MINOR_LAST 3
  29 #define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
  30
  31
  32 /* supported ioctl _IOC_NR's */
  33
  34 #define IO_READBITS  0x1  /* read and return current port bits (obsolete) */
  35 #define IO_SETBITS   0x2  /* set the bits marked by 1 in the argument */
  36 #define IO_CLRBITS   0x3  /* clear the bits marked by 1 in the argument */
  37
  38 /* the alarm is waited for by select() */
  39
  40 #define IO_HIGHALARM 0x4  /* set alarm on high for bits marked by 1 */
  41 #define IO_LOWALARM  0x5  /* set alarm on low for bits marked by 1 */
  42 #define IO_CLRALARM  0x6  /* clear alarm for bits marked by 1 */
  43
  44 /* LED ioctl */
  45 #define IO_LEDACTIVE_SET 0x7 /* set active led
  46                               * 0=off, 1=green, 2=red, 3=yellow */
  47
  48 /* GPIO direction ioctl's */
  49 #define IO_READDIR    0x8  /* Read direction 0=input 1=output  (obsolete) */
  50 #define IO_SETINPUT   0x9  /* Set direction for bits set, 0=unchanged 1=input,
  51                               returns mask with current inputs (obsolete) */
  52 #define IO_SETOUTPUT  0xA  /* Set direction for bits set, 0=unchanged 1=output,
  53                               returns mask with current outputs (obsolete)*/
  54
  55 /* LED ioctl extended */
  56 #define IO_LED_SETBIT 0xB
  57 #define IO_LED_CLRBIT 0xC
  58
  59 /* SHUTDOWN ioctl */
  60 #define IO_SHUTDOWN   0xD
  61 #define IO_GET_PWR_BT 0xE
  62
  63 /* Bit toggling in driver settings */
  64 /* bit set in low byte0 is CLK mask (0x00FF),
  65    bit set in byte1 is DATA mask    (0xFF00)
  66    msb, data_mask[7:0] , clk_mask[7:0]
  67  */
  68 #define IO_CFG_WRITE_MODE 0xF
  69 #define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \
  70         ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) )
  71
  72 /* The following 4 ioctl's take a pointer as argument and handles
  73  * 32 bit ports (port G) properly.
  74  * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT
  75  */
  76 #define IO_READ_INBITS   0x10 /* *arg is result of reading the input pins */
  77 #define IO_READ_OUTBITS  0x11 /* *arg is result of reading the output shadow */
  78 #define IO_SETGET_INPUT  0x12 /* bits set in *arg is set to input, */
  79                               /* *arg updated with current input pins. */
  80 #define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
  81                               /* *arg updated with current output pins. */
  82
  83 #endif