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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / arch / mips / alchemy / devboards / db1200.c
blobda76637704253e3610f4f15b69a42e75af99d516
1 /*
2 * DBAu1200/PBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008-2011 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #include <linux/clk.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/gpio.h>
24 #include <linux/i2c.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/leds.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/rawnand.h>
33 #include <linux/mtd/partitions.h>
34 #include <linux/platform_device.h>
35 #include <linux/serial_8250.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/flash.h>
38 #include <linux/smc91x.h>
39 #include <linux/ata_platform.h>
40 #include <asm/mach-au1x00/au1000.h>
41 #include <asm/mach-au1x00/au1100_mmc.h>
42 #include <asm/mach-au1x00/au1xxx_dbdma.h>
43 #include <asm/mach-au1x00/au1xxx_psc.h>
44 #include <asm/mach-au1x00/au1200fb.h>
45 #include <asm/mach-au1x00/au1550_spi.h>
46 #include <asm/mach-db1x00/bcsr.h>
47
48 #include "platform.h"
49
50 #define BCSR_INT_IDE 0x0001
51 #define BCSR_INT_ETH 0x0002
52 #define BCSR_INT_PC0 0x0004
53 #define BCSR_INT_PC0STSCHG 0x0008
54 #define BCSR_INT_PC1 0x0010
55 #define BCSR_INT_PC1STSCHG 0x0020
56 #define BCSR_INT_DC 0x0040
57 #define BCSR_INT_FLASHBUSY 0x0080
58 #define BCSR_INT_PC0INSERT 0x0100
59 #define BCSR_INT_PC0EJECT 0x0200
60 #define BCSR_INT_PC1INSERT 0x0400
61 #define BCSR_INT_PC1EJECT 0x0800
62 #define BCSR_INT_SD0INSERT 0x1000
63 #define BCSR_INT_SD0EJECT 0x2000
64 #define BCSR_INT_SD1INSERT 0x4000
65 #define BCSR_INT_SD1EJECT 0x8000
66
67 #define DB1200_IDE_PHYS_ADDR 0x18800000
68 #define DB1200_IDE_REG_SHIFT 5
69 #define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT)
70 #define DB1200_ETH_PHYS_ADDR 0x19000300
71 #define DB1200_NAND_PHYS_ADDR 0x20000000
72
73 #define PB1200_IDE_PHYS_ADDR 0x0C800000
74 #define PB1200_ETH_PHYS_ADDR 0x0D000300
75 #define PB1200_NAND_PHYS_ADDR 0x1C000000
76
77 #define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1)
78 #define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
79 #define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
80 #define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
81 #define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
82 #define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
83 #define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
84 #define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
85 #define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
86 #define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
87 #define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
88 #define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
89 #define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
90 #define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
91 #define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
92 #define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14)
93 #define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15)
94 #define DB1200_INT_END (DB1200_INT_BEGIN + 15)
95
96 const char *get_system_type(void);
97
98 static int __init db1200_detect_board(void)
99 {
100 int bid;
101
102 /* try the DB1200 first */
103 bcsr_init(DB1200_BCSR_PHYS_ADDR,
104 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
105 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
106 unsigned short t = bcsr_read(BCSR_HEXLEDS);
107 bcsr_write(BCSR_HEXLEDS, ~t);
108 if (bcsr_read(BCSR_HEXLEDS) != t) {
109 bcsr_write(BCSR_HEXLEDS, t);
110 return 0;
111 }
112 }
113
114 /* okay, try the PB1200 then */
115 bcsr_init(PB1200_BCSR_PHYS_ADDR,
116 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
117 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
118 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
119 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
120 unsigned short t = bcsr_read(BCSR_HEXLEDS);
121 bcsr_write(BCSR_HEXLEDS, ~t);
122 if (bcsr_read(BCSR_HEXLEDS) != t) {
123 bcsr_write(BCSR_HEXLEDS, t);
124 return 0;
125 }
126 }
127
128 return 1; /* it's neither */
129 }
130
131 int __init db1200_board_setup(void)
132 {
133 unsigned short whoami;
134
135 if (db1200_detect_board())
136 return -ENODEV;
137
138 whoami = bcsr_read(BCSR_WHOAMI);
139 switch (BCSR_WHOAMI_BOARD(whoami)) {
140 case BCSR_WHOAMI_PB1200_DDR1:
141 case BCSR_WHOAMI_PB1200_DDR2:
142 case BCSR_WHOAMI_DB1200:
143 break;
144 default:
145 return -ENODEV;
146 }
147
148 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
149 " Board-ID %d Daughtercard ID %d\n", get_system_type(),
150 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
151
152 return 0;
153 }
154
155 /******************************************************************************/
156
157 static struct mtd_partition db1200_spiflash_parts[] = {
158 {
159 .name = "spi_flash",
160 .offset = 0,
161 .size = MTDPART_SIZ_FULL,
162 },
163 };
164
165 static struct flash_platform_data db1200_spiflash_data = {
166 .name = "s25fl001",
167 .parts = db1200_spiflash_parts,
168 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
169 .type = "m25p10",
170 };
171
172 static struct spi_board_info db1200_spi_devs[] __initdata = {
173 {
174 /* TI TMP121AIDBVR temp sensor */
175 .modalias = "tmp121",
176 .max_speed_hz = 2000000,
177 .bus_num = 0,
178 .chip_select = 0,
179 .mode = 0,
180 },
181 {
182 /* Spansion S25FL001D0FMA SPI flash */
183 .modalias = "m25p80",
184 .max_speed_hz = 50000000,
185 .bus_num = 0,
186 .chip_select = 1,
187 .mode = 0,
188 .platform_data = &db1200_spiflash_data,
189 },
190 };
191
192 static struct i2c_board_info db1200_i2c_devs[] __initdata = {
193 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */
194 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
195 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
196 };
197
198 /**********************************************************************/
199
200 static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
201 unsigned int ctrl)
202 {
203 struct nand_chip *this = mtd_to_nand(mtd);
204 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
205
206 ioaddr &= 0xffffff00;
207
208 if (ctrl & NAND_CLE) {
209 ioaddr += MEM_STNAND_CMD;
210 } else if (ctrl & NAND_ALE) {
211 ioaddr += MEM_STNAND_ADDR;
212 } else {
213 /* assume we want to r/w real data by default */
214 ioaddr += MEM_STNAND_DATA;
215 }
216 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
217 if (cmd != NAND_CMD_NONE) {
218 __raw_writeb(cmd, this->IO_ADDR_W);
219 wmb();
220 }
221 }
222
223 static int au1200_nand_device_ready(struct mtd_info *mtd)
224 {
225 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
226 }
227
228 static struct mtd_partition db1200_nand_parts[] = {
229 {
230 .name = "NAND FS 0",
231 .offset = 0,
232 .size = 8 * 1024 * 1024,
233 },
234 {
235 .name = "NAND FS 1",
236 .offset = MTDPART_OFS_APPEND,
237 .size = MTDPART_SIZ_FULL
238 },
239 };
240
241 struct platform_nand_data db1200_nand_platdata = {
242 .chip = {
243 .nr_chips = 1,
244 .chip_offset = 0,
245 .nr_partitions = ARRAY_SIZE(db1200_nand_parts),
246 .partitions = db1200_nand_parts,
247 .chip_delay = 20,
248 },
249 .ctrl = {
250 .dev_ready = au1200_nand_device_ready,
251 .cmd_ctrl = au1200_nand_cmd_ctrl,
252 },
253 };
254
255 static struct resource db1200_nand_res[] = {
256 [0] = {
257 .start = DB1200_NAND_PHYS_ADDR,
258 .end = DB1200_NAND_PHYS_ADDR + 0xff,
259 .flags = IORESOURCE_MEM,
260 },
261 };
262
263 static struct platform_device db1200_nand_dev = {
264 .name = "gen_nand",
265 .num_resources = ARRAY_SIZE(db1200_nand_res),
266 .resource = db1200_nand_res,
267 .id = -1,
268 .dev = {
269 .platform_data = &db1200_nand_platdata,
270 }
271 };
272
273 /**********************************************************************/
274
275 static struct smc91x_platdata db1200_eth_data = {
276 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
277 .leda = RPC_LED_100_10,
278 .ledb = RPC_LED_TX_RX,
279 };
280
281 static struct resource db1200_eth_res[] = {
282 [0] = {
283 .start = DB1200_ETH_PHYS_ADDR,
284 .end = DB1200_ETH_PHYS_ADDR + 0xf,
285 .flags = IORESOURCE_MEM,
286 },
287 [1] = {
288 .start = DB1200_ETH_INT,
289 .end = DB1200_ETH_INT,
290 .flags = IORESOURCE_IRQ,
291 },
292 };
293
294 static struct platform_device db1200_eth_dev = {
295 .dev = {
296 .platform_data = &db1200_eth_data,
297 },
298 .name = "smc91x",
299 .id = -1,
300 .num_resources = ARRAY_SIZE(db1200_eth_res),
301 .resource = db1200_eth_res,
302 };
303
304 /**********************************************************************/
305
306 static struct pata_platform_info db1200_ide_info = {
307 .ioport_shift = DB1200_IDE_REG_SHIFT,
308 };
309
310 #define IDE_ALT_START (14 << DB1200_IDE_REG_SHIFT)
311 static struct resource db1200_ide_res[] = {
312 [0] = {
313 .start = DB1200_IDE_PHYS_ADDR,
314 .end = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1,
315 .flags = IORESOURCE_MEM,
316 },
317 [1] = {
318 .start = DB1200_IDE_PHYS_ADDR + IDE_ALT_START,
319 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
320 .flags = IORESOURCE_MEM,
321 },
322 [2] = {
323 .start = DB1200_IDE_INT,
324 .end = DB1200_IDE_INT,
325 .flags = IORESOURCE_IRQ,
326 },
327 };
328
329 static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
330
331 static struct platform_device db1200_ide_dev = {
332 .name = "pata_platform",
333 .id = 0,
334 .dev = {
335 .dma_mask = &au1200_ide_dmamask,
336 .coherent_dma_mask = DMA_BIT_MASK(32),
337 .platform_data = &db1200_ide_info,
338 },
339 .num_resources = ARRAY_SIZE(db1200_ide_res),
340 .resource = db1200_ide_res,
341 };
342
343 /**********************************************************************/
344
345 /* SD carddetects: they're supposed to be edge-triggered, but ack
346 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
347 * is disabled and its counterpart enabled. The 200ms timeout is
348 * because the carddetect usually triggers twice, after debounce.
349 */
350 static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
351 {
352 disable_irq_nosync(irq);
353 return IRQ_WAKE_THREAD;
354 }
355
356 static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr)
357 {
358 void (*mmc_cd)(struct mmc_host *, unsigned long);
359
360 /* link against CONFIG_MMC=m */
361 mmc_cd = symbol_get(mmc_detect_change);
362 if (mmc_cd) {
363 mmc_cd(ptr, msecs_to_jiffies(200));
364 symbol_put(mmc_detect_change);
365 }
366
367 msleep(100); /* debounce */
368 if (irq == DB1200_SD0_INSERT_INT)
369 enable_irq(DB1200_SD0_EJECT_INT);
370 else
371 enable_irq(DB1200_SD0_INSERT_INT);
372
373 return IRQ_HANDLED;
374 }
375
376 static int db1200_mmc_cd_setup(void *mmc_host, int en)
377 {
378 int ret;
379
380 if (en) {
381 ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
382 db1200_mmc_cdfn, 0, "sd_insert", mmc_host);
383 if (ret)
384 goto out;
385
386 ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
387 db1200_mmc_cdfn, 0, "sd_eject", mmc_host);
388 if (ret) {
389 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
390 goto out;
391 }
392
393 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
394 enable_irq(DB1200_SD0_EJECT_INT);
395 else
396 enable_irq(DB1200_SD0_INSERT_INT);
397
398 } else {
399 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
400 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
401 }
402 ret = 0;
403 out:
404 return ret;
405 }
406
407 static void db1200_mmc_set_power(void *mmc_host, int state)
408 {
409 if (state) {
410 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
411 msleep(400); /* stabilization time */
412 } else
413 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
414 }
415
416 static int db1200_mmc_card_readonly(void *mmc_host)
417 {
418 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
419 }
420
421 static int db1200_mmc_card_inserted(void *mmc_host)
422 {
423 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
424 }
425
426 static void db1200_mmcled_set(struct led_classdev *led,
427 enum led_brightness brightness)
428 {
429 if (brightness != LED_OFF)
430 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
431 else
432 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
433 }
434
435 static struct led_classdev db1200_mmc_led = {
436 .brightness_set = db1200_mmcled_set,
437 };
438
439 /* -- */
440
441 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
442 {
443 disable_irq_nosync(irq);
444 return IRQ_WAKE_THREAD;
445 }
446
447 static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr)
448 {
449 void (*mmc_cd)(struct mmc_host *, unsigned long);
450
451 /* link against CONFIG_MMC=m */
452 mmc_cd = symbol_get(mmc_detect_change);
453 if (mmc_cd) {
454 mmc_cd(ptr, msecs_to_jiffies(200));
455 symbol_put(mmc_detect_change);
456 }
457
458 msleep(100); /* debounce */
459 if (irq == PB1200_SD1_INSERT_INT)
460 enable_irq(PB1200_SD1_EJECT_INT);
461 else
462 enable_irq(PB1200_SD1_INSERT_INT);
463
464 return IRQ_HANDLED;
465 }
466
467 static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
468 {
469 int ret;
470
471 if (en) {
472 ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd,
473 pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host);
474 if (ret)
475 goto out;
476
477 ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd,
478 pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host);
479 if (ret) {
480 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
481 goto out;
482 }
483
484 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
485 enable_irq(PB1200_SD1_EJECT_INT);
486 else
487 enable_irq(PB1200_SD1_INSERT_INT);
488
489 } else {
490 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
491 free_irq(PB1200_SD1_EJECT_INT, mmc_host);
492 }
493 ret = 0;
494 out:
495 return ret;
496 }
497
498 static void pb1200_mmc1led_set(struct led_classdev *led,
499 enum led_brightness brightness)
500 {
501 if (brightness != LED_OFF)
502 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
503 else
504 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
505 }
506
507 static struct led_classdev pb1200_mmc1_led = {
508 .brightness_set = pb1200_mmc1led_set,
509 };
510
511 static void pb1200_mmc1_set_power(void *mmc_host, int state)
512 {
513 if (state) {
514 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
515 msleep(400); /* stabilization time */
516 } else
517 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
518 }
519
520 static int pb1200_mmc1_card_readonly(void *mmc_host)
521 {
522 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
523 }
524
525 static int pb1200_mmc1_card_inserted(void *mmc_host)
526 {
527 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
528 }
529
530
531 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
532 [0] = {
533 .cd_setup = db1200_mmc_cd_setup,
534 .set_power = db1200_mmc_set_power,
535 .card_inserted = db1200_mmc_card_inserted,
536 .card_readonly = db1200_mmc_card_readonly,
537 .led = &db1200_mmc_led,
538 },
539 [1] = {
540 .cd_setup = pb1200_mmc1_cd_setup,
541 .set_power = pb1200_mmc1_set_power,
542 .card_inserted = pb1200_mmc1_card_inserted,
543 .card_readonly = pb1200_mmc1_card_readonly,
544 .led = &pb1200_mmc1_led,
545 },
546 };
547
548 static struct resource au1200_mmc0_resources[] = {
549 [0] = {
550 .start = AU1100_SD0_PHYS_ADDR,
551 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
552 .flags = IORESOURCE_MEM,
553 },
554 [1] = {
555 .start = AU1200_SD_INT,
556 .end = AU1200_SD_INT,
557 .flags = IORESOURCE_IRQ,
558 },
559 [2] = {
560 .start = AU1200_DSCR_CMD0_SDMS_TX0,
561 .end = AU1200_DSCR_CMD0_SDMS_TX0,
562 .flags = IORESOURCE_DMA,
563 },
564 [3] = {
565 .start = AU1200_DSCR_CMD0_SDMS_RX0,
566 .end = AU1200_DSCR_CMD0_SDMS_RX0,
567 .flags = IORESOURCE_DMA,
568 }
569 };
570
571 static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
572
573 static struct platform_device db1200_mmc0_dev = {
574 .name = "au1xxx-mmc",
575 .id = 0,
576 .dev = {
577 .dma_mask = &au1xxx_mmc_dmamask,
578 .coherent_dma_mask = DMA_BIT_MASK(32),
579 .platform_data = &db1200_mmc_platdata[0],
580 },
581 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
582 .resource = au1200_mmc0_resources,
583 };
584
585 static struct resource au1200_mmc1_res[] = {
586 [0] = {
587 .start = AU1100_SD1_PHYS_ADDR,
588 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
589 .flags = IORESOURCE_MEM,
590 },
591 [1] = {
592 .start = AU1200_SD_INT,
593 .end = AU1200_SD_INT,
594 .flags = IORESOURCE_IRQ,
595 },
596 [2] = {
597 .start = AU1200_DSCR_CMD0_SDMS_TX1,
598 .end = AU1200_DSCR_CMD0_SDMS_TX1,
599 .flags = IORESOURCE_DMA,
600 },
601 [3] = {
602 .start = AU1200_DSCR_CMD0_SDMS_RX1,
603 .end = AU1200_DSCR_CMD0_SDMS_RX1,
604 .flags = IORESOURCE_DMA,
605 }
606 };
607
608 static struct platform_device pb1200_mmc1_dev = {
609 .name = "au1xxx-mmc",
610 .id = 1,
611 .dev = {
612 .dma_mask = &au1xxx_mmc_dmamask,
613 .coherent_dma_mask = DMA_BIT_MASK(32),
614 .platform_data = &db1200_mmc_platdata[1],
615 },
616 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
617 .resource = au1200_mmc1_res,
618 };
619
620 /**********************************************************************/
621
622 static int db1200fb_panel_index(void)
623 {
624 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
625 }
626
627 static int db1200fb_panel_init(void)
628 {
629 /* Apply power */
630 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
631 BCSR_BOARD_LCDBL);
632 return 0;
633 }
634
635 static int db1200fb_panel_shutdown(void)
636 {
637 /* Remove power */
638 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
639 BCSR_BOARD_LCDBL, 0);
640 return 0;
641 }
642
643 static struct au1200fb_platdata db1200fb_pd = {
644 .panel_index = db1200fb_panel_index,
645 .panel_init = db1200fb_panel_init,
646 .panel_shutdown = db1200fb_panel_shutdown,
647 };
648
649 static struct resource au1200_lcd_res[] = {
650 [0] = {
651 .start = AU1200_LCD_PHYS_ADDR,
652 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
653 .flags = IORESOURCE_MEM,
654 },
655 [1] = {
656 .start = AU1200_LCD_INT,
657 .end = AU1200_LCD_INT,
658 .flags = IORESOURCE_IRQ,
659 }
660 };
661
662 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
663
664 static struct platform_device au1200_lcd_dev = {
665 .name = "au1200-lcd",
666 .id = 0,
667 .dev = {
668 .dma_mask = &au1200_lcd_dmamask,
669 .coherent_dma_mask = DMA_BIT_MASK(32),
670 .platform_data = &db1200fb_pd,
671 },
672 .num_resources = ARRAY_SIZE(au1200_lcd_res),
673 .resource = au1200_lcd_res,
674 };
675
676 /**********************************************************************/
677
678 static struct resource au1200_psc0_res[] = {
679 [0] = {
680 .start = AU1550_PSC0_PHYS_ADDR,
681 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
682 .flags = IORESOURCE_MEM,
683 },
684 [1] = {
685 .start = AU1200_PSC0_INT,
686 .end = AU1200_PSC0_INT,
687 .flags = IORESOURCE_IRQ,
688 },
689 [2] = {
690 .start = AU1200_DSCR_CMD0_PSC0_TX,
691 .end = AU1200_DSCR_CMD0_PSC0_TX,
692 .flags = IORESOURCE_DMA,
693 },
694 [3] = {
695 .start = AU1200_DSCR_CMD0_PSC0_RX,
696 .end = AU1200_DSCR_CMD0_PSC0_RX,
697 .flags = IORESOURCE_DMA,
698 },
699 };
700
701 static struct platform_device db1200_i2c_dev = {
702 .name = "au1xpsc_smbus",
703 .id = 0, /* bus number */
704 .num_resources = ARRAY_SIZE(au1200_psc0_res),
705 .resource = au1200_psc0_res,
706 };
707
708 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
709 {
710 if (cs)
711 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
712 else
713 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
714 }
715
716 static struct au1550_spi_info db1200_spi_platdata = {
717 .mainclk_hz = 50000000, /* PSC0 clock */
718 .num_chipselect = 2,
719 .activate_cs = db1200_spi_cs_en,
720 };
721
722 static u64 spi_dmamask = DMA_BIT_MASK(32);
723
724 static struct platform_device db1200_spi_dev = {
725 .dev = {
726 .dma_mask = &spi_dmamask,
727 .coherent_dma_mask = DMA_BIT_MASK(32),
728 .platform_data = &db1200_spi_platdata,
729 },
730 .name = "au1550-spi",
731 .id = 0, /* bus number */
732 .num_resources = ARRAY_SIZE(au1200_psc0_res),
733 .resource = au1200_psc0_res,
734 };
735
736 static struct resource au1200_psc1_res[] = {
737 [0] = {
738 .start = AU1550_PSC1_PHYS_ADDR,
739 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
740 .flags = IORESOURCE_MEM,
741 },
742 [1] = {
743 .start = AU1200_PSC1_INT,
744 .end = AU1200_PSC1_INT,
745 .flags = IORESOURCE_IRQ,
746 },
747 [2] = {
748 .start = AU1200_DSCR_CMD0_PSC1_TX,
749 .end = AU1200_DSCR_CMD0_PSC1_TX,
750 .flags = IORESOURCE_DMA,
751 },
752 [3] = {
753 .start = AU1200_DSCR_CMD0_PSC1_RX,
754 .end = AU1200_DSCR_CMD0_PSC1_RX,
755 .flags = IORESOURCE_DMA,
756 },
757 };
758
759 /* AC97 or I2S device */
760 static struct platform_device db1200_audio_dev = {
761 /* name assigned later based on switch setting */
762 .id = 1, /* PSC ID */
763 .num_resources = ARRAY_SIZE(au1200_psc1_res),
764 .resource = au1200_psc1_res,
765 };
766
767 /* DB1200 ASoC card device */
768 static struct platform_device db1200_sound_dev = {
769 /* name assigned later based on switch setting */
770 .id = 1, /* PSC ID */
771 };
772
773 static struct platform_device db1200_stac_dev = {
774 .name = "ac97-codec",
775 .id = 1, /* on PSC1 */
776 };
777
778 static struct platform_device db1200_audiodma_dev = {
779 .name = "au1xpsc-pcm",
780 .id = 1, /* PSC ID */
781 };
782
783 static struct platform_device *db1200_devs[] __initdata = {
784 NULL, /* PSC0, selected by S6.8 */
785 &db1200_ide_dev,
786 &db1200_mmc0_dev,
787 &au1200_lcd_dev,
788 &db1200_eth_dev,
789 &db1200_nand_dev,
790 &db1200_audiodma_dev,
791 &db1200_audio_dev,
792 &db1200_stac_dev,
793 &db1200_sound_dev,
794 };
795
796 static struct platform_device *pb1200_devs[] __initdata = {
797 &pb1200_mmc1_dev,
798 };
799
800 /* Some peripheral base addresses differ on the PB1200 */
801 static int __init pb1200_res_fixup(void)
802 {
803 /* CPLD Revs earlier than 4 cause problems */
804 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
805 printk(KERN_ERR "WARNING!!!\n");
806 printk(KERN_ERR "WARNING!!!\n");
807 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
808 printk(KERN_ERR "the board updated to latest revisions.\n");
809 printk(KERN_ERR "This software will not work reliably\n");
810 printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
811 printk(KERN_ERR "WARNING!!!\n");
812 printk(KERN_ERR "WARNING!!!\n");
813 return 1;
814 }
815
816 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
817 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff;
818 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
819 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
820 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
821 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff;
822 return 0;
823 }
824
825 int __init db1200_dev_setup(void)
826 {
827 unsigned long pfc;
828 unsigned short sw;
829 int swapped, bid;
830 struct clk *c;
831
832 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
833 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
834 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
835 if (pb1200_res_fixup())
836 return -ENODEV;
837 }
838
839 /* GPIO7 is low-level triggered CPLD cascade */
840 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
841 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
842
843 /* SMBus/SPI on PSC0, Audio on PSC1 */
844 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
845 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
846 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
847 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
848 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
849
850 /* get 50MHz for I2C driver on PSC0 */
851 c = clk_get(NULL, "psc0_intclk");
852 if (!IS_ERR(c)) {
853 pfc = clk_round_rate(c, 50000000);
854 if ((pfc < 1) || (abs(50000000 - pfc) > 2500000))
855 pr_warn("DB1200: cant get I2C close to 50MHz\n");
856 else
857 clk_set_rate(c, pfc);
858 clk_prepare_enable(c);
859 clk_put(c);
860 }
861
862 /* insert/eject pairs: one of both is always screaming. To avoid
863 * issues they must not be automatically enabled when initially
864 * requested.
865 */
866 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
867 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
868 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
869 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
870 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
871 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
872
873 i2c_register_board_info(0, db1200_i2c_devs,
874 ARRAY_SIZE(db1200_i2c_devs));
875 spi_register_board_info(db1200_spi_devs,
876 ARRAY_SIZE(db1200_i2c_devs));
877
878 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
879 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
880 * or S12 on the PB1200.
881 */
882
883 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
884 * this pin is claimed by PSC0 (unused though, but pinmux doesn't
885 * allow to free it without crippling the SPI interface).
886 * As a result, in SPI mode, OTG simply won't work (PSC0 uses
887 * it as an input pin which is pulled high on the boards).
888 */
889 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
890
891 /* switch off OTG VBUS supply */
892 gpio_request(215, "otg-vbus");
893 gpio_direction_output(215, 1);
894
895 printk(KERN_INFO "%s device configuration:\n", get_system_type());
896
897 sw = bcsr_read(BCSR_SWITCHES);
898 if (sw & BCSR_SWITCHES_DIP_8) {
899 db1200_devs[0] = &db1200_i2c_dev;
900 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
901
902 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */
903
904 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
905 printk(KERN_INFO " OTG port VBUS supply available!\n");
906 } else {
907 db1200_devs[0] = &db1200_spi_dev;
908 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
909
910 pfc |= (1 << 17); /* PSC0 owns GPIO215 */
911
912 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
913 printk(KERN_INFO " OTG port VBUS supply disabled\n");
914 }
915 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
916
917 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
918 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
919 */
920 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
921 if (sw == BCSR_SWITCHES_DIP_8) {
922 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
923 db1200_audio_dev.name = "au1xpsc_i2s";
924 db1200_sound_dev.name = "db1200-i2s";
925 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
926 } else {
927 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
928 db1200_audio_dev.name = "au1xpsc_ac97";
929 db1200_sound_dev.name = "db1200-ac97";
930 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
931 }
932
933 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
934 __raw_writel(PSC_SEL_CLK_SERCLK,
935 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
936 wmb();
937
938 db1x_register_pcmcia_socket(
939 AU1000_PCMCIA_ATTR_PHYS_ADDR,
940 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
941 AU1000_PCMCIA_MEM_PHYS_ADDR,
942 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
943 AU1000_PCMCIA_IO_PHYS_ADDR,
944 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
945 DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
946 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
947
948 db1x_register_pcmcia_socket(
949 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
950 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
951 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
952 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
953 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
954 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
955 DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
956 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
957
958 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
959 db1x_register_norflash(64 << 20, 2, swapped);
960
961 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
962
963 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
964 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
965 (bid == BCSR_WHOAMI_PB1200_DDR2))
966 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
967
968 return 0;
969 }
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