arch/mips/cavium-octeon/executive/cvmx-helper-board.c

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2008 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 /*
  29  *
  30  * Helper functions to abstract board specific data about
  31  * network ports from the rest of the cvmx-helper files.
  32  */
  33
  34 #include <asm/octeon/octeon.h>
  35 #include <asm/octeon/cvmx-bootinfo.h>
  36
  37 #include <asm/octeon/cvmx-config.h>
  38
  39 #include <asm/octeon/cvmx-helper.h>
  40 #include <asm/octeon/cvmx-helper-util.h>
  41 #include <asm/octeon/cvmx-helper-board.h>
  42
  43 #include <asm/octeon/cvmx-gmxx-defs.h>
  44 #include <asm/octeon/cvmx-asxx-defs.h>
  45
  46 /**
  47  * Return the MII PHY address associated with the given IPD
  48  * port. A result of -1 means there isn't a MII capable PHY
  49  * connected to this port. On chips supporting multiple MII
  50  * busses the bus number is encoded in bits <15:8>.
  51  *
  52  * This function must be modified for every new Octeon board.
  53  * Internally it uses switch statements based on the cvmx_sysinfo
  54  * data to determine board types and revisions. It replies on the
  55  * fact that every Octeon board receives a unique board type
  56  * enumeration from the bootloader.
  57  *
  58  * @ipd_port: Octeon IPD port to get the MII address for.
  59  *
  60  * Returns MII PHY address and bus number or -1.
  61  */
  62 int cvmx_helper_board_get_mii_address(int ipd_port)
  63 {
  64         switch (cvmx_sysinfo_get()->board_type) {
  65         case CVMX_BOARD_TYPE_SIM:
  66                 /* Simulator doesn't have MII */
  67                 return -1;
  68         case CVMX_BOARD_TYPE_EBT3000:
  69         case CVMX_BOARD_TYPE_EBT5800:
  70         case CVMX_BOARD_TYPE_THUNDER:
  71         case CVMX_BOARD_TYPE_NICPRO2:
  72                 /* Interface 0 is SPI4, interface 1 is RGMII */
  73                 if ((ipd_port >= 16) && (ipd_port < 20))
  74                         return ipd_port - 16;
  75                 else
  76                         return -1;
  77         case CVMX_BOARD_TYPE_KODAMA:
  78         case CVMX_BOARD_TYPE_EBH3100:
  79         case CVMX_BOARD_TYPE_HIKARI:
  80         case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
  81         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
  82         case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
  83                 /*
  84                  * Port 0 is WAN connected to a PHY, Port 1 is GMII
  85                  * connected to a switch
  86                  */
  87                 if (ipd_port == 0)
  88                         return 4;
  89                 else if (ipd_port == 1)
  90                         return 9;
  91                 else
  92                         return -1;
  93         case CVMX_BOARD_TYPE_NAC38:
  94                 /* Board has 8 RGMII ports PHYs are 0-7 */
  95                 if ((ipd_port >= 0) && (ipd_port < 4))
  96                         return ipd_port;
  97                 else if ((ipd_port >= 16) && (ipd_port < 20))
  98                         return ipd_port - 16 + 4;
  99                 else
 100                         return -1;
 101         case CVMX_BOARD_TYPE_EBH3000:
 102                 /* Board has dual SPI4 and no PHYs */
 103                 return -1;
 104         case CVMX_BOARD_TYPE_EBH5200:
 105         case CVMX_BOARD_TYPE_EBH5201:
 106         case CVMX_BOARD_TYPE_EBT5200:
 107                 /* Board has 2 management ports */
 108                 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
 109                     (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
 110                         return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
 111                 /*
 112                  * Board has 4 SGMII ports. The PHYs start right after the MII
 113                  * ports MII0 = 0, MII1 = 1, SGMII = 2-5.
 114                  */
 115                 if ((ipd_port >= 0) && (ipd_port < 4))
 116                         return ipd_port + 2;
 117                 else
 118                         return -1;
 119         case CVMX_BOARD_TYPE_EBH5600:
 120         case CVMX_BOARD_TYPE_EBH5601:
 121         case CVMX_BOARD_TYPE_EBH5610:
 122                 /* Board has 1 management port */
 123                 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
 124                         return 0;
 125                 /*
 126                  * Board has 8 SGMII ports. 4 connect out, two connect
 127                  * to a switch, and 2 loop to each other
 128                  */
 129                 if ((ipd_port >= 0) && (ipd_port < 4))
 130                         return ipd_port + 1;
 131                 else
 132                         return -1;
 133         case CVMX_BOARD_TYPE_CUST_NB5:
 134                 if (ipd_port == 2)
 135                         return 4;
 136                 else
 137                         return -1;
 138         case CVMX_BOARD_TYPE_NIC_XLE_4G:
 139                 /* Board has 4 SGMII ports. connected QLM3(interface 1) */
 140                 if ((ipd_port >= 16) && (ipd_port < 20))
 141                         return ipd_port - 16 + 1;
 142                 else
 143                         return -1;
 144         case CVMX_BOARD_TYPE_NIC_XLE_10G:
 145         case CVMX_BOARD_TYPE_NIC10E:
 146                 return -1;
 147         case CVMX_BOARD_TYPE_NIC4E:
 148                 if (ipd_port >= 0 && ipd_port <= 3)
 149                         return (ipd_port + 0x1f) & 0x1f;
 150                 else
 151                         return -1;
 152         case CVMX_BOARD_TYPE_NIC2E:
 153                 if (ipd_port >= 0 && ipd_port <= 1)
 154                         return ipd_port + 1;
 155                 else
 156                         return -1;
 157         case CVMX_BOARD_TYPE_BBGW_REF:
 158                 /*
 159                  * No PHYs are connected to Octeon, everything is
 160                  * through switch.
 161                  */
 162                 return -1;
 163
 164         case CVMX_BOARD_TYPE_CUST_WSX16:
 165                 if (ipd_port >= 0 && ipd_port <= 3)
 166                         return ipd_port;
 167                 else if (ipd_port >= 16 && ipd_port <= 19)
 168                         return ipd_port - 16 + 4;
 169                 else
 170                         return -1;
 171         case CVMX_BOARD_TYPE_UBNT_E100:
 172                 if (ipd_port >= 0 && ipd_port <= 2)
 173                         return 7 - ipd_port;
 174                 else
 175                         return -1;
 176         case CVMX_BOARD_TYPE_KONTRON_S1901:
 177                 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
 178                         return 1;
 179                 else
 180                         return -1;
 181
 182         }
 183
 184         /* Some unknown board. Somebody forgot to update this function... */
 185         cvmx_dprintf
 186             ("cvmx_helper_board_get_mii_address: Unknown board type %d\n",
 187              cvmx_sysinfo_get()->board_type);
 188         return -1;
 189 }
 190
 191 /**
 192  * This function is the board specific method of determining an
 193  * ethernet ports link speed. Most Octeon boards have Marvell PHYs
 194  * and are handled by the fall through case. This function must be
 195  * updated for boards that don't have the normal Marvell PHYs.
 196  *
 197  * This function must be modified for every new Octeon board.
 198  * Internally it uses switch statements based on the cvmx_sysinfo
 199  * data to determine board types and revisions. It relies on the
 200  * fact that every Octeon board receives a unique board type
 201  * enumeration from the bootloader.
 202  *
 203  * @ipd_port: IPD input port associated with the port we want to get link
 204  *                 status for.
 205  *
 206  * Returns The ports link status. If the link isn't fully resolved, this must
 207  *         return zero.
 208  */
 209 cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
 210 {
 211         cvmx_helper_link_info_t result;
 212
 213         /* Unless we fix it later, all links are defaulted to down */
 214         result.u64 = 0;
 215
 216         /*
 217          * This switch statement should handle all ports that either don't use
 218          * Marvell PHYS, or don't support in-band status.
 219          */
 220         switch (cvmx_sysinfo_get()->board_type) {
 221         case CVMX_BOARD_TYPE_SIM:
 222                 /* The simulator gives you a simulated 1Gbps full duplex link */
 223                 result.s.link_up = 1;
 224                 result.s.full_duplex = 1;
 225                 result.s.speed = 1000;
 226                 return result;
 227         case CVMX_BOARD_TYPE_EBH3100:
 228         case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
 229         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
 230         case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
 231                 /* Port 1 on these boards is always Gigabit */
 232                 if (ipd_port == 1) {
 233                         result.s.link_up = 1;
 234                         result.s.full_duplex = 1;
 235                         result.s.speed = 1000;
 236                         return result;
 237                 }
 238                 /* Fall through to the generic code below */
 239                 break;
 240         case CVMX_BOARD_TYPE_CUST_NB5:
 241                 /* Port 1 on these boards is always Gigabit */
 242                 if (ipd_port == 1) {
 243                         result.s.link_up = 1;
 244                         result.s.full_duplex = 1;
 245                         result.s.speed = 1000;
 246                         return result;
 247                 }
 248                 break;
 249         case CVMX_BOARD_TYPE_BBGW_REF:
 250                 /* Port 1 on these boards is always Gigabit */
 251                 if (ipd_port == 2) {
 252                         /* Port 2 is not hooked up */
 253                         result.u64 = 0;
 254                         return result;
 255                 } else {
 256                         /* Ports 0 and 1 connect to the switch */
 257                         result.s.link_up = 1;
 258                         result.s.full_duplex = 1;
 259                         result.s.speed = 1000;
 260                         return result;
 261                 }
 262                 break;
 263         }
 264
 265         if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
 266                    || OCTEON_IS_MODEL(OCTEON_CN58XX)
 267                    || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
 268                 /*
 269                  * We don't have a PHY address, so attempt to use
 270                  * in-band status. It is really important that boards
 271                  * not supporting in-band status never get
 272                  * here. Reading broken in-band status tends to do bad
 273                  * things
 274                  */
 275                 union cvmx_gmxx_rxx_rx_inbnd inband_status;
 276                 int interface = cvmx_helper_get_interface_num(ipd_port);
 277                 int index = cvmx_helper_get_interface_index_num(ipd_port);
 278                 inband_status.u64 =
 279                     cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
 280
 281                 result.s.link_up = inband_status.s.status;
 282                 result.s.full_duplex = inband_status.s.duplex;
 283                 switch (inband_status.s.speed) {
 284                 case 0: /* 10 Mbps */
 285                         result.s.speed = 10;
 286                         break;
 287                 case 1: /* 100 Mbps */
 288                         result.s.speed = 100;
 289                         break;
 290                 case 2: /* 1 Gbps */
 291                         result.s.speed = 1000;
 292                         break;
 293                 case 3: /* Illegal */
 294                         result.u64 = 0;
 295                         break;
 296                 }
 297         } else {
 298                 /*
 299                  * We don't have a PHY address and we don't have
 300                  * in-band status. There is no way to determine the
 301                  * link speed. Return down assuming this port isn't
 302                  * wired
 303                  */
 304                 result.u64 = 0;
 305         }
 306
 307         /* If link is down, return all fields as zero. */
 308         if (!result.s.link_up)
 309                 result.u64 = 0;
 310
 311         return result;
 312 }
 313
 314 /**
 315  * This function is called by cvmx_helper_interface_probe() after it
 316  * determines the number of ports Octeon can support on a specific
 317  * interface. This function is the per board location to override
 318  * this value. It is called with the number of ports Octeon might
 319  * support and should return the number of actual ports on the
 320  * board.
 321  *
 322  * This function must be modifed for every new Octeon board.
 323  * Internally it uses switch statements based on the cvmx_sysinfo
 324  * data to determine board types and revisions. It relys on the
 325  * fact that every Octeon board receives a unique board type
 326  * enumeration from the bootloader.
 327  *
 328  * @interface: Interface to probe
 329  * @supported_ports:
 330  *                  Number of ports Octeon supports.
 331  *
 332  * Returns Number of ports the actual board supports. Many times this will
 333  *         simple be "support_ports".
 334  */
 335 int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
 336 {
 337         switch (cvmx_sysinfo_get()->board_type) {
 338         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
 339                 if (interface == 0)
 340                         return 2;
 341                 break;
 342         case CVMX_BOARD_TYPE_BBGW_REF:
 343                 if (interface == 0)
 344                         return 2;
 345                 break;
 346         case CVMX_BOARD_TYPE_NIC_XLE_4G:
 347                 if (interface == 0)
 348                         return 0;
 349                 break;
 350                 /* The 2nd interface on the EBH5600 is connected to the Marvel switch,
 351                    which we don't support. Disable ports connected to it */
 352         case CVMX_BOARD_TYPE_EBH5600:
 353                 if (interface == 1)
 354                         return 0;
 355                 break;
 356         }
 357         return supported_ports;
 358 }
 359
 360 /**
 361  * Enable packet input/output from the hardware. This function is
 362  * called after by cvmx_helper_packet_hardware_enable() to
 363  * perform board specific initialization. For most boards
 364  * nothing is needed.
 365  *
 366  * @interface: Interface to enable
 367  *
 368  * Returns Zero on success, negative on failure
 369  */
 370 int __cvmx_helper_board_hardware_enable(int interface)
 371 {
 372         if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) {
 373                 if (interface == 0) {
 374                         /* Different config for switch port */
 375                         cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0);
 376                         cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
 377                         /*
 378                          * Boards with gigabit WAN ports need a
 379                          * different setting that is compatible with
 380                          * 100 Mbit settings
 381                          */
 382                         cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface),
 383                                        0xc);
 384                         cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface),
 385                                        0xc);
 386                 }
 387         } else if (cvmx_sysinfo_get()->board_type ==
 388                         CVMX_BOARD_TYPE_UBNT_E100) {
 389                 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0);
 390                 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10);
 391                 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
 392                 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10);
 393                 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0);
 394                 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10);
 395         }
 396         return 0;
 397 }
 398
 399 /**
 400  * Get the clock type used for the USB block based on board type.
 401  * Used by the USB code for auto configuration of clock type.
 402  *
 403  * Return USB clock type enumeration
 404  */
 405 enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void)
 406 {
 407         switch (cvmx_sysinfo_get()->board_type) {
 408         case CVMX_BOARD_TYPE_BBGW_REF:
 409         case CVMX_BOARD_TYPE_LANAI2_A:
 410         case CVMX_BOARD_TYPE_LANAI2_U:
 411         case CVMX_BOARD_TYPE_LANAI2_G:
 412         case CVMX_BOARD_TYPE_NIC10E_66:
 413         case CVMX_BOARD_TYPE_UBNT_E100:
 414                 return USB_CLOCK_TYPE_CRYSTAL_12;
 415         case CVMX_BOARD_TYPE_NIC10E:
 416                 return USB_CLOCK_TYPE_REF_12;
 417         default:
 418                 break;
 419         }
 420         /* Most boards except NIC10e use a 12MHz crystal */
 421         if (OCTEON_IS_OCTEON2())
 422                 return USB_CLOCK_TYPE_CRYSTAL_12;
 423         return USB_CLOCK_TYPE_REF_48;
 424 }