2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
9 #ifndef __ASM_MACH_IP32_DMA_COHERENCE_H
10 #define __ASM_MACH_IP32_DMA_COHERENCE_H
12 #include <asm/ip32/crime.h>
18 * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
19 * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for
21 * 3. All other devices see memory as one big chunk at 0x40000000
22 * 4. Non-PCI devices will pass NULL as struct device*
24 * Thus we translate differently, depending on device.
27 #define RAM_OFFSET_MASK 0x3fffffffUL
29 static inline dma_addr_t
plat_map_dma_mem(struct device
*dev
, void *addr
,
32 dma_addr_t pa
= virt_to_phys(addr
) & RAM_OFFSET_MASK
;
35 pa
+= CRIME_HI_MEM_BASE
;
40 static inline dma_addr_t
plat_map_dma_mem_page(struct device
*dev
,
45 pa
= page_to_phys(page
) & RAM_OFFSET_MASK
;
48 pa
+= CRIME_HI_MEM_BASE
;
53 /* This is almost certainly wrong but it's what dma-ip32.c used to use */
54 static inline unsigned long plat_dma_addr_to_phys(struct device
*dev
,
57 unsigned long addr
= dma_addr
& RAM_OFFSET_MASK
;
59 if (dma_addr
>= 256*1024*1024)
60 addr
+= CRIME_HI_MEM_BASE
;
65 static inline void plat_unmap_dma_mem(struct device
*dev
, dma_addr_t dma_addr
,
66 size_t size
, enum dma_data_direction direction
)
70 static inline int plat_dma_supported(struct device
*dev
, u64 mask
)
73 * we fall back to GFP_DMA when the mask isn't all 1s,
74 * so we can't guarantee allocations that must be
75 * within a tighter range than GFP_DMA..
77 if (mask
< DMA_BIT_MASK(24))
83 static inline void plat_post_dma_flush(struct device
*dev
)
87 static inline int plat_device_is_coherent(struct device
*dev
)
89 return 0; /* IP32 is non-coherent */
92 #endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */