arch/mips/include/asm/mach-loongson64/cs5536/cs5536.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * The header file of cs5536 south bridge.
   4  *
   5  * Copyright (C) 2007 Lemote, Inc.
   6  * Author : jlliu <liujl@lemote.com>
   7  */
   8
   9 #ifndef _CS5536_H
  10 #define _CS5536_H
  11
  12 #include <linux/types.h>
  13
  14 extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
  15 extern void _wrmsr(u32 msr, u32 hi, u32 lo);
  16
  17 /*
  18  * MSR module base
  19  */
  20 #define CS5536_SB_MSR_BASE      (0x00000000)
  21 #define CS5536_GLIU_MSR_BASE    (0x10000000)
  22 #define CS5536_ILLEGAL_MSR_BASE (0x20000000)
  23 #define CS5536_USB_MSR_BASE     (0x40000000)
  24 #define CS5536_IDE_MSR_BASE     (0x60000000)
  25 #define CS5536_DIVIL_MSR_BASE   (0x80000000)
  26 #define CS5536_ACC_MSR_BASE     (0xa0000000)
  27 #define CS5536_UNUSED_MSR_BASE  (0xc0000000)
  28 #define CS5536_GLCP_MSR_BASE    (0xe0000000)
  29
  30 #define SB_MSR_REG(offset)      (CS5536_SB_MSR_BASE     | (offset))
  31 #define GLIU_MSR_REG(offset)    (CS5536_GLIU_MSR_BASE   | (offset))
  32 #define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
  33 #define USB_MSR_REG(offset)     (CS5536_USB_MSR_BASE    | (offset))
  34 #define IDE_MSR_REG(offset)     (CS5536_IDE_MSR_BASE    | (offset))
  35 #define DIVIL_MSR_REG(offset)   (CS5536_DIVIL_MSR_BASE  | (offset))
  36 #define ACC_MSR_REG(offset)     (CS5536_ACC_MSR_BASE    | (offset))
  37 #define UNUSED_MSR_REG(offset)  (CS5536_UNUSED_MSR_BASE | (offset))
  38 #define GLCP_MSR_REG(offset)    (CS5536_GLCP_MSR_BASE   | (offset))
  39
  40 /*
  41  * BAR SPACE OF VIRTUAL PCI :
  42  * range for pci probe use, length is the actual size.
  43  */
  44 /* IO space for all DIVIL modules */
  45 #define CS5536_IRQ_RANGE        0xffffffe0 /* USERD FOR PCI PROBE */
  46 #define CS5536_IRQ_LENGTH       0x20    /* THE REGS ACTUAL LENGTH */
  47 #define CS5536_SMB_RANGE        0xfffffff8
  48 #define CS5536_SMB_LENGTH       0x08
  49 #define CS5536_GPIO_RANGE       0xffffff00
  50 #define CS5536_GPIO_LENGTH      0x100
  51 #define CS5536_MFGPT_RANGE      0xffffffc0
  52 #define CS5536_MFGPT_LENGTH     0x40
  53 #define CS5536_ACPI_RANGE       0xffffffe0
  54 #define CS5536_ACPI_LENGTH      0x20
  55 #define CS5536_PMS_RANGE        0xffffff80
  56 #define CS5536_PMS_LENGTH       0x80
  57 /* IO space for IDE */
  58 #define CS5536_IDE_RANGE        0xfffffff0
  59 #define CS5536_IDE_LENGTH       0x10
  60 /* IO space for ACC */
  61 #define CS5536_ACC_RANGE        0xffffff80
  62 #define CS5536_ACC_LENGTH       0x80
  63 /* MEM space for ALL USB modules */
  64 #define CS5536_OHCI_RANGE       0xfffff000
  65 #define CS5536_OHCI_LENGTH      0x1000
  66 #define CS5536_EHCI_RANGE       0xfffff000
  67 #define CS5536_EHCI_LENGTH      0x1000
  68
  69 /*
  70  * PCI MSR ACCESS
  71  */
  72 #define PCI_MSR_CTRL            0xF0
  73 #define PCI_MSR_ADDR            0xF4
  74 #define PCI_MSR_DATA_LO         0xF8
  75 #define PCI_MSR_DATA_HI         0xFC
  76
  77 /**************** MSR *****************************/
  78
  79 /*
  80  * GLIU STANDARD MSR
  81  */
  82 #define GLIU_CAP                0x00
  83 #define GLIU_CONFIG             0x01
  84 #define GLIU_SMI                0x02
  85 #define GLIU_ERROR              0x03
  86 #define GLIU_PM                 0x04
  87 #define GLIU_DIAG               0x05
  88
  89 /*
  90  * GLIU SPEC. MSR
  91  */
  92 #define GLIU_P2D_BM0            0x20
  93 #define GLIU_P2D_BM1            0x21
  94 #define GLIU_P2D_BM2            0x22
  95 #define GLIU_P2D_BMK0           0x23
  96 #define GLIU_P2D_BMK1           0x24
  97 #define GLIU_P2D_BM3            0x25
  98 #define GLIU_P2D_BM4            0x26
  99 #define GLIU_COH                0x80
 100 #define GLIU_PAE                0x81
 101 #define GLIU_ARB                0x82
 102 #define GLIU_ASMI               0x83
 103 #define GLIU_AERR               0x84
 104 #define GLIU_DEBUG              0x85
 105 #define GLIU_PHY_CAP            0x86
 106 #define GLIU_NOUT_RESP          0x87
 107 #define GLIU_NOUT_WDATA         0x88
 108 #define GLIU_WHOAMI             0x8B
 109 #define GLIU_SLV_DIS            0x8C
 110 #define GLIU_IOD_BM0            0xE0
 111 #define GLIU_IOD_BM1            0xE1
 112 #define GLIU_IOD_BM2            0xE2
 113 #define GLIU_IOD_BM3            0xE3
 114 #define GLIU_IOD_BM4            0xE4
 115 #define GLIU_IOD_BM5            0xE5
 116 #define GLIU_IOD_BM6            0xE6
 117 #define GLIU_IOD_BM7            0xE7
 118 #define GLIU_IOD_BM8            0xE8
 119 #define GLIU_IOD_BM9            0xE9
 120 #define GLIU_IOD_SC0            0xEA
 121 #define GLIU_IOD_SC1            0xEB
 122 #define GLIU_IOD_SC2            0xEC
 123 #define GLIU_IOD_SC3            0xED
 124 #define GLIU_IOD_SC4            0xEE
 125 #define GLIU_IOD_SC5            0xEF
 126 #define GLIU_IOD_SC6            0xF0
 127 #define GLIU_IOD_SC7            0xF1
 128
 129 /*
 130  * SB STANDARD
 131  */
 132 #define SB_CAP          0x00
 133 #define SB_CONFIG       0x01
 134 #define SB_SMI          0x02
 135 #define SB_ERROR        0x03
 136 #define SB_MAR_ERR_EN           0x00000001
 137 #define SB_TAR_ERR_EN           0x00000002
 138 #define SB_RSVD_BIT1            0x00000004
 139 #define SB_EXCEP_ERR_EN         0x00000008
 140 #define SB_SYSE_ERR_EN          0x00000010
 141 #define SB_PARE_ERR_EN          0x00000020
 142 #define SB_TAS_ERR_EN           0x00000040
 143 #define SB_MAR_ERR_FLAG         0x00010000
 144 #define SB_TAR_ERR_FLAG         0x00020000
 145 #define SB_RSVD_BIT2            0x00040000
 146 #define SB_EXCEP_ERR_FLAG       0x00080000
 147 #define SB_SYSE_ERR_FLAG        0x00100000
 148 #define SB_PARE_ERR_FLAG        0x00200000
 149 #define SB_TAS_ERR_FLAG         0x00400000
 150 #define SB_PM           0x04
 151 #define SB_DIAG         0x05
 152
 153 /*
 154  * SB SPEC.
 155  */
 156 #define SB_CTRL         0x10
 157 #define SB_R0           0x20
 158 #define SB_R1           0x21
 159 #define SB_R2           0x22
 160 #define SB_R3           0x23
 161 #define SB_R4           0x24
 162 #define SB_R5           0x25
 163 #define SB_R6           0x26
 164 #define SB_R7           0x27
 165 #define SB_R8           0x28
 166 #define SB_R9           0x29
 167 #define SB_R10          0x2A
 168 #define SB_R11          0x2B
 169 #define SB_R12          0x2C
 170 #define SB_R13          0x2D
 171 #define SB_R14          0x2E
 172 #define SB_R15          0x2F
 173
 174 /*
 175  * GLCP STANDARD
 176  */
 177 #define GLCP_CAP                0x00
 178 #define GLCP_CONFIG             0x01
 179 #define GLCP_SMI                0x02
 180 #define GLCP_ERROR              0x03
 181 #define GLCP_PM                 0x04
 182 #define GLCP_DIAG               0x05
 183
 184 /*
 185  * GLCP SPEC.
 186  */
 187 #define GLCP_CLK_DIS_DELAY      0x08
 188 #define GLCP_PM_CLK_DISABLE     0x09
 189 #define GLCP_GLB_PM             0x0B
 190 #define GLCP_DBG_OUT            0x0C
 191 #define GLCP_RSVD1              0x0D
 192 #define GLCP_SOFT_COM           0x0E
 193 #define SOFT_BAR_SMB_FLAG       0x00000001
 194 #define SOFT_BAR_GPIO_FLAG      0x00000002
 195 #define SOFT_BAR_MFGPT_FLAG     0x00000004
 196 #define SOFT_BAR_IRQ_FLAG       0x00000008
 197 #define SOFT_BAR_PMS_FLAG       0x00000010
 198 #define SOFT_BAR_ACPI_FLAG      0x00000020
 199 #define SOFT_BAR_IDE_FLAG       0x00000400
 200 #define SOFT_BAR_ACC_FLAG       0x00000800
 201 #define SOFT_BAR_OHCI_FLAG      0x00001000
 202 #define SOFT_BAR_EHCI_FLAG      0x00002000
 203 #define GLCP_RSVD2              0x0F
 204 #define GLCP_CLK_OFF            0x10
 205 #define GLCP_CLK_ACTIVE         0x11
 206 #define GLCP_CLK_DISABLE        0x12
 207 #define GLCP_CLK4ACK            0x13
 208 #define GLCP_SYS_RST            0x14
 209 #define GLCP_RSVD3              0x15
 210 #define GLCP_DBG_CLK_CTRL       0x16
 211 #define GLCP_CHIP_REV_ID        0x17
 212
 213 /* PIC */
 214 #define PIC_YSEL_LOW            0x20
 215 #define PIC_YSEL_LOW_USB_SHIFT          8
 216 #define PIC_YSEL_LOW_ACC_SHIFT          16
 217 #define PIC_YSEL_LOW_FLASH_SHIFT        24
 218 #define PIC_YSEL_HIGH           0x21
 219 #define PIC_ZSEL_LOW            0x22
 220 #define PIC_ZSEL_HIGH           0x23
 221 #define PIC_IRQM_PRIM           0x24
 222 #define PIC_IRQM_LPC            0x25
 223 #define PIC_XIRR_STS_LOW        0x26
 224 #define PIC_XIRR_STS_HIGH       0x27
 225 #define PCI_SHDW                0x34
 226
 227 /*
 228  * DIVIL STANDARD
 229  */
 230 #define DIVIL_CAP               0x00
 231 #define DIVIL_CONFIG            0x01
 232 #define DIVIL_SMI               0x02
 233 #define DIVIL_ERROR             0x03
 234 #define DIVIL_PM                0x04
 235 #define DIVIL_DIAG              0x05
 236
 237 /*
 238  * DIVIL SPEC.
 239  */
 240 #define DIVIL_LBAR_IRQ          0x08
 241 #define DIVIL_LBAR_KEL          0x09
 242 #define DIVIL_LBAR_SMB          0x0B
 243 #define DIVIL_LBAR_GPIO         0x0C
 244 #define DIVIL_LBAR_MFGPT        0x0D
 245 #define DIVIL_LBAR_ACPI         0x0E
 246 #define DIVIL_LBAR_PMS          0x0F
 247 #define DIVIL_LEG_IO            0x14
 248 #define DIVIL_BALL_OPTS         0x15
 249 #define DIVIL_SOFT_IRQ          0x16
 250 #define DIVIL_SOFT_RESET        0x17
 251
 252 /* MFGPT */
 253 #define MFGPT_IRQ       0x28
 254
 255 /*
 256  * IDE STANDARD
 257  */
 258 #define IDE_CAP         0x00
 259 #define IDE_CONFIG      0x01
 260 #define IDE_SMI         0x02
 261 #define IDE_ERROR       0x03
 262 #define IDE_PM          0x04
 263 #define IDE_DIAG        0x05
 264
 265 /*
 266  * IDE SPEC.
 267  */
 268 #define IDE_IO_BAR      0x08
 269 #define IDE_CFG         0x10
 270 #define IDE_DTC         0x12
 271 #define IDE_CAST        0x13
 272 #define IDE_ETC         0x14
 273 #define IDE_INTERNAL_PM 0x15
 274
 275 /*
 276  * ACC STANDARD
 277  */
 278 #define ACC_CAP         0x00
 279 #define ACC_CONFIG      0x01
 280 #define ACC_SMI         0x02
 281 #define ACC_ERROR       0x03
 282 #define ACC_PM          0x04
 283 #define ACC_DIAG        0x05
 284
 285 /*
 286  * USB STANDARD
 287  */
 288 #define USB_CAP         0x00
 289 #define USB_CONFIG      0x01
 290 #define USB_SMI         0x02
 291 #define USB_ERROR       0x03
 292 #define USB_PM          0x04
 293 #define USB_DIAG        0x05
 294
 295 /*
 296  * USB SPEC.
 297  */
 298 #define USB_OHCI        0x08
 299 #define USB_EHCI        0x09
 300
 301 /****************** NATIVE ***************************/
 302 /* GPIO : I/O SPACE; REG : 32BITS */
 303 #define GPIOL_OUT_VAL           0x00
 304 #define GPIOL_OUT_EN            0x04
 305
 306 #endif                          /* _CS5536_H */