arch/mips/include/asm/mips-boards/piix4.h

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
   4  * Copyright (C) 2013 Imagination Technologies Ltd.
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  *
  19  * Register definitions for Intel PIIX4 South Bridge Device.
  20  */
  21 #ifndef __ASM_MIPS_BOARDS_PIIX4_H
  22 #define __ASM_MIPS_BOARDS_PIIX4_H
  23
  24 /* PIRQX Route Control */
  25 #define PIIX4_FUNC0_PIRQRC                      0x60
  26 #define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE        (1 << 7)
  27 #define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK           0xf
  28 #define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX            16
  29 /* SERIRQ Control */
  30 #define PIIX4_FUNC0_SERIRQC                     0x64
  31 #define   PIIX4_FUNC0_SERIRQC_EN                        (1 << 7)
  32 #define   PIIX4_FUNC0_SERIRQC_CONT                      (1 << 6)
  33 /* Top Of Memory */
  34 #define PIIX4_FUNC0_TOM                         0x69
  35 #define   PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK            0xf0
  36 /* Deterministic Latency Control */
  37 #define PIIX4_FUNC0_DLC                         0x82
  38 #define   PIIX4_FUNC0_DLC_USBPR_EN                      (1 << 2)
  39 #define   PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN            (1 << 1)
  40 #define   PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN        (1 << 0)
  41 /* General Configuration */
  42 #define PIIX4_FUNC0_GENCFG                      0xb0
  43 #define   PIIX4_FUNC0_GENCFG_SERIRQ                     (1 << 16)
  44
  45 /* IDE Timing */
  46 #define PIIX4_FUNC1_IDETIM_PRIMARY_LO           0x40
  47 #define PIIX4_FUNC1_IDETIM_PRIMARY_HI           0x41
  48 #define   PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN   (1 << 7)
  49 #define PIIX4_FUNC1_IDETIM_SECONDARY_LO         0x42
  50 #define PIIX4_FUNC1_IDETIM_SECONDARY_HI         0x43
  51 #define   PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
  52
  53 /* Power Management Configuration Space */
  54 #define PIIX4_FUNC3_PMBA                        0x40
  55 #define PIIX4_FUNC3_PMREGMISC                   0x80
  56 #define   PIIX4_FUNC3_PMREGMISC_EN                      (1 << 0)
  57
  58 /* Power Management IO Space */
  59 #define PIIX4_FUNC3IO_PMSTS                     0x00
  60 #define   PIIX4_FUNC3IO_PMSTS_PWRBTN_STS                (1 << 8)
  61 #define PIIX4_FUNC3IO_PMCNTRL                   0x04
  62 #define   PIIX4_FUNC3IO_PMCNTRL_SUS_EN                  (1 << 13)
  63 #define   PIIX4_FUNC3IO_PMCNTRL_SUS_TYP                 (0x7 << 10)
  64 #define   PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF            (0x0 << 10)
  65 #define   PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_STR             (0x1 << 10)
  66
  67 /* Data for magic special PCI cycle */
  68 #define PIIX4_SUSPEND_MAGIC                     0x00120002
  69
  70 #endif /* __ASM_MIPS_BOARDS_PIIX4_H */