arch/powerpc/boot/dts/c2k.dts

   1 /* Device Tree Source for GEFanuc C2K
   2  *
   3  * Author: Remi Machet <rmachet@slac.stanford.edu>
   4  *
   5  * Originated from prpmc2800.dts
   6  *
   7  * 2008 (c) Stanford University
   8  * 2007 (c) MontaVista, Software, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  */
  14
  15 /dts-v1/;
  16
  17 / {
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20         model = "C2K";
  21         compatible = "GEFanuc,C2K";
  22         coherency-off;
  23
  24         aliases {
  25                 pci0 = &PCI0;
  26                 pci1 = &PCI1;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "PowerPC,7447";
  36                         reg = <0>;
  37                         clock-frequency = <996000000>;  /* 996 MHz */
  38                         bus-frequency = <166666667>;    /* 166.6666 MHz */
  39                         timebase-frequency = <41666667>;        /* 166.6666/4 MHz */
  40                         i-cache-line-size = <32>;
  41                         d-cache-line-size = <32>;
  42                         i-cache-size = <32768>;
  43                         d-cache-size = <32768>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x00000000 0x40000000>;  /* 1GB */
  50         };
  51
  52         system-controller@d8000000 { /* Marvell Discovery */
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 model = "mv64460";
  56                 compatible = "marvell,mv64360";
  57                 clock-frequency = <166666667>;          /* 166.66... MHz */
  58                 reg = <0xd8000000 0x00010000>;
  59                 virtual-reg = <0xd8000000>;
  60                 ranges = <0xd4000000 0xd4000000 0x01000000      /* PCI 0 I/O Space */
  61                           0x80000000 0x80000000 0x08000000      /* PCI 0 MEM Space */
  62                           0xd0000000 0xd0000000 0x01000000      /* PCI 1 I/O Space */
  63                           0xa0000000 0xa0000000 0x08000000      /* PCI 1 MEM Space */
  64                           0xd8100000 0xd8100000 0x00010000      /* FPGA */
  65                           0xd8110000 0xd8110000 0x00010000      /* FPGA USARTs */
  66                           0xf8000000 0xf8000000 0x08000000      /* User FLASH */
  67                           0x00000000 0xd8000000 0x00010000      /* Bridge's regs */
  68                           0xd8140000 0xd8140000 0x00040000>;    /* Integrated SRAM */
  69
  70                 mdio@2000 {
  71                         #address-cells = <1>;
  72                         #size-cells = <0>;
  73                         compatible = "marvell,mv64360-mdio";
  74                         reg = <0x2000 4>;
  75                         PHY0: ethernet-phy@0 {
  76                                 interrupts = <76>;      /* GPP 12 */
  77                                 interrupt-parent = <&PIC>;
  78                                 reg = <0>;
  79                         };
  80                         PHY1: ethernet-phy@1 {
  81                                 interrupts = <76>;      /* GPP 12 */
  82                                 interrupt-parent = <&PIC>;
  83                                 reg = <1>;
  84                         };
  85                         PHY2: ethernet-phy@2 {
  86                                 interrupts = <76>;      /* GPP 12 */
  87                                 interrupt-parent = <&PIC>;
  88                                 reg = <2>;
  89                         };
  90                 };
  91
  92                 ethernet-group@2000 {
  93                         #address-cells = <1>;
  94                         #size-cells = <0>;
  95                         compatible = "marvell,mv64360-eth-group";
  96                         reg = <0x2000 0x2000>;
  97                         ethernet@0 {
  98                                 device_type = "network";
  99                                 compatible = "marvell,mv64360-eth";
 100                                 reg = <0>;
 101                                 interrupts = <32>;
 102                                 interrupt-parent = <&PIC>;
 103                                 phy = <&PHY0>;
 104                                 local-mac-address = [ 00 00 00 00 00 00 ];
 105                         };
 106                         ethernet@1 {
 107                                 device_type = "network";
 108                                 compatible = "marvell,mv64360-eth";
 109                                 reg = <1>;
 110                                 interrupts = <33>;
 111                                 interrupt-parent = <&PIC>;
 112                                 phy = <&PHY1>;
 113                                 local-mac-address = [ 00 00 00 00 00 00 ];
 114                         };
 115                         ethernet@2 {
 116                                 device_type = "network";
 117                                 compatible = "marvell,mv64360-eth";
 118                                 reg = <2>;
 119                                 interrupts = <34>;
 120                                 interrupt-parent = <&PIC>;
 121                                 phy = <&PHY2>;
 122                                 local-mac-address = [ 00 00 00 00 00 00 ];
 123                         };
 124                 };
 125
 126                 SDMA0: sdma@4000 {
 127                         compatible = "marvell,mv64360-sdma";
 128                         reg = <0x4000 0xc18>;
 129                         virtual-reg = <0xd8004000>;
 130                         interrupt-base = <0>;
 131                         interrupts = <36>;
 132                         interrupt-parent = <&PIC>;
 133                 };
 134
 135                 SDMA1: sdma@6000 {
 136                         compatible = "marvell,mv64360-sdma";
 137                         reg = <0x6000 0xc18>;
 138                         virtual-reg = <0xd8006000>;
 139                         interrupt-base = <0>;
 140                         interrupts = <38>;
 141                         interrupt-parent = <&PIC>;
 142                 };
 143
 144                 BRG0: brg@b200 {
 145                         compatible = "marvell,mv64360-brg";
 146                         reg = <0xb200 0x8>;
 147                         clock-src = <8>;
 148                         clock-frequency = <133333333>;
 149                         current-speed = <115200>;
 150                 };
 151
 152                 BRG1: brg@b208 {
 153                         compatible = "marvell,mv64360-brg";
 154                         reg = <0xb208 0x8>;
 155                         clock-src = <8>;
 156                         clock-frequency = <133333333>;
 157                         current-speed = <115200>;
 158                 };
 159
 160                 CUNIT: cunit@f200 {
 161                         reg = <0xf200 0x200>;
 162                 };
 163
 164                 MPSCROUTING: mpscrouting@b400 {
 165                         reg = <0xb400 0xc>;
 166                 };
 167
 168                 MPSCINTR: mpscintr@b800 {
 169                         reg = <0xb800 0x100>;
 170                         virtual-reg = <0xd800b800>;
 171                 };
 172
 173                 MPSC0: mpsc@8000 {
 174                         compatible = "marvell,mv64360-mpsc";
 175                         reg = <0x8000 0x38>;
 176                         virtual-reg = <0xd8008000>;
 177                         sdma = <&SDMA0>;
 178                         brg = <&BRG0>;
 179                         cunit = <&CUNIT>;
 180                         mpscrouting = <&MPSCROUTING>;
 181                         mpscintr = <&MPSCINTR>;
 182                         cell-index = <0>;
 183                         interrupts = <40>;
 184                         interrupt-parent = <&PIC>;
 185                 };
 186
 187                 MPSC1: mpsc@9000 {
 188                         compatible = "marvell,mv64360-mpsc";
 189                         reg = <0x9000 0x38>;
 190                         virtual-reg = <0xd8009000>;
 191                         sdma = <&SDMA1>;
 192                         brg = <&BRG1>;
 193                         cunit = <&CUNIT>;
 194                         mpscrouting = <&MPSCROUTING>;
 195                         mpscintr = <&MPSCINTR>;
 196                         cell-index = <1>;
 197                         interrupts = <42>;
 198                         interrupt-parent = <&PIC>;
 199                 };
 200
 201                 wdt@b410 {                      /* watchdog timer */
 202                         compatible = "marvell,mv64360-wdt";
 203                         reg = <0xb410 0x8>;
 204                 };
 205
 206                 i2c@c000 {
 207                         compatible = "marvell,mv64360-i2c";
 208                         reg = <0xc000 0x20>;
 209                         virtual-reg = <0xd800c000>;
 210                         interrupts = <37>;
 211                         interrupt-parent = <&PIC>;
 212                 };
 213
 214                 PIC: pic {
 215                         #interrupt-cells = <1>;
 216                         #address-cells = <0>;
 217                         compatible = "marvell,mv64360-pic";
 218                         reg = <0x0000 0x88>;
 219                         interrupt-controller;
 220                 };
 221
 222                 mpp@f000 {
 223                         compatible = "marvell,mv64360-mpp";
 224                         reg = <0xf000 0x10>;
 225                 };
 226
 227                 gpp@f100 {
 228                         compatible = "marvell,mv64360-gpp";
 229                         reg = <0xf100 0x20>;
 230                 };
 231
 232                 PCI0: pci@80000000 {
 233                         #address-cells = <3>;
 234                         #size-cells = <2>;
 235                         #interrupt-cells = <1>;
 236                         device_type = "pci";
 237                         compatible = "marvell,mv64360-pci";
 238                         reg = <0x0cf8 0x8>;
 239                         ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
 240                                   0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
 241                         bus-range = <0 255>;
 242                         clock-frequency = <66000000>;
 243                         interrupt-pci-iack = <0x0c34>;
 244                         interrupt-parent = <&PIC>;
 245                         interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
 246                         interrupt-map = <
 247                                 /* Only one interrupt line for PMC0 slot (INTA) */
 248                                 0x0000 0 0 1 &PIC 88
 249                         >;
 250                 };
 251
 252
 253                 PCI1: pci@a0000000 {
 254                         #address-cells = <3>;
 255                         #size-cells = <2>;
 256                         #interrupt-cells = <1>;
 257                         device_type = "pci";
 258                         compatible = "marvell,mv64360-pci";
 259                         reg = <0x0c78 0x8>;
 260                         ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
 261                                   0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
 262                         bus-range = <0 255>;
 263                         clock-frequency = <66000000>;
 264                         interrupt-pci-iack = <0x0cb4>;
 265                         interrupt-parent = <&PIC>;
 266                         interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
 267                         interrupt-map = <
 268                                 /* IDSEL 0x01: PMC1 ? */
 269                                 0x0800 0 0 1 &PIC 88
 270                                 /* IDSEL 0x02: cPCI bridge */
 271                                 0x1000 0 0 1 &PIC 88
 272                                 /* IDSEL 0x03: USB controller */
 273                                 0x1800 0 0 1 &PIC 91
 274                                 /* IDSEL 0x04: SATA controller */
 275                                 0x2000 0 0 1 &PIC 95
 276                         >;
 277                 };
 278
 279                 cpu-error@70 {
 280                         compatible = "marvell,mv64360-cpu-error";
 281                         reg = <0x0070 0x10 0x0128 0x28>;
 282                         interrupts = <3>;
 283                         interrupt-parent = <&PIC>;
 284                 };
 285
 286                 sram-ctrl@380 {
 287                         compatible = "marvell,mv64360-sram-ctrl";
 288                         reg = <0x0380 0x80>;
 289                         interrupts = <13>;
 290                         interrupt-parent = <&PIC>;
 291                 };
 292
 293                 pci-error@1d40 {
 294                         compatible = "marvell,mv64360-pci-error";
 295                         reg = <0x1d40 0x40 0x0c28 0x4>;
 296                         interrupts = <12>;
 297                         interrupt-parent = <&PIC>;
 298                 };
 299
 300                 pci-error@1dc0 {
 301                         compatible = "marvell,mv64360-pci-error";
 302                         reg = <0x1dc0 0x40 0x0ca8 0x4>;
 303                         interrupts = <16>;
 304                         interrupt-parent = <&PIC>;
 305                 };
 306
 307                 mem-ctrl@1400 {
 308                         compatible = "marvell,mv64360-mem-ctrl";
 309                         reg = <0x1400 0x60>;
 310                         interrupts = <17>;
 311                         interrupt-parent = <&PIC>;
 312                 };
 313                 /* Devices attached to the device controller */
 314                 devicebus@45c {
 315                         #address-cells = <2>;
 316                         #size-cells = <1>;
 317                         compatible = "marvell,mv64306-devctrl";
 318                         reg = <0x45C 0x88>;
 319                         interrupts = <1>;
 320                         interrupt-parent = <&PIC>;
 321                         ranges =        <0 0 0xd8100000 0x10000
 322                                          2 0 0xd8110000 0x10000
 323                                          4 0 0xf8000000 0x8000000>;
 324                         fpga@0,0 {
 325                                 compatible = "sbs,fpga-c2k";
 326                                 reg = <0 0 0x10000>;
 327                         };
 328                         fpga_usart@2,0 {
 329                                 compatible = "sbs,fpga_usart-c2k";
 330                                 reg = <2 0 0x10000>;
 331                         };
 332                         nor_flash@4,0 {
 333                                 compatible = "cfi-flash";
 334                                 reg = <4 0 0x8000000>; /* 128MB */
 335                                 bank-width = <4>;
 336                                 device-width = <1>;
 337                                 #address-cells = <1>;
 338                                 #size-cells = <1>;
 339                                 partition@0 {
 340                                         label = "boot";
 341                                         reg = <0x00000000 0x00080000>;
 342                                 };
 343                                 partition@40000 {
 344                                         label = "kernel";
 345                                         reg = <0x00080000 0x00400000>;
 346                                 };
 347                                 partition@440000 {
 348                                         label = "initrd";
 349                                         reg = <0x00480000 0x00B80000>;
 350                                 };
 351                                 partition@1000000 {
 352                                         label = "rootfs";
 353                                         reg = <0x01000000 0x06800000>;
 354                                 };
 355                                 partition@7800000 {
 356                                         label = "recovery";
 357                                         reg = <0x07800000 0x00800000>;
 358                                         read-only;
 359                                 };
 360                         };
 361                 };
 362         };
 363         chosen {
 364                 linux,stdout-path = &MPSC0;
 365         };
 366 };