| blob | 4b635dc4ecded8c0e4729582ac1e5cc9d0f143bd |
1 /*
2 * MPC8313E RDB Device Tree Source
3 *
4 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8313ERDB";
16 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
32 PowerPC,8313@0 {
33 device_type = "cpu";
34 reg = <0x0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <16384>;
38 i-cache-size = <16384>;
39 timebase-frequency = <0>; // from bootloader
40 bus-frequency = <0>; // from bootloader
41 clock-frequency = <0>; // from bootloader
42 };
43 };
45 memory {
46 device_type = "memory";
47 reg = <0x00000000 0x08000000>; // 128MB at 0
48 };
50 localbus@e0005000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
54 reg = <0xe0005000 0x1000>;
55 interrupts = <77 0x8>;
56 interrupt-parent = <&ipic>;
58 // CS0 and CS1 are swapped when
59 // booting from nand, but the
60 // addresses are the same.
61 ranges = <0x0 0x0 0xfe000000 0x00800000
62 0x1 0x0 0xe2800000 0x00008000
63 0x2 0x0 0xf0000000 0x00020000
64 0x3 0x0 0xfa000000 0x00008000>;
66 flash@0,0 {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 compatible = "cfi-flash";
70 reg = <0x0 0x0 0x800000>;
71 bank-width = <2>;
72 device-width = <1>;
73 };
75 nand@1,0 {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 compatible = "fsl,mpc8313-fcm-nand",
79 "fsl,elbc-fcm-nand";
80 reg = <0x1 0x0 0x2000>;
82 u-boot@0 {
83 reg = <0x0 0x100000>;
84 read-only;
85 };
87 kernel@100000 {
88 reg = <0x100000 0x300000>;
89 };
91 fs@400000 {
92 reg = <0x400000 0x1c00000>;
93 };
94 };
95 };
97 soc8313@e0000000 {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 device_type = "soc";
101 compatible = "simple-bus";
102 ranges = <0x0 0xe0000000 0x00100000>;
103 reg = <0xe0000000 0x00000200>;
104 bus-frequency = <0>;
106 wdt@200 {
107 device_type = "watchdog";
108 compatible = "mpc83xx_wdt";
109 reg = <0x200 0x100>;
110 };
112 sleep-nexus {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 compatible = "simple-bus";
116 sleep = <&pmc 0x03000000>;
117 ranges;
119 i2c@3000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 cell-index = <0>;
123 compatible = "fsl-i2c";
124 reg = <0x3000 0x100>;
125 interrupts = <14 0x8>;
126 interrupt-parent = <&ipic>;
127 dfsrr;
128 rtc@68 {
129 compatible = "dallas,ds1339";
130 reg = <0x68>;
131 };
132 };
134 crypto@30000 {
135 compatible = "fsl,sec2.2", "fsl,sec2.1",
136 "fsl,sec2.0";
137 reg = <0x30000 0x10000>;
138 interrupts = <11 0x8>;
139 interrupt-parent = <&ipic>;
140 fsl,num-channels = <1>;
141 fsl,channel-fifo-len = <24>;
142 fsl,exec-units-mask = <0x4c>;
143 fsl,descriptor-types-mask = <0x0122003f>;
144 };
145 };
147 i2c@3100 {
148 #address-cells = <1>;
149 #size-cells = <0>;
150 cell-index = <1>;
151 compatible = "fsl-i2c";
152 reg = <0x3100 0x100>;
153 interrupts = <15 0x8>;
154 interrupt-parent = <&ipic>;
155 dfsrr;
156 };
158 spi@7000 {
159 cell-index = <0>;
160 compatible = "fsl,spi";
161 reg = <0x7000 0x1000>;
162 interrupts = <16 0x8>;
163 interrupt-parent = <&ipic>;
164 mode = "cpu";
165 };
167 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
168 usb@23000 {
169 compatible = "fsl-usb2-dr";
170 reg = <0x23000 0x1000>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 interrupt-parent = <&ipic>;
174 interrupts = <38 0x8>;
175 phy_type = "utmi_wide";
176 sleep = <&pmc 0x00300000>;
177 };
179 ptp_clock@24E00 {
180 compatible = "fsl,etsec-ptp";
181 reg = <0x24E00 0xB0>;
182 interrupts = <12 0x8 13 0x8>;
183 interrupt-parent = < &ipic >;
184 fsl,tclk-period = <10>;
185 fsl,tmr-prsc = <100>;
186 fsl,tmr-add = <0x999999A4>;
187 fsl,tmr-fiper1 = <0x3B9AC9F6>;
188 fsl,tmr-fiper2 = <0x00018696>;
189 fsl,max-adj = <659999998>;
190 };
192 enet0: ethernet@24000 {
193 #address-cells = <1>;
194 #size-cells = <1>;
195 sleep = <&pmc 0x20000000>;
196 ranges = <0x0 0x24000 0x1000>;
198 cell-index = <0>;
199 device_type = "network";
200 model = "eTSEC";
201 compatible = "gianfar";
202 reg = <0x24000 0x1000>;
203 local-mac-address = [ 00 00 00 00 00 00 ];
204 interrupts = <37 0x8 36 0x8 35 0x8>;
205 interrupt-parent = <&ipic>;
206 tbi-handle = < &tbi0 >;
207 /* Vitesse 7385 isn't on the MDIO bus */
208 fixed-link = <1 1 1000 0 0>;
209 fsl,magic-packet;
211 mdio@520 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,gianfar-mdio";
215 reg = <0x520 0x20>;
216 phy4: ethernet-phy@4 {
217 interrupt-parent = <&ipic>;
218 interrupts = <20 0x8>;
219 reg = <0x4>;
220 };
221 tbi0: tbi-phy@11 {
222 reg = <0x11>;
223 device_type = "tbi-phy";
224 };
225 };
226 };
228 enet1: ethernet@25000 {
229 #address-cells = <1>;
230 #size-cells = <1>;
231 cell-index = <1>;
232 device_type = "network";
233 model = "eTSEC";
234 compatible = "gianfar";
235 reg = <0x25000 0x1000>;
236 ranges = <0x0 0x25000 0x1000>;
237 local-mac-address = [ 00 00 00 00 00 00 ];
238 interrupts = <34 0x8 33 0x8 32 0x8>;
239 interrupt-parent = <&ipic>;
240 tbi-handle = < &tbi1 >;
241 phy-handle = < &phy4 >;
242 sleep = <&pmc 0x10000000>;
243 fsl,magic-packet;
245 mdio@520 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "fsl,gianfar-tbi";
249 reg = <0x520 0x20>;
251 tbi1: tbi-phy@11 {
252 reg = <0x11>;
253 device_type = "tbi-phy";
254 };
255 };
258 };
260 serial0: serial@4500 {
261 cell-index = <0>;
262 device_type = "serial";
263 compatible = "fsl,ns16550", "ns16550";
264 reg = <0x4500 0x100>;
265 clock-frequency = <0>;
266 interrupts = <9 0x8>;
267 interrupt-parent = <&ipic>;
268 };
270 serial1: serial@4600 {
271 cell-index = <1>;
272 device_type = "serial";
273 compatible = "fsl,ns16550", "ns16550";
274 reg = <0x4600 0x100>;
275 clock-frequency = <0>;
276 interrupts = <10 0x8>;
277 interrupt-parent = <&ipic>;
278 };
280 /* IPIC
281 * interrupts cell = <intr #, sense>
282 * sense values match linux IORESOURCE_IRQ_* defines:
283 * sense == 8: Level, low assertion
284 * sense == 2: Edge, high-to-low change
285 */
286 ipic: pic@700 {
287 interrupt-controller;
288 #address-cells = <0>;
289 #interrupt-cells = <2>;
290 reg = <0x700 0x100>;
291 device_type = "ipic";
292 };
294 pmc: power@b00 {
295 compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
296 reg = <0xb00 0x100 0xa00 0x100>;
297 interrupts = <80 8>;
298 interrupt-parent = <&ipic>;
299 fsl,mpc8313-wakeup-timer = <>m1>;
301 /* Remove this (or change to "okay") if you have
302 * a REVA3 or later board, if you apply one of the
303 * workarounds listed in section 8.5 of the board
304 * manual, or if you are adapting this device tree
305 * to a different board.
306 */
307 status = "fail";
308 };
310 gtm1: timer@500 {
311 compatible = "fsl,mpc8313-gtm", "fsl,gtm";
312 reg = <0x500 0x100>;
313 interrupts = <90 8 78 8 84 8 72 8>;
314 interrupt-parent = <&ipic>;
315 };
317 timer@600 {
318 compatible = "fsl,mpc8313-gtm", "fsl,gtm";
319 reg = <0x600 0x100>;
320 interrupts = <91 8 79 8 85 8 73 8>;
321 interrupt-parent = <&ipic>;
322 };
323 };
325 sleep-nexus {
326 #address-cells = <1>;
327 #size-cells = <1>;
328 compatible = "simple-bus";
329 sleep = <&pmc 0x00010000>;
330 ranges;
332 pci0: pci@e0008500 {
333 cell-index = <1>;
334 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
335 interrupt-map = <
336 /* IDSEL 0x0E -mini PCI */
337 0x7000 0x0 0x0 0x1 &ipic 18 0x8
338 0x7000 0x0 0x0 0x2 &ipic 18 0x8
339 0x7000 0x0 0x0 0x3 &ipic 18 0x8
340 0x7000 0x0 0x0 0x4 &ipic 18 0x8
342 /* IDSEL 0x0F - PCI slot */
343 0x7800 0x0 0x0 0x1 &ipic 17 0x8
344 0x7800 0x0 0x0 0x2 &ipic 18 0x8
345 0x7800 0x0 0x0 0x3 &ipic 17 0x8
346 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
347 interrupt-parent = <&ipic>;
348 interrupts = <66 0x8>;
349 bus-range = <0x0 0x0>;
350 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
351 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
352 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
353 clock-frequency = <66666666>;
354 #interrupt-cells = <1>;
355 #size-cells = <2>;
356 #address-cells = <3>;
357 reg = <0xe0008500 0x100 /* internal registers */
358 0xe0008300 0x8>; /* config space access registers */
359 compatible = "fsl,mpc8349-pci";
360 device_type = "pci";
361 };
363 dma@82a8 {
364 #address-cells = <1>;
365 #size-cells = <1>;
366 compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
367 reg = <0xe00082a8 4>;
368 ranges = <0 0xe0008100 0x1a8>;
369 interrupt-parent = <&ipic>;
370 interrupts = <71 8>;
372 dma-channel@0 {
373 compatible = "fsl,mpc8313-dma-channel",
374 "fsl,elo-dma-channel";
375 reg = <0 0x28>;
376 interrupt-parent = <&ipic>;
377 interrupts = <71 8>;
378 cell-index = <0>;
379 };
381 dma-channel@80 {
382 compatible = "fsl,mpc8313-dma-channel",
383 "fsl,elo-dma-channel";
384 reg = <0x80 0x28>;
385 interrupt-parent = <&ipic>;
386 interrupts = <71 8>;
387 cell-index = <1>;
388 };
390 dma-channel@100 {
391 compatible = "fsl,mpc8313-dma-channel",
392 "fsl,elo-dma-channel";
393 reg = <0x100 0x28>;
394 interrupt-parent = <&ipic>;
395 interrupts = <71 8>;
396 cell-index = <2>;
397 };
399 dma-channel@180 {
400 compatible = "fsl,mpc8313-dma-channel",
401 "fsl,elo-dma-channel";
402 reg = <0x180 0x28>;
403 interrupt-parent = <&ipic>;
404 interrupts = <71 8>;
405 cell-index = <3>;
406 };
407 };
408 };
409 };