2 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
4 * Copyright (C) 2006-2009 Pengutronix
5 * Sascha Hauer <s.hauer@pengutronix.de>
6 * Juergen Beisert <j.beisert@pengutronix.de>
7 * Wolfram Sang <w.sang@pengutronix.de>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 /include/ "mpc5200b.dtsi"
17 &gpt0 { fsl,has-wdt; };
18 &gpt2 { gpio-controller; };
19 &gpt3 { gpio-controller; };
20 &gpt4 { gpio-controller; };
21 &gpt5 { gpio-controller; };
22 &gpt6 { gpio-controller; };
23 &gpt7 { gpio-controller; };
26 model = "phytec,pcm032";
27 compatible = "phytec,pcm032";
30 reg = <0x00000000 0x08000000>; // 128MB
34 psc@2000 { /* PSC1 is ac97 */
35 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
39 /* PSC2 port is used by CAN1/2 */
44 psc@2400 { /* PSC3 in UART mode */
45 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
58 psc@2c00 { /* PSC6 in UART mode */
59 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
67 phy0: ethernet-phy@0 {
74 compatible = "nxp,pcf8563";
78 compatible = "catalyst,24c32", "atmel,24c32";
86 interrupt-map-mask = <0xf800 0 0 7>;
87 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
88 0xc000 0 0 2 &mpc5200_pic 1 1 3
89 0xc000 0 0 3 &mpc5200_pic 1 2 3
90 0xc000 0 0 4 &mpc5200_pic 1 3 3
92 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
93 0xc800 0 0 2 &mpc5200_pic 1 2 3
94 0xc800 0 0 3 &mpc5200_pic 1 3 3
95 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
96 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
97 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
98 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
102 ranges = <0 0 0xfe000000 0x02000000
103 1 0 0xfc000000 0x02000000
104 2 0 0xfbe00000 0x00200000
105 3 0 0xf9e00000 0x02000000
106 4 0 0xf7e00000 0x02000000
107 5 0 0xe6000000 0x02000000
108 6 0 0xe8000000 0x02000000
109 7 0 0xea000000 0x02000000>;
112 compatible = "cfi-flash";
113 reg = <0 0 0x02000000>;
116 #address-cells = <1>;
120 reg = <0x00000000 0x00040000>;
124 reg = <0x00040000 0x001c0000>;
128 reg = <0x00200000 0x01d00000>;
132 reg = <0x01f00000 0x00040000>;
136 reg = <0x01f40000 0x00040000>;
140 reg = <0x01f80000 0x00040000>;
144 reg = <0x01fc0000 0x00040000>;
149 compatible = "mtd-ram";
150 reg = <2 0 0x00200000>;
155 * example snippets for FPGA
158 * compatible = "fpga_driver";
159 * reg = <3 0 0x02000000>;
164 * compatible = "fpga_driver";
165 * reg = <4 0 0x02000000>;
171 * example snippets for free chipselects
174 * compatible = "custom_driver";
175 * reg = <5 0 0x02000000>;
179 * compatible = "custom_driver";
180 * reg = <6 0 0x02000000>;
184 * compatible = "custom_driver";
185 * reg = <7 0 0x02000000>;