arch/powerpc/include/asm/page_32.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_PAGE_32_H
   3 #define _ASM_POWERPC_PAGE_32_H
   4
   5 #include <asm/cache.h>
   6
   7 #if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
   8 #if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
   9 #error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
  10 #endif
  11 #endif
  12
  13 #define VM_DATA_DEFAULT_FLAGS   VM_DATA_DEFAULT_FLAGS32
  14
  15 #ifdef CONFIG_NOT_COHERENT_CACHE
  16 #define ARCH_DMA_MINALIGN       L1_CACHE_BYTES
  17 #endif
  18
  19 #ifdef CONFIG_PTE_64BIT
  20 #define PTE_FLAGS_OFFSET        4       /* offset of PTE flags, in bytes */
  21 #else
  22 #define PTE_FLAGS_OFFSET        0
  23 #endif
  24
  25 #ifdef CONFIG_PPC_256K_PAGES
  26 #define PTE_SHIFT       (PAGE_SHIFT - PTE_T_LOG2 - 2)   /* 1/4 of a page */
  27 #else
  28 #define PTE_SHIFT       (PAGE_SHIFT - PTE_T_LOG2)       /* full page */
  29 #endif
  30
  31 #ifndef __ASSEMBLY__
  32 /*
  33  * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
  34  * physical addressing.
  35  */
  36 #ifdef CONFIG_PTE_64BIT
  37 typedef unsigned long long pte_basic_t;
  38 #else
  39 typedef unsigned long pte_basic_t;
  40 #endif
  41
  42 /*
  43  * Clear page using the dcbz instruction, which doesn't cause any
  44  * memory traffic (except to write out any cache lines which get
  45  * displaced).  This only works on cacheable memory.
  46  */
  47 static inline void clear_page(void *addr)
  48 {
  49         unsigned int i;
  50
  51         for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
  52                 dcbz(addr);
  53 }
  54 extern void copy_page(void *to, void *from);
  55
  56 #include <asm-generic/getorder.h>
  57
  58 #define PGD_T_LOG2      (__builtin_ffs(sizeof(pgd_t)) - 1)
  59 #define PTE_T_LOG2      (__builtin_ffs(sizeof(pte_t)) - 1)
  60
  61 #endif /* __ASSEMBLY__ */
  62
  63 #endif /* _ASM_POWERPC_PAGE_32_H */