arch/powerpc/include/asm/processor.h

   1 #ifndef _ASM_POWERPC_PROCESSOR_H
   2 #define _ASM_POWERPC_PROCESSOR_H
   3
   4 /*
   5  * Copyright (C) 2001 PPC 64 Team, IBM Corp
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12
  13 #include <asm/reg.h>
  14
  15 #ifdef CONFIG_VSX
  16 #define TS_FPRWIDTH 2
  17
  18 #ifdef __BIG_ENDIAN__
  19 #define TS_FPROFFSET 0
  20 #define TS_VSRLOWOFFSET 1
  21 #else
  22 #define TS_FPROFFSET 1
  23 #define TS_VSRLOWOFFSET 0
  24 #endif
  25
  26 #else
  27 #define TS_FPRWIDTH 1
  28 #define TS_FPROFFSET 0
  29 #endif
  30
  31 #ifdef CONFIG_PPC64
  32 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
  33 #define PPR_PRIORITY 3
  34 #ifdef __ASSEMBLY__
  35 #define INIT_PPR (PPR_PRIORITY << 50)
  36 #else
  37 #define INIT_PPR ((u64)PPR_PRIORITY << 50)
  38 #endif /* __ASSEMBLY__ */
  39 #endif /* CONFIG_PPC64 */
  40
  41 #ifndef __ASSEMBLY__
  42 #include <linux/compiler.h>
  43 #include <linux/cache.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/types.h>
  46 #include <asm/hw_breakpoint.h>
  47
  48 /* We do _not_ want to define new machine types at all, those must die
  49  * in favor of using the device-tree
  50  * -- BenH.
  51  */
  52
  53 /* PREP sub-platform types. Unused */
  54 #define _PREP_Motorola  0x01    /* motorola prep */
  55 #define _PREP_Firm      0x02    /* firmworks prep */
  56 #define _PREP_IBM       0x00    /* ibm prep */
  57 #define _PREP_Bull      0x03    /* bull prep */
  58
  59 /* CHRP sub-platform types. These are arbitrary */
  60 #define _CHRP_Motorola  0x04    /* motorola chrp, the cobra */
  61 #define _CHRP_IBM       0x05    /* IBM chrp, the longtrail and longtrail 2 */
  62 #define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
  63 #define _CHRP_briq      0x07    /* TotalImpact's briQ */
  64
  65 #if defined(__KERNEL__) && defined(CONFIG_PPC32)
  66
  67 extern int _chrp_type;
  68
  69 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
  70
  71 /*
  72  * Default implementation of macro that returns current
  73  * instruction pointer ("program counter").
  74  */
  75 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  76
  77 /* Macros for adjusting thread priority (hardware multi-threading) */
  78 #define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
  79 #define HMT_low()        asm volatile("or 1,1,1      # low priority")
  80 #define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
  81 #define HMT_medium()     asm volatile("or 2,2,2      # medium priority")
  82 #define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
  83 #define HMT_high()       asm volatile("or 3,3,3      # high priority")
  84
  85 #ifdef __KERNEL__
  86
  87 struct task_struct;
  88 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
  89 void release_thread(struct task_struct *);
  90
  91 #ifdef CONFIG_PPC32
  92
  93 #if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
  94 #error User TASK_SIZE overlaps with KERNEL_START address
  95 #endif
  96 #define TASK_SIZE       (CONFIG_TASK_SIZE)
  97
  98 /* This decides where the kernel will search for a free chunk of vm
  99  * space during mmap's.
 100  */
 101 #define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
 102 #endif
 103
 104 #ifdef CONFIG_PPC64
 105 /*
 106  * 64-bit user address space can have multiple limits
 107  * For now supported values are:
 108  */
 109 #define TASK_SIZE_64TB  (0x0000400000000000UL)
 110 #define TASK_SIZE_128TB (0x0000800000000000UL)
 111 #define TASK_SIZE_512TB (0x0002000000000000UL)
 112
 113 /*
 114  * For now 512TB is only supported with book3s and 64K linux page size.
 115  */
 116 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_64K_PAGES)
 117 /*
 118  * Max value currently used:
 119  */
 120 #define TASK_SIZE_USER64                TASK_SIZE_512TB
 121 #define DEFAULT_MAP_WINDOW_USER64       TASK_SIZE_128TB
 122 #else
 123 #define TASK_SIZE_USER64                TASK_SIZE_64TB
 124 #define DEFAULT_MAP_WINDOW_USER64       TASK_SIZE_64TB
 125 #endif
 126
 127 /*
 128  * 32-bit user address space is 4GB - 1 page
 129  * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 130  */
 131 #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
 132
 133 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
 134                 TASK_SIZE_USER32 : TASK_SIZE_USER64)
 135 #define TASK_SIZE         TASK_SIZE_OF(current)
 136 /* This decides where the kernel will search for a free chunk of vm
 137  * space during mmap's.
 138  */
 139 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
 140 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(DEFAULT_MAP_WINDOW_USER64 / 4))
 141
 142 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
 143                 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
 144 #endif
 145
 146 /*
 147  * Initial task size value for user applications. For book3s 64 we start
 148  * with 128TB and conditionally enable upto 512TB
 149  */
 150 #ifdef CONFIG_PPC_BOOK3S_64
 151 #define DEFAULT_MAP_WINDOW      ((is_32bit_task()) ?                    \
 152                                  TASK_SIZE_USER32 : DEFAULT_MAP_WINDOW_USER64)
 153 #else
 154 #define DEFAULT_MAP_WINDOW      TASK_SIZE
 155 #endif
 156
 157 #ifdef __powerpc64__
 158
 159 #define STACK_TOP_USER64 DEFAULT_MAP_WINDOW_USER64
 160 #define STACK_TOP_USER32 TASK_SIZE_USER32
 161
 162 #define STACK_TOP (is_32bit_task() ? \
 163                    STACK_TOP_USER32 : STACK_TOP_USER64)
 164
 165 #define STACK_TOP_MAX TASK_SIZE_USER64
 166
 167 #else /* __powerpc64__ */
 168
 169 #define STACK_TOP TASK_SIZE
 170 #define STACK_TOP_MAX   STACK_TOP
 171
 172 #endif /* __powerpc64__ */
 173
 174 typedef struct {
 175         unsigned long seg;
 176 } mm_segment_t;
 177
 178 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
 179 #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
 180
 181 /* FP and VSX 0-31 register set */
 182 struct thread_fp_state {
 183         u64     fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
 184         u64     fpscr;          /* Floating point status */
 185 };
 186
 187 /* Complete AltiVec register set including VSCR */
 188 struct thread_vr_state {
 189         vector128       vr[32] __attribute__((aligned(16)));
 190         vector128       vscr __attribute__((aligned(16)));
 191 };
 192
 193 struct debug_reg {
 194 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 195         /*
 196          * The following help to manage the use of Debug Control Registers
 197          * om the BookE platforms.
 198          */
 199         uint32_t        dbcr0;
 200         uint32_t        dbcr1;
 201 #ifdef CONFIG_BOOKE
 202         uint32_t        dbcr2;
 203 #endif
 204         /*
 205          * The stored value of the DBSR register will be the value at the
 206          * last debug interrupt. This register can only be read from the
 207          * user (will never be written to) and has value while helping to
 208          * describe the reason for the last debug trap.  Torez
 209          */
 210         uint32_t        dbsr;
 211         /*
 212          * The following will contain addresses used by debug applications
 213          * to help trace and trap on particular address locations.
 214          * The bits in the Debug Control Registers above help define which
 215          * of the following registers will contain valid data and/or addresses.
 216          */
 217         unsigned long   iac1;
 218         unsigned long   iac2;
 219 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 220         unsigned long   iac3;
 221         unsigned long   iac4;
 222 #endif
 223         unsigned long   dac1;
 224         unsigned long   dac2;
 225 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 226         unsigned long   dvc1;
 227         unsigned long   dvc2;
 228 #endif
 229 #endif
 230 };
 231
 232 struct thread_struct {
 233         unsigned long   ksp;            /* Kernel stack pointer */
 234
 235 #ifdef CONFIG_PPC64
 236         unsigned long   ksp_vsid;
 237 #endif
 238         struct pt_regs  *regs;          /* Pointer to saved register state */
 239         mm_segment_t    fs;             /* for get_fs() validation */
 240 #ifdef CONFIG_BOOKE
 241         /* BookE base exception scratch space; align on cacheline */
 242         unsigned long   normsave[8] ____cacheline_aligned;
 243 #endif
 244 #ifdef CONFIG_PPC32
 245         void            *pgdir;         /* root of page-table tree */
 246         unsigned long   ksp_limit;      /* if ksp <= ksp_limit stack overflow */
 247 #endif
 248         /* Debug Registers */
 249         struct debug_reg debug;
 250         struct thread_fp_state  fp_state;
 251         struct thread_fp_state  *fp_save_area;
 252         int             fpexc_mode;     /* floating-point exception mode */
 253         unsigned int    align_ctl;      /* alignment handling control */
 254 #ifdef CONFIG_PPC64
 255         unsigned long   start_tb;       /* Start purr when proc switched in */
 256         unsigned long   accum_tb;       /* Total accumulated purr for process */
 257 #endif
 258 #ifdef CONFIG_HAVE_HW_BREAKPOINT
 259         struct perf_event *ptrace_bps[HBP_NUM];
 260         /*
 261          * Helps identify source of single-step exception and subsequent
 262          * hw-breakpoint enablement
 263          */
 264         struct perf_event *last_hit_ubp;
 265 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 266         struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
 267         unsigned long   trap_nr;        /* last trap # on this thread */
 268         u8 load_fp;
 269 #ifdef CONFIG_ALTIVEC
 270         u8 load_vec;
 271         struct thread_vr_state vr_state;
 272         struct thread_vr_state *vr_save_area;
 273         unsigned long   vrsave;
 274         int             used_vr;        /* set if process has used altivec */
 275 #endif /* CONFIG_ALTIVEC */
 276 #ifdef CONFIG_VSX
 277         /* VSR status */
 278         int             used_vsr;       /* set if process has used VSX */
 279 #endif /* CONFIG_VSX */
 280 #ifdef CONFIG_SPE
 281         unsigned long   evr[32];        /* upper 32-bits of SPE regs */
 282         u64             acc;            /* Accumulator */
 283         unsigned long   spefscr;        /* SPE & eFP status */
 284         unsigned long   spefscr_last;   /* SPEFSCR value on last prctl
 285                                            call or trap return */
 286         int             used_spe;       /* set if process has used spe */
 287 #endif /* CONFIG_SPE */
 288 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 289         u8      load_tm;
 290         u64             tm_tfhar;       /* Transaction fail handler addr */
 291         u64             tm_texasr;      /* Transaction exception & summary */
 292         u64             tm_tfiar;       /* Transaction fail instr address reg */
 293         struct pt_regs  ckpt_regs;      /* Checkpointed registers */
 294
 295         unsigned long   tm_tar;
 296         unsigned long   tm_ppr;
 297         unsigned long   tm_dscr;
 298
 299         /*
 300          * Checkpointed FP and VSX 0-31 register set.
 301          *
 302          * When a transaction is active/signalled/scheduled etc., *regs is the
 303          * most recent set of/speculated GPRs with ckpt_regs being the older
 304          * checkpointed regs to which we roll back if transaction aborts.
 305          *
 306          * These are analogous to how ckpt_regs and pt_regs work
 307          */
 308         struct thread_fp_state ckfp_state; /* Checkpointed FP state */
 309         struct thread_vr_state ckvr_state; /* Checkpointed VR state */
 310         unsigned long   ckvrsave; /* Checkpointed VRSAVE */
 311 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 312 #ifdef CONFIG_PPC_MEM_KEYS
 313         unsigned long   amr;
 314         unsigned long   iamr;
 315         unsigned long   uamor;
 316 #endif
 317 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
 318         void*           kvm_shadow_vcpu; /* KVM internal data */
 319 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
 320 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
 321         struct kvm_vcpu *kvm_vcpu;
 322 #endif
 323 #ifdef CONFIG_PPC64
 324         unsigned long   dscr;
 325         unsigned long   fscr;
 326         /*
 327          * This member element dscr_inherit indicates that the process
 328          * has explicitly attempted and changed the DSCR register value
 329          * for itself. Hence kernel wont use the default CPU DSCR value
 330          * contained in the PACA structure anymore during process context
 331          * switch. Once this variable is set, this behaviour will also be
 332          * inherited to all the children of this process from that point
 333          * onwards.
 334          */
 335         int             dscr_inherit;
 336         unsigned long   ppr;    /* used to save/restore SMT priority */
 337         unsigned long   tidr;
 338 #endif
 339 #ifdef CONFIG_PPC_BOOK3S_64
 340         unsigned long   tar;
 341         unsigned long   ebbrr;
 342         unsigned long   ebbhr;
 343         unsigned long   bescr;
 344         unsigned long   siar;
 345         unsigned long   sdar;
 346         unsigned long   sier;
 347         unsigned long   mmcr2;
 348         unsigned        mmcr0;
 349
 350         unsigned        used_ebb;
 351         unsigned int    used_vas;
 352 #endif
 353 };
 354
 355 #define ARCH_MIN_TASKALIGN 16
 356
 357 #define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 358 #define INIT_SP_LIMIT \
 359         (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
 360
 361 #ifdef CONFIG_SPE
 362 #define SPEFSCR_INIT \
 363         .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
 364         .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
 365 #else
 366 #define SPEFSCR_INIT
 367 #endif
 368
 369 #ifdef CONFIG_PPC32
 370 #define INIT_THREAD { \
 371         .ksp = INIT_SP, \
 372         .ksp_limit = INIT_SP_LIMIT, \
 373         .fs = KERNEL_DS, \
 374         .pgdir = swapper_pg_dir, \
 375         .fpexc_mode = MSR_FE0 | MSR_FE1, \
 376         SPEFSCR_INIT \
 377 }
 378 #else
 379 #define INIT_THREAD  { \
 380         .ksp = INIT_SP, \
 381         .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
 382         .fs = KERNEL_DS, \
 383         .fpexc_mode = 0, \
 384         .ppr = INIT_PPR, \
 385         .fscr = FSCR_TAR | FSCR_EBB \
 386 }
 387 #endif
 388
 389 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.regs)
 390
 391 unsigned long get_wchan(struct task_struct *p);
 392
 393 #define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 394 #define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 395
 396 /* Get/set floating-point exception mode */
 397 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
 398 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
 399
 400 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 401 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
 402
 403 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
 404 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
 405
 406 extern int get_endian(struct task_struct *tsk, unsigned long adr);
 407 extern int set_endian(struct task_struct *tsk, unsigned int val);
 408
 409 #define GET_UNALIGN_CTL(tsk, adr)       get_unalign_ctl((tsk), (adr))
 410 #define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
 411
 412 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
 413 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
 414
 415 extern void load_fp_state(struct thread_fp_state *fp);
 416 extern void store_fp_state(struct thread_fp_state *fp);
 417 extern void load_vr_state(struct thread_vr_state *vr);
 418 extern void store_vr_state(struct thread_vr_state *vr);
 419
 420 static inline unsigned int __unpack_fe01(unsigned long msr_bits)
 421 {
 422         return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
 423 }
 424
 425 static inline unsigned long __pack_fe01(unsigned int fpmode)
 426 {
 427         return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
 428 }
 429
 430 #ifdef CONFIG_PPC64
 431 #define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
 432
 433 #define spin_begin()    HMT_low()
 434
 435 #define spin_cpu_relax()        barrier()
 436
 437 #define spin_cpu_yield()        spin_cpu_relax()
 438
 439 #define spin_end()      HMT_medium()
 440
 441 #define spin_until_cond(cond)                                   \
 442 do {                                                            \
 443         if (unlikely(!(cond))) {                                \
 444                 spin_begin();                                   \
 445                 do {                                            \
 446                         spin_cpu_relax();                       \
 447                 } while (!(cond));                              \
 448                 spin_end();                                     \
 449         }                                                       \
 450 } while (0)
 451
 452 #else
 453 #define cpu_relax()     barrier()
 454 #endif
 455
 456 /* Check that a certain kernel stack pointer is valid in task_struct p */
 457 int validate_sp(unsigned long sp, struct task_struct *p,
 458                        unsigned long nbytes);
 459
 460 /*
 461  * Prefetch macros.
 462  */
 463 #define ARCH_HAS_PREFETCH
 464 #define ARCH_HAS_PREFETCHW
 465 #define ARCH_HAS_SPINLOCK_PREFETCH
 466
 467 static inline void prefetch(const void *x)
 468 {
 469         if (unlikely(!x))
 470                 return;
 471
 472         __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 473 }
 474
 475 static inline void prefetchw(const void *x)
 476 {
 477         if (unlikely(!x))
 478                 return;
 479
 480         __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 481 }
 482
 483 #define spin_lock_prefetch(x)   prefetchw(x)
 484
 485 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 486
 487 #ifdef CONFIG_PPC64
 488 static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
 489 {
 490         if (is_32)
 491                 return sp & 0x0ffffffffUL;
 492         return sp;
 493 }
 494 #else
 495 static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
 496 {
 497         return sp;
 498 }
 499 #endif
 500
 501 extern unsigned long cpuidle_disable;
 502 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 503
 504 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 505 extern unsigned long power7_idle_insn(unsigned long type); /* PNV_THREAD_NAP/etc*/
 506 extern void power7_idle_type(unsigned long type);
 507 extern unsigned long power9_idle_stop(unsigned long psscr_val);
 508 extern void power9_idle_type(unsigned long stop_psscr_val,
 509                               unsigned long stop_psscr_mask);
 510
 511 extern void flush_instruction_cache(void);
 512 extern void hard_reset_now(void);
 513 extern void poweroff_now(void);
 514 extern int fix_alignment(struct pt_regs *);
 515 extern void cvt_fd(float *from, double *to);
 516 extern void cvt_df(double *from, float *to);
 517 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 518
 519 #ifdef CONFIG_PPC64
 520 /*
 521  * We handle most unaligned accesses in hardware. On the other hand
 522  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 523  * powers of 2 writes until it reaches sufficient alignment).
 524  *
 525  * Based on this we disable the IP header alignment in network drivers.
 526  */
 527 #define NET_IP_ALIGN    0
 528 #endif
 529
 530 #endif /* __KERNEL__ */
 531 #endif /* __ASSEMBLY__ */
 532 #endif /* _ASM_POWERPC_PROCESSOR_H */