| blob | a61151a6ea5e82f8edc5828d923d80b07863182a |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 *
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
14 *
15 * This file contains the entry point for the 64-bit kernel along
16 * with some early initialization code common to all 64-bit powerpc
17 * variants.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
25 #include <linux/threads.h>
26 #include <linux/init.h>
27 #include <asm/reg.h>
28 #include <asm/page.h>
29 #include <asm/mmu.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/head-64.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/bug.h>
34 #include <asm/cputable.h>
35 #include <asm/setup.h>
36 #include <asm/hvcall.h>
37 #include <asm/thread_info.h>
38 #include <asm/firmware.h>
39 #include <asm/page_64.h>
40 #include <asm/irqflags.h>
41 #include <asm/kvm_book3s_asm.h>
42 #include <asm/ptrace.h>
43 #include <asm/hw_irq.h>
44 #include <asm/cputhreads.h>
45 #include <asm/ppc-opcode.h>
46 #include <asm/export.h>
48 /* The physical memory is laid out such that the secondary processor
49 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
50 * using the layout described in exceptions-64s.S
51 */
53 /*
54 * Entering into this code we make the following assumptions:
55 *
56 * For pSeries or server processors:
57 * 1. The MMU is off & open firmware is running in real mode.
58 * 2. The primary CPU enters at __start.
59 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
60 * CPUs will enter as directed by "start-cpu" RTAS call, which is
61 * generic_secondary_smp_init, with PIR in r3.
62 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
63 * directed by the "start-cpu" RTS call, with PIR in r3.
64 * -or- For OPAL entry:
65 * 1. The MMU is off, processor in HV mode.
66 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
67 * in r8, and entry in r9 for debugging purposes.
68 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
69 * is at generic_secondary_smp_init, with PIR in r3.
70 *
71 * For Book3E processors:
72 * 1. The MMU is on running in AS0 in a state defined in ePAPR
73 * 2. The kernel is entered at __start
74 */
76 OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
77 USE_FIXED_SECTION(first_256B)
78 /*
79 * Offsets are relative from the start of fixed section, and
80 * first_256B starts at 0. Offsets are a bit easier to use here
81 * than the fixed section entry macros.
82 */
83 . = 0x0
84 _GLOBAL(__start)
85 /* NOP this out unconditionally */
86 BEGIN_FTR_SECTION
87 FIXUP_ENDIAN
88 b __start_initialization_multiplatform
89 END_FTR_SECTION(0, 1)
91 /* Catch branch to 0 in real mode */
92 trap
94 /* Secondary processors spin on this value until it becomes non-zero.
95 * When non-zero, it contains the real address of the function the cpu
96 * should jump to.
97 */
98 .balign 8
99 .globl __secondary_hold_spinloop
100 __secondary_hold_spinloop:
101 .8byte 0x0
103 /* Secondary processors write this value with their cpu # */
104 /* after they enter the spin loop immediately below. */
105 .globl __secondary_hold_acknowledge
106 __secondary_hold_acknowledge:
107 .8byte 0x0
109 #ifdef CONFIG_RELOCATABLE
110 /* This flag is set to 1 by a loader if the kernel should run
111 * at the loaded address instead of the linked address. This
112 * is used by kexec-tools to keep the the kdump kernel in the
113 * crash_kernel region. The loader is responsible for
114 * observing the alignment requirement.
115 */
117 #ifdef CONFIG_RELOCATABLE_TEST
118 #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
119 #else
120 #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
121 #endif
123 /* Do not move this variable as kexec-tools knows about it. */
124 . = 0x5c
125 .globl __run_at_load
126 __run_at_load:
127 DEFINE_FIXED_SYMBOL(__run_at_load)
128 .long RUN_AT_LOAD_DEFAULT
129 #endif
131 . = 0x60
132 /*
133 * The following code is used to hold secondary processors
134 * in a spin loop after they have entered the kernel, but
135 * before the bulk of the kernel has been relocated. This code
136 * is relocated to physical address 0x60 before prom_init is run.
137 * All of it must fit below the first exception vector at 0x100.
138 * Use .globl here not _GLOBAL because we want __secondary_hold
139 * to be the actual text address, not a descriptor.
140 */
141 .globl __secondary_hold
142 __secondary_hold:
143 FIXUP_ENDIAN
144 #ifndef CONFIG_PPC_BOOK3E
145 mfmsr r24
146 ori r24,r24,MSR_RI
147 mtmsrd r24 /* RI on */
148 #endif
149 /* Grab our physical cpu number */
150 mr r24,r3
151 /* stash r4 for book3e */
152 mr r25,r4
154 /* Tell the master cpu we're here */
155 /* Relocation is off & we are located at an address less */
156 /* than 0x100, so only need to grab low order offset. */
157 std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0)
158 sync
160 li r26,0
161 #ifdef CONFIG_PPC_BOOK3E
162 tovirt(r26,r26)
163 #endif
164 /* All secondary cpus wait here until told to start. */
165 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26)
166 cmpdi 0,r12,0
167 beq 100b
169 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
170 #ifdef CONFIG_PPC_BOOK3E
171 tovirt(r12,r12)
172 #endif
173 mtctr r12
174 mr r3,r24
175 /*
176 * it may be the case that other platforms have r4 right to
177 * begin with, this gives us some safety in case it is not
178 */
179 #ifdef CONFIG_PPC_BOOK3E
180 mr r4,r25
181 #else
182 li r4,0
183 #endif
184 /* Make sure that patched code is visible */
185 isync
186 bctr
187 #else
188 BUG_OPCODE
189 #endif
190 CLOSE_FIXED_SECTION(first_256B)
192 /* This value is used to mark exception frames on the stack. */
193 .section ".toc","aw"
194 exception_marker:
195 .tc ID_72656773_68657265[TC],0x7265677368657265
196 .previous
198 /*
199 * On server, we include the exception vectors code here as it
200 * relies on absolute addressing which is only possible within
201 * this compilation unit
202 */
203 #ifdef CONFIG_PPC_BOOK3S
204 #include "exceptions-64s.S"
205 #else
206 OPEN_TEXT_SECTION(0x100)
207 #endif
209 USE_TEXT_SECTION()
211 #ifdef CONFIG_PPC_BOOK3E
212 /*
213 * The booting_thread_hwid holds the thread id we want to boot in cpu
214 * hotplug case. It is set by cpu hotplug code, and is invalid by default.
215 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
216 * bit field.
217 */
218 .globl booting_thread_hwid
219 booting_thread_hwid:
220 .long INVALID_THREAD_HWID
221 .align 3
222 /*
223 * start a thread in the same core
224 * input parameters:
225 * r3 = the thread physical id
226 * r4 = the entry point where thread starts
227 */
228 _GLOBAL(book3e_start_thread)
229 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
230 cmpwi r3, 0
231 beq 10f
232 cmpwi r3, 1
233 beq 11f
234 /* If the thread id is invalid, just exit. */
235 b 13f
236 10:
237 MTTMR(TMRN_IMSR0, 5)
238 MTTMR(TMRN_INIA0, 4)
239 b 12f
240 11:
241 MTTMR(TMRN_IMSR1, 5)
242 MTTMR(TMRN_INIA1, 4)
243 12:
244 isync
245 li r6, 1
246 sld r6, r6, r3
247 mtspr SPRN_TENS, r6
248 13:
249 blr
251 /*
252 * stop a thread in the same core
253 * input parameter:
254 * r3 = the thread physical id
255 */
256 _GLOBAL(book3e_stop_thread)
257 cmpwi r3, 0
258 beq 10f
259 cmpwi r3, 1
260 beq 10f
261 /* If the thread id is invalid, just exit. */
262 b 13f
263 10:
264 li r4, 1
265 sld r4, r4, r3
266 mtspr SPRN_TENC, r4
267 13:
268 blr
270 _GLOBAL(fsl_secondary_thread_init)
271 mfspr r4,SPRN_BUCSR
273 /* Enable branch prediction */
274 lis r3,BUCSR_INIT@h
275 ori r3,r3,BUCSR_INIT@l
276 mtspr SPRN_BUCSR,r3
277 isync
279 /*
280 * Fix PIR to match the linear numbering in the device tree.
281 *
282 * On e6500, the reset value of PIR uses the low three bits for
283 * the thread within a core, and the upper bits for the core
284 * number. There are two threads per core, so shift everything
285 * but the low bit right by two bits so that the cpu numbering is
286 * continuous.
287 *
288 * If the old value of BUCSR is non-zero, this thread has run
289 * before. Thus, we assume we are coming from kexec or a similar
290 * scenario, and PIR is already set to the correct value. This
291 * is a bit of a hack, but there are limited opportunities for
292 * getting information into the thread and the alternatives
293 * seemed like they'd be overkill. We can't tell just by looking
294 * at the old PIR value which state it's in, since the same value
295 * could be valid for one thread out of reset and for a different
296 * thread in Linux.
297 */
299 mfspr r3, SPRN_PIR
300 cmpwi r4,0
301 bne 1f
302 rlwimi r3, r3, 30, 2, 30
303 mtspr SPRN_PIR, r3
304 1:
305 #endif
307 _GLOBAL(generic_secondary_thread_init)
308 mr r24,r3
310 /* turn on 64-bit mode */
311 bl enable_64b_mode
313 /* get a valid TOC pointer, wherever we're mapped at */
314 bl relative_toc
315 tovirt(r2,r2)
317 #ifdef CONFIG_PPC_BOOK3E
318 /* Book3E initialization */
319 mr r3,r24
320 bl book3e_secondary_thread_init
321 #endif
322 b generic_secondary_common_init
324 /*
325 * On pSeries and most other platforms, secondary processors spin
326 * in the following code.
327 * At entry, r3 = this processor's number (physical cpu id)
328 *
329 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
330 * this core already exists (setup via some other mechanism such
331 * as SCOM before entry).
332 */
333 _GLOBAL(generic_secondary_smp_init)
334 FIXUP_ENDIAN
335 mr r24,r3
336 mr r25,r4
338 /* turn on 64-bit mode */
339 bl enable_64b_mode
341 /* get a valid TOC pointer, wherever we're mapped at */
342 bl relative_toc
343 tovirt(r2,r2)
345 #ifdef CONFIG_PPC_BOOK3E
346 /* Book3E initialization */
347 mr r3,r24
348 mr r4,r25
349 bl book3e_secondary_core_init
351 /*
352 * After common core init has finished, check if the current thread is the
353 * one we wanted to boot. If not, start the specified thread and stop the
354 * current thread.
355 */
356 LOAD_REG_ADDR(r4, booting_thread_hwid)
357 lwz r3, 0(r4)
358 li r5, INVALID_THREAD_HWID
359 cmpw r3, r5
360 beq 20f
362 /*
363 * The value of booting_thread_hwid has been stored in r3,
364 * so make it invalid.
365 */
366 stw r5, 0(r4)
368 /*
369 * Get the current thread id and check if it is the one we wanted.
370 * If not, start the one specified in booting_thread_hwid and stop
371 * the current thread.
372 */
373 mfspr r8, SPRN_TIR
374 cmpw r3, r8
375 beq 20f
377 /* start the specified thread */
378 LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
379 ld r4, 0(r5)
380 bl book3e_start_thread
382 /* stop the current thread */
383 mr r3, r8
384 bl book3e_stop_thread
385 10:
386 b 10b
387 20:
388 #endif
390 generic_secondary_common_init:
391 /* Set up a paca value for this processor. Since we have the
392 * physical cpu id in r24, we need to search the pacas to find
393 * which logical id maps to our physical one.
394 */
395 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */
396 ld r13,0(r13) /* Get base vaddr of paca array */
397 #ifndef CONFIG_SMP
398 addi r13,r13,PACA_SIZE /* know r13 if used accidentally */
399 b kexec_wait /* wait for next kernel if !SMP */
400 #else
401 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
402 lwz r7,0(r7) /* also the max paca allocated */
403 li r5,0 /* logical cpu id */
404 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
405 cmpw r6,r24 /* Compare to our id */
406 beq 2f
407 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
408 addi r5,r5,1
409 cmpw r5,r7 /* Check if more pacas exist */
410 blt 1b
412 mr r3,r24 /* not found, copy phys to r3 */
413 b kexec_wait /* next kernel might do better */
415 2: SET_PACA(r13)
416 #ifdef CONFIG_PPC_BOOK3E
417 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
418 mtspr SPRN_SPRG_TLB_EXFRAME,r12
419 #endif
421 /* From now on, r24 is expected to be logical cpuid */
422 mr r24,r5
424 /* See if we need to call a cpu state restore handler */
425 LOAD_REG_ADDR(r23, cur_cpu_spec)
426 ld r23,0(r23)
427 ld r12,CPU_SPEC_RESTORE(r23)
428 cmpdi 0,r12,0
429 beq 3f
430 #ifdef PPC64_ELF_ABI_v1
431 ld r12,0(r12)
432 #endif
433 mtctr r12
434 bctrl
436 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
437 lwarx r4,0,r3
438 subi r4,r4,1
439 stwcx. r4,0,r3
440 bne 3b
441 isync
443 4: HMT_LOW
444 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
445 /* start. */
446 cmpwi 0,r23,0
447 beq 4b /* Loop until told to go */
449 sync /* order paca.run and cur_cpu_spec */
450 isync /* In case code patching happened */
452 /* Create a temp kernel stack for use before relocation is on. */
453 ld r1,PACAEMERGSP(r13)
454 subi r1,r1,STACK_FRAME_OVERHEAD
456 b __secondary_start
457 #endif /* SMP */
459 /*
460 * Turn the MMU off.
461 * Assumes we're mapped EA == RA if the MMU is on.
462 */
463 #ifdef CONFIG_PPC_BOOK3S
464 __mmu_off:
465 mfmsr r3
466 andi. r0,r3,MSR_IR|MSR_DR
467 beqlr
468 mflr r4
469 andc r3,r3,r0
470 mtspr SPRN_SRR0,r4
471 mtspr SPRN_SRR1,r3
472 sync
473 rfid
474 b . /* prevent speculative execution */
475 #endif
478 /*
479 * Here is our main kernel entry point. We support currently 2 kind of entries
480 * depending on the value of r5.
481 *
482 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
483 * in r3...r7
484 *
485 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
486 * DT block, r4 is a physical pointer to the kernel itself
487 *
488 */
489 __start_initialization_multiplatform:
490 /* Make sure we are running in 64 bits mode */
491 bl enable_64b_mode
493 /* Get TOC pointer (current runtime address) */
494 bl relative_toc
496 /* find out where we are now */
497 bcl 20,31,$+4
498 0: mflr r26 /* r26 = runtime addr here */
499 addis r26,r26,(_stext - 0b)@ha
500 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
502 /*
503 * Are we booted from a PROM Of-type client-interface ?
504 */
505 cmpldi cr0,r5,0
506 beq 1f
507 b __boot_from_prom /* yes -> prom */
508 1:
509 /* Save parameters */
510 mr r31,r3
511 mr r30,r4
512 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
513 /* Save OPAL entry */
514 mr r28,r8
515 mr r29,r9
516 #endif
518 #ifdef CONFIG_PPC_BOOK3E
519 bl start_initialization_book3e
520 b __after_prom_start
521 #else
522 /* Setup some critical 970 SPRs before switching MMU off */
523 mfspr r0,SPRN_PVR
524 srwi r0,r0,16
525 cmpwi r0,0x39 /* 970 */
526 beq 1f
527 cmpwi r0,0x3c /* 970FX */
528 beq 1f
529 cmpwi r0,0x44 /* 970MP */
530 beq 1f
531 cmpwi r0,0x45 /* 970GX */
532 bne 2f
533 1: bl __cpu_preinit_ppc970
534 2:
536 /* Switch off MMU if not already off */
537 bl __mmu_off
538 b __after_prom_start
539 #endif /* CONFIG_PPC_BOOK3E */
541 __boot_from_prom:
542 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
543 /* Save parameters */
544 mr r31,r3
545 mr r30,r4
546 mr r29,r5
547 mr r28,r6
548 mr r27,r7
550 /*
551 * Align the stack to 16-byte boundary
552 * Depending on the size and layout of the ELF sections in the initial
553 * boot binary, the stack pointer may be unaligned on PowerMac
554 */
555 rldicr r1,r1,0,59
557 #ifdef CONFIG_RELOCATABLE
558 /* Relocate code for where we are now */
559 mr r3,r26
560 bl relocate
561 #endif
563 /* Restore parameters */
564 mr r3,r31
565 mr r4,r30
566 mr r5,r29
567 mr r6,r28
568 mr r7,r27
570 /* Do all of the interaction with OF client interface */
571 mr r8,r26
572 bl prom_init
573 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
575 /* We never return. We also hit that trap if trying to boot
576 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
577 trap
579 __after_prom_start:
580 #ifdef CONFIG_RELOCATABLE
581 /* process relocations for the final address of the kernel */
582 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
583 sldi r25,r25,32
584 #if defined(CONFIG_PPC_BOOK3E)
585 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
586 #endif
587 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
588 #if defined(CONFIG_PPC_BOOK3E)
589 tophys(r26,r26)
590 #endif
591 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
592 bne 1f
593 add r25,r25,r26
594 1: mr r3,r25
595 bl relocate
596 #if defined(CONFIG_PPC_BOOK3E)
597 /* IVPR needs to be set after relocation. */
598 bl init_core_book3e
599 #endif
600 #endif
602 /*
603 * We need to run with _stext at physical address PHYSICAL_START.
604 * This will leave some code in the first 256B of
605 * real memory, which are reserved for software use.
606 *
607 * Note: This process overwrites the OF exception vectors.
608 */
609 li r3,0 /* target addr */
610 #ifdef CONFIG_PPC_BOOK3E
611 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
612 #endif
613 mr. r4,r26 /* In some cases the loader may */
614 #if defined(CONFIG_PPC_BOOK3E)
615 tovirt(r4,r4)
616 #endif
617 beq 9f /* have already put us at zero */
618 li r6,0x100 /* Start offset, the first 0x100 */
619 /* bytes were copied earlier. */
621 #ifdef CONFIG_RELOCATABLE
622 /*
623 * Check if the kernel has to be running as relocatable kernel based on the
624 * variable __run_at_load, if it is set the kernel is treated as relocatable
625 * kernel, otherwise it will be moved to PHYSICAL_START
626 */
627 #if defined(CONFIG_PPC_BOOK3E)
628 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
629 #endif
630 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
631 cmplwi cr0,r7,1
632 bne 3f
634 #ifdef CONFIG_PPC_BOOK3E
635 LOAD_REG_ADDR(r5, __end_interrupts)
636 LOAD_REG_ADDR(r11, _stext)
637 sub r5,r5,r11
638 #else
639 /* just copy interrupts */
640 LOAD_REG_IMMEDIATE(r5, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
641 #endif
642 b 5f
643 3:
644 #endif
645 /* # bytes of memory to copy */
646 lis r5,(ABS_ADDR(copy_to_here))@ha
647 addi r5,r5,(ABS_ADDR(copy_to_here))@l
649 bl copy_and_flush /* copy the first n bytes */
650 /* this includes the code being */
651 /* executed here. */
652 /* Jump to the copy of this code that we just made */
653 addis r8,r3,(ABS_ADDR(4f))@ha
654 addi r12,r8,(ABS_ADDR(4f))@l
655 mtctr r12
656 bctr
658 .balign 8
659 p_end: .8byte _end - copy_to_here
661 4:
662 /*
663 * Now copy the rest of the kernel up to _end, add
664 * _end - copy_to_here to the copy limit and run again.
665 */
666 addis r8,r26,(ABS_ADDR(p_end))@ha
667 ld r8,(ABS_ADDR(p_end))@l(r8)
668 add r5,r5,r8
669 5: bl copy_and_flush /* copy the rest */
671 9: b start_here_multiplatform
673 /*
674 * Copy routine used to copy the kernel to start at physical address 0
675 * and flush and invalidate the caches as needed.
676 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
677 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
678 *
679 * Note: this routine *only* clobbers r0, r6 and lr
680 */
681 _GLOBAL(copy_and_flush)
682 addi r5,r5,-8
683 addi r6,r6,-8
684 4: li r0,8 /* Use the smallest common */
685 /* denominator cache line */
686 /* size. This results in */
687 /* extra cache line flushes */
688 /* but operation is correct. */
689 /* Can't get cache line size */
690 /* from NACA as it is being */
691 /* moved too. */
693 mtctr r0 /* put # words/line in ctr */
694 3: addi r6,r6,8 /* copy a cache line */
695 ldx r0,r6,r4
696 stdx r0,r6,r3
697 bdnz 3b
698 dcbst r6,r3 /* write it to memory */
699 sync
700 icbi r6,r3 /* flush the icache line */
701 cmpld 0,r6,r5
702 blt 4b
703 sync
704 addi r5,r5,8
705 addi r6,r6,8
706 isync
707 blr
709 .align 8
710 copy_to_here:
712 #ifdef CONFIG_SMP
713 #ifdef CONFIG_PPC_PMAC
714 /*
715 * On PowerMac, secondary processors starts from the reset vector, which
716 * is temporarily turned into a call to one of the functions below.
717 */
718 .section ".text";
719 .align 2 ;
721 .globl __secondary_start_pmac_0
722 __secondary_start_pmac_0:
723 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
724 li r24,0
725 b 1f
726 li r24,1
727 b 1f
728 li r24,2
729 b 1f
730 li r24,3
731 1:
733 _GLOBAL(pmac_secondary_start)
734 /* turn on 64-bit mode */
735 bl enable_64b_mode
737 li r0,0
738 mfspr r3,SPRN_HID4
739 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
740 sync
741 mtspr SPRN_HID4,r3
742 isync
743 sync
744 slbia
746 /* get TOC pointer (real address) */
747 bl relative_toc
748 tovirt(r2,r2)
750 /* Copy some CPU settings from CPU 0 */
751 bl __restore_cpu_ppc970
753 /* pSeries do that early though I don't think we really need it */
754 mfmsr r3
755 ori r3,r3,MSR_RI
756 mtmsrd r3 /* RI on */
758 /* Set up a paca value for this processor. */
759 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */
760 ld r4,0(r4) /* Get base vaddr of paca array */
761 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
762 add r13,r13,r4 /* for this processor. */
763 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
765 /* Mark interrupts soft and hard disabled (they might be enabled
766 * in the PACA when doing hotplug)
767 */
768 li r0,IRQS_DISABLED
769 stb r0,PACAIRQSOFTMASK(r13)
770 li r0,PACA_IRQ_HARD_DIS
771 stb r0,PACAIRQHAPPENED(r13)
773 /* Create a temp kernel stack for use before relocation is on. */
774 ld r1,PACAEMERGSP(r13)
775 subi r1,r1,STACK_FRAME_OVERHEAD
777 b __secondary_start
779 #endif /* CONFIG_PPC_PMAC */
781 /*
782 * This function is called after the master CPU has released the
783 * secondary processors. The execution environment is relocation off.
784 * The paca for this processor has the following fields initialized at
785 * this point:
786 * 1. Processor number
787 * 2. Segment table pointer (virtual address)
788 * On entry the following are set:
789 * r1 = stack pointer (real addr of temp stack)
790 * r24 = cpu# (in Linux terms)
791 * r13 = paca virtual address
792 * SPRG_PACA = paca virtual address
793 */
794 .section ".text";
795 .align 2 ;
797 .globl __secondary_start
798 __secondary_start:
799 /* Set thread priority to MEDIUM */
800 HMT_MEDIUM
802 /* Initialize the kernel stack */
803 LOAD_REG_ADDR(r3, current_set)
804 sldi r28,r24,3 /* get current_set[cpu#] */
805 ldx r14,r3,r28
806 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD
807 std r14,PACAKSAVE(r13)
809 /* Do early setup for that CPU (SLB and hash table pointer) */
810 bl early_setup_secondary
812 /*
813 * setup the new stack pointer, but *don't* use this until
814 * translation is on.
815 */
816 mr r1, r14
818 /* Clear backchain so we get nice backtraces */
819 li r7,0
820 mtlr r7
822 /* Mark interrupts soft and hard disabled (they might be enabled
823 * in the PACA when doing hotplug)
824 */
825 li r7,IRQS_DISABLED
826 stb r7,PACAIRQSOFTMASK(r13)
827 li r0,PACA_IRQ_HARD_DIS
828 stb r0,PACAIRQHAPPENED(r13)
830 /* enable MMU and jump to start_secondary */
831 LOAD_REG_ADDR(r3, start_secondary_prolog)
832 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
834 mtspr SPRN_SRR0,r3
835 mtspr SPRN_SRR1,r4
836 RFI
837 b . /* prevent speculative execution */
839 /*
840 * Running with relocation on at this point. All we want to do is
841 * zero the stack back-chain pointer and get the TOC virtual address
842 * before going into C code.
843 */
844 start_secondary_prolog:
845 ld r2,PACATOC(r13)
846 li r3,0
847 std r3,0(r1) /* Zero the stack frame pointer */
848 bl start_secondary
849 b .
850 /*
851 * Reset stack pointer and call start_secondary
852 * to continue with online operation when woken up
853 * from cede in cpu offline.
854 */
855 _GLOBAL(start_secondary_resume)
856 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
857 li r3,0
858 std r3,0(r1) /* Zero the stack frame pointer */
859 bl start_secondary
860 b .
861 #endif
863 /*
864 * This subroutine clobbers r11 and r12
865 */
866 enable_64b_mode:
867 mfmsr r11 /* grab the current MSR */
868 #ifdef CONFIG_PPC_BOOK3E
869 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
870 mtmsr r11
871 #else /* CONFIG_PPC_BOOK3E */
872 li r12,(MSR_64BIT | MSR_ISF)@highest
873 sldi r12,r12,48
874 or r11,r11,r12
875 mtmsrd r11
876 isync
877 #endif
878 blr
880 /*
881 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
882 * by the toolchain). It computes the correct value for wherever we
883 * are running at the moment, using position-independent code.
884 *
885 * Note: The compiler constructs pointers using offsets from the
886 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
887 * the MMU is on we need our TOC to be a virtual address otherwise
888 * these pointers will be real addresses which may get stored and
889 * accessed later with the MMU on. We use tovirt() at the call
890 * sites to handle this.
891 */
892 _GLOBAL(relative_toc)
893 mflr r0
894 bcl 20,31,$+4
895 0: mflr r11
896 ld r2,(p_toc - 0b)(r11)
897 add r2,r2,r11
898 mtlr r0
899 blr
901 .balign 8
902 p_toc: .8byte __toc_start + 0x8000 - 0b
904 /*
905 * This is where the main kernel code starts.
906 */
907 start_here_multiplatform:
908 /* set up the TOC */
909 bl relative_toc
910 tovirt(r2,r2)
912 /* Clear out the BSS. It may have been done in prom_init,
913 * already but that's irrelevant since prom_init will soon
914 * be detached from the kernel completely. Besides, we need
915 * to clear it now for kexec-style entry.
916 */
917 LOAD_REG_ADDR(r11,__bss_stop)
918 LOAD_REG_ADDR(r8,__bss_start)
919 sub r11,r11,r8 /* bss size */
920 addi r11,r11,7 /* round up to an even double word */
921 srdi. r11,r11,3 /* shift right by 3 */
922 beq 4f
923 addi r8,r8,-8
924 li r0,0
925 mtctr r11 /* zero this many doublewords */
926 3: stdu r0,8(r8)
927 bdnz 3b
928 4:
930 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
931 /* Setup OPAL entry */
932 LOAD_REG_ADDR(r11, opal)
933 std r28,0(r11);
934 std r29,8(r11);
935 #endif
937 #ifndef CONFIG_PPC_BOOK3E
938 mfmsr r6
939 ori r6,r6,MSR_RI
940 mtmsrd r6 /* RI on */
941 #endif
943 #ifdef CONFIG_RELOCATABLE
944 /* Save the physical address we're running at in kernstart_addr */
945 LOAD_REG_ADDR(r4, kernstart_addr)
946 clrldi r0,r25,2
947 std r0,0(r4)
948 #endif
950 /* The following gets the stack set up with the regs */
951 /* pointing to the real addr of the kernel stack. This is */
952 /* all done to support the C function call below which sets */
953 /* up the htab. This is done because we have relocated the */
954 /* kernel but are still running in real mode. */
956 LOAD_REG_ADDR(r3,init_thread_union)
958 /* set up a stack pointer */
959 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
960 add r1,r3,r1
961 li r0,0
962 stdu r0,-STACK_FRAME_OVERHEAD(r1)
964 /*
965 * Do very early kernel initializations, including initial hash table
966 * and SLB setup before we turn on relocation.
967 */
969 /* Restore parameters passed from prom_init/kexec */
970 mr r3,r31
971 bl early_setup /* also sets r13 and SPRG_PACA */
973 LOAD_REG_ADDR(r3, start_here_common)
974 ld r4,PACAKMSR(r13)
975 mtspr SPRN_SRR0,r3
976 mtspr SPRN_SRR1,r4
977 RFI
978 b . /* prevent speculative execution */
980 /* This is where all platforms converge execution */
982 start_here_common:
983 /* relocation is on at this point */
984 std r1,PACAKSAVE(r13)
986 /* Load the TOC (virtual address) */
987 ld r2,PACATOC(r13)
989 /* Mark interrupts soft and hard disabled (they might be enabled
990 * in the PACA when doing hotplug)
991 */
992 li r0,IRQS_DISABLED
993 stb r0,PACAIRQSOFTMASK(r13)
994 li r0,PACA_IRQ_HARD_DIS
995 stb r0,PACAIRQHAPPENED(r13)
997 /* Generic kernel entry */
998 bl start_kernel
1000 /* Not reached */
1001 BUG_OPCODE
1003 /*
1004 * We put a few things here that have to be page-aligned.
1005 * This stuff goes at the beginning of the bss, which is page-aligned.
1006 */
1007 .section ".bss"
1008 /*
1009 * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K.
1010 * We will need to find a better way to fix this
1011 */
1012 .align 16
1014 .globl swapper_pg_dir
1015 swapper_pg_dir:
1016 .space PGD_TABLE_SIZE
1018 .globl empty_zero_page
1019 empty_zero_page:
1020 .space PAGE_SIZE
1021 EXPORT_SYMBOL(empty_zero_page)