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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / arch / powerpc / platforms / 4xx / pci.c
blob73e6b36bcd5125724a0c913d745e1a4bab9b1133
1 /*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
17 */
18
19 #undef DEBUG
20
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/of.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27
28 #include <asm/io.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
31 #include <asm/dcr.h>
32 #include <asm/dcr-regs.h>
33 #include <mm/mmu_decl.h>
34
35 #include "pci.h"
36
37 static int dma_offset_set;
38
39 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
40 #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
41
42 #define RES_TO_U32_LOW(val) \
43 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
44 #define RES_TO_U32_HIGH(val) \
45 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
46
47 static inline int ppc440spe_revA(void)
48 {
49 /* Catch both 440SPe variants, with and without RAID6 support */
50 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
51 return 1;
52 else
53 return 0;
54 }
55
56 static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
57 {
58 struct pci_controller *hose;
59 int i;
60
61 if (dev->devfn != 0 || dev->bus->self != NULL)
62 return;
63
64 hose = pci_bus_to_host(dev->bus);
65 if (hose == NULL)
66 return;
67
68 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
69 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
70 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
71 return;
72
73 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
74 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
75 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
76 }
77
78 /* Hide the PCI host BARs from the kernel as their content doesn't
79 * fit well in the resource management
80 */
81 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
82 dev->resource[i].start = dev->resource[i].end = 0;
83 dev->resource[i].flags = 0;
84 }
85
86 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
87 pci_name(dev));
88 }
89 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
90
91 static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
92 void __iomem *reg,
93 struct resource *res)
94 {
95 u64 size;
96 const u32 *ranges;
97 int rlen;
98 int pna = of_n_addr_cells(hose->dn);
99 int np = pna + 5;
100
101 /* Default */
102 res->start = 0;
103 size = 0x80000000;
104 res->end = size - 1;
105 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
106
107 /* Get dma-ranges property */
108 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
109 if (ranges == NULL)
110 goto out;
111
112 /* Walk it */
113 while ((rlen -= np * 4) >= 0) {
114 u32 pci_space = ranges[0];
115 u64 pci_addr = of_read_number(ranges + 1, 2);
116 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
117 size = of_read_number(ranges + pna + 3, 2);
118 ranges += np;
119 if (cpu_addr == OF_BAD_ADDR || size == 0)
120 continue;
121
122 /* We only care about memory */
123 if ((pci_space & 0x03000000) != 0x02000000)
124 continue;
125
126 /* We currently only support memory at 0, and pci_addr
127 * within 32 bits space
128 */
129 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
130 printk(KERN_WARNING "%pOF: Ignored unsupported dma range"
131 " 0x%016llx...0x%016llx -> 0x%016llx\n",
132 hose->dn,
133 pci_addr, pci_addr + size - 1, cpu_addr);
134 continue;
135 }
136
137 /* Check if not prefetchable */
138 if (!(pci_space & 0x40000000))
139 res->flags &= ~IORESOURCE_PREFETCH;
140
141
142 /* Use that */
143 res->start = pci_addr;
144 /* Beware of 32 bits resources */
145 if (sizeof(resource_size_t) == sizeof(u32) &&
146 (pci_addr + size) > 0x100000000ull)
147 res->end = 0xffffffff;
148 else
149 res->end = res->start + size - 1;
150 break;
151 }
152
153 /* We only support one global DMA offset */
154 if (dma_offset_set && pci_dram_offset != res->start) {
155 printk(KERN_ERR "%pOF: dma-ranges(s) mismatch\n", hose->dn);
156 return -ENXIO;
157 }
158
159 /* Check that we can fit all of memory as we don't support
160 * DMA bounce buffers
161 */
162 if (size < total_memory) {
163 printk(KERN_ERR "%pOF: dma-ranges too small "
164 "(size=%llx total_memory=%llx)\n",
165 hose->dn, size, (u64)total_memory);
166 return -ENXIO;
167 }
168
169 /* Check we are a power of 2 size and that base is a multiple of size*/
170 if ((size & (size - 1)) != 0 ||
171 (res->start & (size - 1)) != 0) {
172 printk(KERN_ERR "%pOF: dma-ranges unaligned\n", hose->dn);
173 return -ENXIO;
174 }
175
176 /* Check that we are fully contained within 32 bits space if we are not
177 * running on a 460sx or 476fpe which have 64 bit bus addresses.
178 */
179 if (res->end > 0xffffffff &&
180 !(of_device_is_compatible(hose->dn, "ibm,plb-pciex-460sx")
181 || of_device_is_compatible(hose->dn, "ibm,plb-pciex-476fpe"))) {
182 printk(KERN_ERR "%pOF: dma-ranges outside of 32 bits space\n",
183 hose->dn);
184 return -ENXIO;
185 }
186 out:
187 dma_offset_set = 1;
188 pci_dram_offset = res->start;
189 hose->dma_window_base_cur = res->start;
190 hose->dma_window_size = resource_size(res);
191
192 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
193 pci_dram_offset);
194 printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n",
195 (unsigned long long)hose->dma_window_base_cur);
196 printk(KERN_INFO "DMA window size 0x%016llx\n",
197 (unsigned long long)hose->dma_window_size);
198 return 0;
199 }
200
201 /*
202 * 4xx PCI 2.x part
203 */
204
205 static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose,
206 void __iomem *reg,
207 u64 plb_addr,
208 u64 pci_addr,
209 u64 size,
210 unsigned int flags,
211 int index)
212 {
213 u32 ma, pcila, pciha;
214
215 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
216 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
217 * address are actually hard wired to a value that appears to depend
218 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
219 *
220 * The trick here is we just crop those top bits and ignore them when
221 * programming the chip. That means the device-tree has to be right
222 * for the specific part used (we don't print a warning if it's wrong
223 * but on the other hand, you'll crash quickly enough), but at least
224 * this code should work whatever the hard coded value is
225 */
226 plb_addr &= 0xffffffffull;
227
228 /* Note: Due to the above hack, the test below doesn't actually test
229 * if you address is above 4G, but it tests that address and
230 * (address + size) are both contained in the same 4G
231 */
232 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
233 size < 0x1000 || (plb_addr & (size - 1)) != 0) {
234 printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn);
235 return -1;
236 }
237 ma = (0xffffffffu << ilog2(size)) | 1;
238 if (flags & IORESOURCE_PREFETCH)
239 ma |= 2;
240
241 pciha = RES_TO_U32_HIGH(pci_addr);
242 pcila = RES_TO_U32_LOW(pci_addr);
243
244 writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index));
245 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index));
246 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index));
247 writel(ma, reg + PCIL0_PMM0MA + (0x10 * index));
248
249 return 0;
250 }
251
252 static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
253 void __iomem *reg)
254 {
255 int i, j, found_isa_hole = 0;
256
257 /* Setup outbound memory windows */
258 for (i = j = 0; i < 3; i++) {
259 struct resource *res = &hose->mem_resources[i];
260 resource_size_t offset = hose->mem_offset[i];
261
262 /* we only care about memory windows */
263 if (!(res->flags & IORESOURCE_MEM))
264 continue;
265 if (j > 2) {
266 printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn);
267 break;
268 }
269
270 /* Configure the resource */
271 if (ppc4xx_setup_one_pci_PMM(hose, reg,
272 res->start,
273 res->start - offset,
274 resource_size(res),
275 res->flags,
276 j) == 0) {
277 j++;
278
279 /* If the resource PCI address is 0 then we have our
280 * ISA memory hole
281 */
282 if (res->start == offset)
283 found_isa_hole = 1;
284 }
285 }
286
287 /* Handle ISA memory hole if not already covered */
288 if (j <= 2 && !found_isa_hole && hose->isa_mem_size)
289 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0,
290 hose->isa_mem_size, 0, j) == 0)
291 printk(KERN_INFO "%pOF: Legacy ISA memory support enabled\n",
292 hose->dn);
293 }
294
295 static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
296 void __iomem *reg,
297 const struct resource *res)
298 {
299 resource_size_t size = resource_size(res);
300 u32 sa;
301
302 /* Calculate window size */
303 sa = (0xffffffffu << ilog2(size)) | 1;
304 sa |= 0x1;
305
306 /* RAM is always at 0 local for now */
307 writel(0, reg + PCIL0_PTM1LA);
308 writel(sa, reg + PCIL0_PTM1MS);
309
310 /* Map on PCI side */
311 early_write_config_dword(hose, hose->first_busno, 0,
312 PCI_BASE_ADDRESS_1, res->start);
313 early_write_config_dword(hose, hose->first_busno, 0,
314 PCI_BASE_ADDRESS_2, 0x00000000);
315 early_write_config_word(hose, hose->first_busno, 0,
316 PCI_COMMAND, 0x0006);
317 }
318
319 static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
320 {
321 /* NYI */
322 struct resource rsrc_cfg;
323 struct resource rsrc_reg;
324 struct resource dma_window;
325 struct pci_controller *hose = NULL;
326 void __iomem *reg = NULL;
327 const int *bus_range;
328 int primary = 0;
329
330 /* Check if device is enabled */
331 if (!of_device_is_available(np)) {
332 printk(KERN_INFO "%pOF: Port disabled via device-tree\n", np);
333 return;
334 }
335
336 /* Fetch config space registers address */
337 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
338 printk(KERN_ERR "%pOF: Can't get PCI config register base !",
339 np);
340 return;
341 }
342 /* Fetch host bridge internal registers address */
343 if (of_address_to_resource(np, 3, &rsrc_reg)) {
344 printk(KERN_ERR "%pOF: Can't get PCI internal register base !",
345 np);
346 return;
347 }
348
349 /* Check if primary bridge */
350 if (of_get_property(np, "primary", NULL))
351 primary = 1;
352
353 /* Get bus range if any */
354 bus_range = of_get_property(np, "bus-range", NULL);
355
356 /* Map registers */
357 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
358 if (reg == NULL) {
359 printk(KERN_ERR "%pOF: Can't map registers !", np);
360 goto fail;
361 }
362
363 /* Allocate the host controller data structure */
364 hose = pcibios_alloc_controller(np);
365 if (!hose)
366 goto fail;
367
368 hose->first_busno = bus_range ? bus_range[0] : 0x0;
369 hose->last_busno = bus_range ? bus_range[1] : 0xff;
370
371 /* Setup config space */
372 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
373
374 /* Disable all windows */
375 writel(0, reg + PCIL0_PMM0MA);
376 writel(0, reg + PCIL0_PMM1MA);
377 writel(0, reg + PCIL0_PMM2MA);
378 writel(0, reg + PCIL0_PTM1MS);
379 writel(0, reg + PCIL0_PTM2MS);
380
381 /* Parse outbound mapping resources */
382 pci_process_bridge_OF_ranges(hose, np, primary);
383
384 /* Parse inbound mapping resources */
385 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
386 goto fail;
387
388 /* Configure outbound ranges POMs */
389 ppc4xx_configure_pci_PMMs(hose, reg);
390
391 /* Configure inbound ranges PIMs */
392 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
393
394 /* We don't need the registers anymore */
395 iounmap(reg);
396 return;
397
398 fail:
399 if (hose)
400 pcibios_free_controller(hose);
401 if (reg)
402 iounmap(reg);
403 }
404
405 /*
406 * 4xx PCI-X part
407 */
408
409 static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose,
410 void __iomem *reg,
411 u64 plb_addr,
412 u64 pci_addr,
413 u64 size,
414 unsigned int flags,
415 int index)
416 {
417 u32 lah, lal, pciah, pcial, sa;
418
419 if (!is_power_of_2(size) || size < 0x1000 ||
420 (plb_addr & (size - 1)) != 0) {
421 printk(KERN_WARNING "%pOF: Resource out of range\n",
422 hose->dn);
423 return -1;
424 }
425
426 /* Calculate register values */
427 lah = RES_TO_U32_HIGH(plb_addr);
428 lal = RES_TO_U32_LOW(plb_addr);
429 pciah = RES_TO_U32_HIGH(pci_addr);
430 pcial = RES_TO_U32_LOW(pci_addr);
431 sa = (0xffffffffu << ilog2(size)) | 0x1;
432
433 /* Program register values */
434 if (index == 0) {
435 writel(lah, reg + PCIX0_POM0LAH);
436 writel(lal, reg + PCIX0_POM0LAL);
437 writel(pciah, reg + PCIX0_POM0PCIAH);
438 writel(pcial, reg + PCIX0_POM0PCIAL);
439 writel(sa, reg + PCIX0_POM0SA);
440 } else {
441 writel(lah, reg + PCIX0_POM1LAH);
442 writel(lal, reg + PCIX0_POM1LAL);
443 writel(pciah, reg + PCIX0_POM1PCIAH);
444 writel(pcial, reg + PCIX0_POM1PCIAL);
445 writel(sa, reg + PCIX0_POM1SA);
446 }
447
448 return 0;
449 }
450
451 static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
452 void __iomem *reg)
453 {
454 int i, j, found_isa_hole = 0;
455
456 /* Setup outbound memory windows */
457 for (i = j = 0; i < 3; i++) {
458 struct resource *res = &hose->mem_resources[i];
459 resource_size_t offset = hose->mem_offset[i];
460
461 /* we only care about memory windows */
462 if (!(res->flags & IORESOURCE_MEM))
463 continue;
464 if (j > 1) {
465 printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn);
466 break;
467 }
468
469 /* Configure the resource */
470 if (ppc4xx_setup_one_pcix_POM(hose, reg,
471 res->start,
472 res->start - offset,
473 resource_size(res),
474 res->flags,
475 j) == 0) {
476 j++;
477
478 /* If the resource PCI address is 0 then we have our
479 * ISA memory hole
480 */
481 if (res->start == offset)
482 found_isa_hole = 1;
483 }
484 }
485
486 /* Handle ISA memory hole if not already covered */
487 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
488 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0,
489 hose->isa_mem_size, 0, j) == 0)
490 printk(KERN_INFO "%pOF: Legacy ISA memory support enabled\n",
491 hose->dn);
492 }
493
494 static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
495 void __iomem *reg,
496 const struct resource *res,
497 int big_pim,
498 int enable_msi_hole)
499 {
500 resource_size_t size = resource_size(res);
501 u32 sa;
502
503 /* RAM is always at 0 */
504 writel(0x00000000, reg + PCIX0_PIM0LAH);
505 writel(0x00000000, reg + PCIX0_PIM0LAL);
506
507 /* Calculate window size */
508 sa = (0xffffffffu << ilog2(size)) | 1;
509 sa |= 0x1;
510 if (res->flags & IORESOURCE_PREFETCH)
511 sa |= 0x2;
512 if (enable_msi_hole)
513 sa |= 0x4;
514 writel(sa, reg + PCIX0_PIM0SA);
515 if (big_pim)
516 writel(0xffffffff, reg + PCIX0_PIM0SAH);
517
518 /* Map on PCI side */
519 writel(0x00000000, reg + PCIX0_BAR0H);
520 writel(res->start, reg + PCIX0_BAR0L);
521 writew(0x0006, reg + PCIX0_COMMAND);
522 }
523
524 static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
525 {
526 struct resource rsrc_cfg;
527 struct resource rsrc_reg;
528 struct resource dma_window;
529 struct pci_controller *hose = NULL;
530 void __iomem *reg = NULL;
531 const int *bus_range;
532 int big_pim = 0, msi = 0, primary = 0;
533
534 /* Fetch config space registers address */
535 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
536 printk(KERN_ERR "%pOF: Can't get PCI-X config register base !",
537 np);
538 return;
539 }
540 /* Fetch host bridge internal registers address */
541 if (of_address_to_resource(np, 3, &rsrc_reg)) {
542 printk(KERN_ERR "%pOF: Can't get PCI-X internal register base !",
543 np);
544 return;
545 }
546
547 /* Check if it supports large PIMs (440GX) */
548 if (of_get_property(np, "large-inbound-windows", NULL))
549 big_pim = 1;
550
551 /* Check if we should enable MSIs inbound hole */
552 if (of_get_property(np, "enable-msi-hole", NULL))
553 msi = 1;
554
555 /* Check if primary bridge */
556 if (of_get_property(np, "primary", NULL))
557 primary = 1;
558
559 /* Get bus range if any */
560 bus_range = of_get_property(np, "bus-range", NULL);
561
562 /* Map registers */
563 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
564 if (reg == NULL) {
565 printk(KERN_ERR "%pOF: Can't map registers !", np);
566 goto fail;
567 }
568
569 /* Allocate the host controller data structure */
570 hose = pcibios_alloc_controller(np);
571 if (!hose)
572 goto fail;
573
574 hose->first_busno = bus_range ? bus_range[0] : 0x0;
575 hose->last_busno = bus_range ? bus_range[1] : 0xff;
576
577 /* Setup config space */
578 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4,
579 PPC_INDIRECT_TYPE_SET_CFG_TYPE);
580
581 /* Disable all windows */
582 writel(0, reg + PCIX0_POM0SA);
583 writel(0, reg + PCIX0_POM1SA);
584 writel(0, reg + PCIX0_POM2SA);
585 writel(0, reg + PCIX0_PIM0SA);
586 writel(0, reg + PCIX0_PIM1SA);
587 writel(0, reg + PCIX0_PIM2SA);
588 if (big_pim) {
589 writel(0, reg + PCIX0_PIM0SAH);
590 writel(0, reg + PCIX0_PIM2SAH);
591 }
592
593 /* Parse outbound mapping resources */
594 pci_process_bridge_OF_ranges(hose, np, primary);
595
596 /* Parse inbound mapping resources */
597 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
598 goto fail;
599
600 /* Configure outbound ranges POMs */
601 ppc4xx_configure_pcix_POMs(hose, reg);
602
603 /* Configure inbound ranges PIMs */
604 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
605
606 /* We don't need the registers anymore */
607 iounmap(reg);
608 return;
609
610 fail:
611 if (hose)
612 pcibios_free_controller(hose);
613 if (reg)
614 iounmap(reg);
615 }
616
617 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
618
619 /*
620 * 4xx PCI-Express part
621 *
622 * We support 3 parts currently based on the compatible property:
623 *
624 * ibm,plb-pciex-440spe
625 * ibm,plb-pciex-405ex
626 * ibm,plb-pciex-460ex
627 *
628 * Anything else will be rejected for now as they are all subtly
629 * different unfortunately.
630 *
631 */
632
633 #define MAX_PCIE_BUS_MAPPED 0x40
634
635 struct ppc4xx_pciex_port
636 {
637 struct pci_controller *hose;
638 struct device_node *node;
639 unsigned int index;
640 int endpoint;
641 int link;
642 int has_ibpre;
643 unsigned int sdr_base;
644 dcr_host_t dcrs;
645 struct resource cfg_space;
646 struct resource utl_regs;
647 void __iomem *utl_base;
648 };
649
650 static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
651 static unsigned int ppc4xx_pciex_port_count;
652
653 struct ppc4xx_pciex_hwops
654 {
655 bool want_sdr;
656 int (*core_init)(struct device_node *np);
657 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
658 int (*setup_utl)(struct ppc4xx_pciex_port *port);
659 void (*check_link)(struct ppc4xx_pciex_port *port);
660 };
661
662 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
663
664 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
665 unsigned int sdr_offset,
666 unsigned int mask,
667 unsigned int value,
668 int timeout_ms)
669 {
670 u32 val;
671
672 while(timeout_ms--) {
673 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
674 if ((val & mask) == value) {
675 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
676 port->index, sdr_offset, timeout_ms, val);
677 return 0;
678 }
679 msleep(1);
680 }
681 return -1;
682 }
683
684 static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
685 {
686 /* Wait for reset to complete */
687 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
688 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
689 port->index);
690 return -1;
691 }
692 return 0;
693 }
694
695
696 static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
697 {
698 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
699
700 /* Check for card presence detect if supported, if not, just wait for
701 * link unconditionally.
702 *
703 * note that we don't fail if there is no link, we just filter out
704 * config space accesses. That way, it will be easier to implement
705 * hotplug later on.
706 */
707 if (!port->has_ibpre ||
708 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
709 1 << 28, 1 << 28, 100)) {
710 printk(KERN_INFO
711 "PCIE%d: Device detected, waiting for link...\n",
712 port->index);
713 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
714 0x1000, 0x1000, 2000))
715 printk(KERN_WARNING
716 "PCIE%d: Link up failed\n", port->index);
717 else {
718 printk(KERN_INFO
719 "PCIE%d: link is up !\n", port->index);
720 port->link = 1;
721 }
722 } else
723 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
724 }
725
726 #ifdef CONFIG_44x
727
728 /* Check various reset bits of the 440SPe PCIe core */
729 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
730 {
731 u32 valPE0, valPE1, valPE2;
732 int err = 0;
733
734 /* SDR0_PEGPLLLCT1 reset */
735 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
736 /*
737 * the PCIe core was probably already initialised
738 * by firmware - let's re-reset RCSSET regs
739 *
740 * -- Shouldn't we also re-reset the whole thing ? -- BenH
741 */
742 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
743 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
744 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
745 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
746 }
747
748 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
749 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
750 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
751
752 /* SDR0_PExRCSSET rstgu */
753 if (!(valPE0 & 0x01000000) ||
754 !(valPE1 & 0x01000000) ||
755 !(valPE2 & 0x01000000)) {
756 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
757 err = -1;
758 }
759
760 /* SDR0_PExRCSSET rstdl */
761 if (!(valPE0 & 0x00010000) ||
762 !(valPE1 & 0x00010000) ||
763 !(valPE2 & 0x00010000)) {
764 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
765 err = -1;
766 }
767
768 /* SDR0_PExRCSSET rstpyn */
769 if ((valPE0 & 0x00001000) ||
770 (valPE1 & 0x00001000) ||
771 (valPE2 & 0x00001000)) {
772 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
773 err = -1;
774 }
775
776 /* SDR0_PExRCSSET hldplb */
777 if ((valPE0 & 0x10000000) ||
778 (valPE1 & 0x10000000) ||
779 (valPE2 & 0x10000000)) {
780 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
781 err = -1;
782 }
783
784 /* SDR0_PExRCSSET rdy */
785 if ((valPE0 & 0x00100000) ||
786 (valPE1 & 0x00100000) ||
787 (valPE2 & 0x00100000)) {
788 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
789 err = -1;
790 }
791
792 /* SDR0_PExRCSSET shutdown */
793 if ((valPE0 & 0x00000100) ||
794 (valPE1 & 0x00000100) ||
795 (valPE2 & 0x00000100)) {
796 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
797 err = -1;
798 }
799
800 return err;
801 }
802
803 /* Global PCIe core initializations for 440SPe core */
804 static int __init ppc440spe_pciex_core_init(struct device_node *np)
805 {
806 int time_out = 20;
807
808 /* Set PLL clock receiver to LVPECL */
809 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
810
811 /* Shouldn't we do all the calibration stuff etc... here ? */
812 if (ppc440spe_pciex_check_reset(np))
813 return -ENXIO;
814
815 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
816 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
817 "failed (0x%08x)\n",
818 mfdcri(SDR0, PESDR0_PLLLCT2));
819 return -1;
820 }
821
822 /* De-assert reset of PCIe PLL, wait for lock */
823 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
824 udelay(3);
825
826 while (time_out) {
827 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
828 time_out--;
829 udelay(1);
830 } else
831 break;
832 }
833 if (!time_out) {
834 printk(KERN_INFO "PCIE: VCO output not locked\n");
835 return -1;
836 }
837
838 pr_debug("PCIE initialization OK\n");
839
840 return 3;
841 }
842
843 static int __init ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
844 {
845 u32 val = 1 << 24;
846
847 if (port->endpoint)
848 val = PTYPE_LEGACY_ENDPOINT << 20;
849 else
850 val = PTYPE_ROOT_PORT << 20;
851
852 if (port->index == 0)
853 val |= LNKW_X8 << 12;
854 else
855 val |= LNKW_X4 << 12;
856
857 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
858 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
859 if (ppc440spe_revA())
860 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
861 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
863 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
865 if (port->index == 0) {
866 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
867 0x35000000);
868 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
869 0x35000000);
870 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
871 0x35000000);
872 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
873 0x35000000);
874 }
875 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
876 (1 << 24) | (1 << 16), 1 << 12);
877
878 return ppc4xx_pciex_port_reset_sdr(port);
879 }
880
881 static int __init ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
882 {
883 return ppc440spe_pciex_init_port_hw(port);
884 }
885
886 static int __init ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
887 {
888 int rc = ppc440spe_pciex_init_port_hw(port);
889
890 port->has_ibpre = 1;
891
892 return rc;
893 }
894
895 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
896 {
897 /* XXX Check what that value means... I hate magic */
898 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
899
900 /*
901 * Set buffer allocations and then assert VRB and TXE.
902 */
903 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
904 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
905 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
906 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
907 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
908 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
909 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
910 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
911
912 return 0;
913 }
914
915 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
916 {
917 /* Report CRS to the operating system */
918 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
919
920 return 0;
921 }
922
923 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
924 {
925 .want_sdr = true,
926 .core_init = ppc440spe_pciex_core_init,
927 .port_init_hw = ppc440speA_pciex_init_port_hw,
928 .setup_utl = ppc440speA_pciex_init_utl,
929 .check_link = ppc4xx_pciex_check_link_sdr,
930 };
931
932 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
933 {
934 .want_sdr = true,
935 .core_init = ppc440spe_pciex_core_init,
936 .port_init_hw = ppc440speB_pciex_init_port_hw,
937 .setup_utl = ppc440speB_pciex_init_utl,
938 .check_link = ppc4xx_pciex_check_link_sdr,
939 };
940
941 static int __init ppc460ex_pciex_core_init(struct device_node *np)
942 {
943 /* Nothing to do, return 2 ports */
944 return 2;
945 }
946
947 static int __init ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
948 {
949 u32 val;
950 u32 utlset1;
951
952 if (port->endpoint)
953 val = PTYPE_LEGACY_ENDPOINT << 20;
954 else
955 val = PTYPE_ROOT_PORT << 20;
956
957 if (port->index == 0) {
958 val |= LNKW_X1 << 12;
959 utlset1 = 0x20000000;
960 } else {
961 val |= LNKW_X4 << 12;
962 utlset1 = 0x20101101;
963 }
964
965 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
966 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
967 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
968
969 switch (port->index) {
970 case 0:
971 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
972 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
973 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
974
975 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
976 break;
977
978 case 1:
979 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
980 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
981 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
982 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
983 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
984 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
985 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
986 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
987 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
988 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
989 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
990 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
991
992 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
993 break;
994 }
995
996 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
997 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
998 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
999
1000 /* Poll for PHY reset */
1001 /* XXX FIXME add timeout */
1002 switch (port->index) {
1003 case 0:
1004 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
1005 udelay(10);
1006 break;
1007 case 1:
1008 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
1009 udelay(10);
1010 break;
1011 }
1012
1013 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1014 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1015 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
1016 PESDRx_RCSSET_RSTPYN);
1017
1018 port->has_ibpre = 1;
1019
1020 return ppc4xx_pciex_port_reset_sdr(port);
1021 }
1022
1023 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1024 {
1025 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1026
1027 /*
1028 * Set buffer allocations and then assert VRB and TXE.
1029 */
1030 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
1031 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
1032 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1033 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1034 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
1035 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1036 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1037 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
1038 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1039
1040 return 0;
1041 }
1042
1043 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
1044 {
1045 .want_sdr = true,
1046 .core_init = ppc460ex_pciex_core_init,
1047 .port_init_hw = ppc460ex_pciex_init_port_hw,
1048 .setup_utl = ppc460ex_pciex_init_utl,
1049 .check_link = ppc4xx_pciex_check_link_sdr,
1050 };
1051
1052 static int __init apm821xx_pciex_core_init(struct device_node *np)
1053 {
1054 /* Return the number of pcie port */
1055 return 1;
1056 }
1057
1058 static int __init apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1059 {
1060 u32 val;
1061
1062 /*
1063 * Do a software reset on PCIe ports.
1064 * This code is to fix the issue that pci drivers doesn't re-assign
1065 * bus number for PCIE devices after Uboot
1066 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
1067 * PT quad port, SAS LSI 1064E)
1068 */
1069
1070 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
1071 mdelay(10);
1072
1073 if (port->endpoint)
1074 val = PTYPE_LEGACY_ENDPOINT << 20;
1075 else
1076 val = PTYPE_ROOT_PORT << 20;
1077
1078 val |= LNKW_X1 << 12;
1079
1080 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
1081 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1082 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1083
1084 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
1085 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
1086 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
1087
1088 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
1089 mdelay(50);
1090 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
1091
1092 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1093 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
1094 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
1095
1096 /* Poll for PHY reset */
1097 val = PESDR0_460EX_RSTSTA - port->sdr_base;
1098 if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) {
1099 printk(KERN_WARNING "%s: PCIE: Can't reset PHY\n", __func__);
1100 return -EBUSY;
1101 } else {
1102 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1103 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1104 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
1105 PESDRx_RCSSET_RSTPYN);
1106
1107 port->has_ibpre = 1;
1108 return 0;
1109 }
1110 }
1111
1112 static struct ppc4xx_pciex_hwops apm821xx_pcie_hwops __initdata = {
1113 .want_sdr = true,
1114 .core_init = apm821xx_pciex_core_init,
1115 .port_init_hw = apm821xx_pciex_init_port_hw,
1116 .setup_utl = ppc460ex_pciex_init_utl,
1117 .check_link = ppc4xx_pciex_check_link_sdr,
1118 };
1119
1120 static int __init ppc460sx_pciex_core_init(struct device_node *np)
1121 {
1122 /* HSS drive amplitude */
1123 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
1124 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
1125 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
1126 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
1127 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
1128 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
1129 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
1130 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
1131
1132 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
1133 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
1134 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
1135 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
1136
1137 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
1138 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
1139 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
1140 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
1141
1142 /* HSS TX pre-emphasis */
1143 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
1144 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
1145 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
1146 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
1147 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
1148 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
1149 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
1150 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
1151
1152 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
1153 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
1154 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
1155 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
1156
1157 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
1158 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
1159 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
1160 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
1161
1162 /* HSS TX calibration control */
1163 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
1164 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
1165 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
1166
1167 /* HSS TX slew control */
1168 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
1169 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
1170 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
1171
1172 /* Set HSS PRBS enabled */
1173 mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130);
1174 mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130);
1175
1176 udelay(100);
1177
1178 /* De-assert PLLRESET */
1179 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
1180
1181 /* Reset DL, UTL, GPL before configuration */
1182 mtdcri(SDR0, PESDR0_460SX_RCSSET,
1183 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1184 mtdcri(SDR0, PESDR1_460SX_RCSSET,
1185 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1186 mtdcri(SDR0, PESDR2_460SX_RCSSET,
1187 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1188
1189 udelay(100);
1190
1191 /*
1192 * If bifurcation is not enabled, u-boot would have disabled the
1193 * third PCIe port
1194 */
1195 if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
1196 0x00000001)) {
1197 printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
1198 printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
1199 return 3;
1200 }
1201
1202 printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
1203 return 2;
1204 }
1205
1206 static int __init ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1207 {
1208
1209 if (port->endpoint)
1210 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1211 0x01000000, 0);
1212 else
1213 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1214 0, 0x01000000);
1215
1216 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
1217 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
1218 PESDRx_RCSSET_RSTPYN);
1219
1220 port->has_ibpre = 1;
1221
1222 return ppc4xx_pciex_port_reset_sdr(port);
1223 }
1224
1225 static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
1226 {
1227 /* Max 128 Bytes */
1228 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
1229 /* Assert VRB and TXE - per datasheet turn off addr validation */
1230 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000);
1231 return 0;
1232 }
1233
1234 static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port *port)
1235 {
1236 void __iomem *mbase;
1237 int attempt = 50;
1238
1239 port->link = 0;
1240
1241 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1242 if (mbase == NULL) {
1243 printk(KERN_ERR "%pOF: Can't map internal config space !",
1244 port->node);
1245 goto done;
1246 }
1247
1248 while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA)
1249 & PECFG_460SX_DLLSTA_LINKUP))) {
1250 attempt--;
1251 mdelay(10);
1252 }
1253 if (attempt)
1254 port->link = 1;
1255 done:
1256 iounmap(mbase);
1257
1258 }
1259
1260 static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
1261 .want_sdr = true,
1262 .core_init = ppc460sx_pciex_core_init,
1263 .port_init_hw = ppc460sx_pciex_init_port_hw,
1264 .setup_utl = ppc460sx_pciex_init_utl,
1265 .check_link = ppc460sx_pciex_check_link,
1266 };
1267
1268 #endif /* CONFIG_44x */
1269
1270 #ifdef CONFIG_40x
1271
1272 static int __init ppc405ex_pciex_core_init(struct device_node *np)
1273 {
1274 /* Nothing to do, return 2 ports */
1275 return 2;
1276 }
1277
1278 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
1279 {
1280 /* Assert the PE0_PHY reset */
1281 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
1282 msleep(1);
1283
1284 /* deassert the PE0_hotreset */
1285 if (port->endpoint)
1286 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
1287 else
1288 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
1289
1290 /* poll for phy !reset */
1291 /* XXX FIXME add timeout */
1292 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
1293 ;
1294
1295 /* deassert the PE0_gpl_utl_reset */
1296 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
1297 }
1298
1299 static int __init ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1300 {
1301 u32 val;
1302
1303 if (port->endpoint)
1304 val = PTYPE_LEGACY_ENDPOINT;
1305 else
1306 val = PTYPE_ROOT_PORT;
1307
1308 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
1309 1 << 24 | val << 20 | LNKW_X1 << 12);
1310
1311 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1312 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1313 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
1314 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
1315
1316 /*
1317 * Only reset the PHY when no link is currently established.
1318 * This is for the Atheros PCIe board which has problems to establish
1319 * the link (again) after this PHY reset. All other currently tested
1320 * PCIe boards don't show this problem.
1321 * This has to be re-tested and fixed in a later release!
1322 */
1323 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
1324 if (!(val & 0x00001000))
1325 ppc405ex_pcie_phy_reset(port);
1326
1327 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
1328
1329 port->has_ibpre = 1;
1330
1331 return ppc4xx_pciex_port_reset_sdr(port);
1332 }
1333
1334 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1335 {
1336 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1337
1338 /*
1339 * Set buffer allocations and then assert VRB and TXE.
1340 */
1341 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
1342 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1343 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1344 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
1345 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1346 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1347 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
1348 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1349
1350 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
1351
1352 return 0;
1353 }
1354
1355 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1356 {
1357 .want_sdr = true,
1358 .core_init = ppc405ex_pciex_core_init,
1359 .port_init_hw = ppc405ex_pciex_init_port_hw,
1360 .setup_utl = ppc405ex_pciex_init_utl,
1361 .check_link = ppc4xx_pciex_check_link_sdr,
1362 };
1363
1364 #endif /* CONFIG_40x */
1365
1366 #ifdef CONFIG_476FPE
1367 static int __init ppc_476fpe_pciex_core_init(struct device_node *np)
1368 {
1369 return 4;
1370 }
1371
1372 static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port)
1373 {
1374 u32 timeout_ms = 20;
1375 u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT);
1376 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
1377 0x1000);
1378
1379 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
1380
1381 if (mbase == NULL) {
1382 printk(KERN_WARNING "PCIE%d: failed to get cfg space\n",
1383 port->index);
1384 return;
1385 }
1386
1387 while (timeout_ms--) {
1388 val = in_le32(mbase + PECFG_TLDLP);
1389
1390 if ((val & mask) == mask)
1391 break;
1392 msleep(10);
1393 }
1394
1395 if (val & PECFG_TLDLP_PRESENT) {
1396 printk(KERN_INFO "PCIE%d: link is up !\n", port->index);
1397 port->link = 1;
1398 } else
1399 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index);
1400
1401 iounmap(mbase);
1402 return;
1403 }
1404
1405 static struct ppc4xx_pciex_hwops ppc_476fpe_pcie_hwops __initdata =
1406 {
1407 .core_init = ppc_476fpe_pciex_core_init,
1408 .check_link = ppc_476fpe_pciex_check_link,
1409 };
1410 #endif /* CONFIG_476FPE */
1411
1412 /* Check that the core has been initied and if not, do it */
1413 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1414 {
1415 static int core_init;
1416 int count = -ENODEV;
1417
1418 if (core_init++)
1419 return 0;
1420
1421 #ifdef CONFIG_44x
1422 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
1423 if (ppc440spe_revA())
1424 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1425 else
1426 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1427 }
1428 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1429 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1430 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
1431 ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
1432 if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx"))
1433 ppc4xx_pciex_hwops = &apm821xx_pcie_hwops;
1434 #endif /* CONFIG_44x */
1435 #ifdef CONFIG_40x
1436 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1437 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1438 #endif
1439 #ifdef CONFIG_476FPE
1440 if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe")
1441 || of_device_is_compatible(np, "ibm,plb-pciex-476gtr"))
1442 ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops;
1443 #endif
1444 if (ppc4xx_pciex_hwops == NULL) {
1445 printk(KERN_WARNING "PCIE: unknown host type %pOF\n", np);
1446 return -ENODEV;
1447 }
1448
1449 count = ppc4xx_pciex_hwops->core_init(np);
1450 if (count > 0) {
1451 ppc4xx_pciex_ports =
1452 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1453 GFP_KERNEL);
1454 if (ppc4xx_pciex_ports) {
1455 ppc4xx_pciex_port_count = count;
1456 return 0;
1457 }
1458 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1459 return -ENOMEM;
1460 }
1461 return -ENODEV;
1462 }
1463
1464 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1465 {
1466 /* We map PCI Express configuration based on the reg property */
1467 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1468 RES_TO_U32_HIGH(port->cfg_space.start));
1469 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1470 RES_TO_U32_LOW(port->cfg_space.start));
1471
1472 /* XXX FIXME: Use size from reg property. For now, map 512M */
1473 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1474
1475 /* We map UTL registers based on the reg property */
1476 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1477 RES_TO_U32_HIGH(port->utl_regs.start));
1478 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1479 RES_TO_U32_LOW(port->utl_regs.start));
1480
1481 /* XXX FIXME: Use size from reg property */
1482 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1483
1484 /* Disable all other outbound windows */
1485 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1486 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1487 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1488 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1489 }
1490
1491 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1492 {
1493 int rc = 0;
1494
1495 /* Init HW */
1496 if (ppc4xx_pciex_hwops->port_init_hw)
1497 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1498 if (rc != 0)
1499 return rc;
1500
1501 /*
1502 * Initialize mapping: disable all regions and configure
1503 * CFG and REG regions based on resources in the device tree
1504 */
1505 ppc4xx_pciex_port_init_mapping(port);
1506
1507 if (ppc4xx_pciex_hwops->check_link)
1508 ppc4xx_pciex_hwops->check_link(port);
1509
1510 /*
1511 * Map UTL
1512 */
1513 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1514 BUG_ON(port->utl_base == NULL);
1515
1516 /*
1517 * Setup UTL registers --BenH.
1518 */
1519 if (ppc4xx_pciex_hwops->setup_utl)
1520 ppc4xx_pciex_hwops->setup_utl(port);
1521
1522 /*
1523 * Check for VC0 active or PLL Locked and assert RDY.
1524 */
1525 if (port->sdr_base) {
1526 if (of_device_is_compatible(port->node,
1527 "ibm,plb-pciex-460sx")){
1528 if (port->link && ppc4xx_pciex_wait_on_sdr(port,
1529 PESDRn_RCSSTS,
1530 1 << 12, 1 << 12, 5000)) {
1531 printk(KERN_INFO "PCIE%d: PLL not locked\n",
1532 port->index);
1533 port->link = 0;
1534 }
1535 } else if (port->link &&
1536 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1537 1 << 16, 1 << 16, 5000)) {
1538 printk(KERN_INFO "PCIE%d: VC0 not active\n",
1539 port->index);
1540 port->link = 0;
1541 }
1542
1543 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1544 }
1545
1546 msleep(100);
1547
1548 return 0;
1549 }
1550
1551 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1552 struct pci_bus *bus,
1553 unsigned int devfn)
1554 {
1555 static int message;
1556
1557 /* Endpoint can not generate upstream(remote) config cycles */
1558 if (port->endpoint && bus->number != port->hose->first_busno)
1559 return PCIBIOS_DEVICE_NOT_FOUND;
1560
1561 /* Check we are within the mapped range */
1562 if (bus->number > port->hose->last_busno) {
1563 if (!message) {
1564 printk(KERN_WARNING "Warning! Probing bus %u"
1565 " out of range !\n", bus->number);
1566 message++;
1567 }
1568 return PCIBIOS_DEVICE_NOT_FOUND;
1569 }
1570
1571 /* The root complex has only one device / function */
1572 if (bus->number == port->hose->first_busno && devfn != 0)
1573 return PCIBIOS_DEVICE_NOT_FOUND;
1574
1575 /* The other side of the RC has only one device as well */
1576 if (bus->number == (port->hose->first_busno + 1) &&
1577 PCI_SLOT(devfn) != 0)
1578 return PCIBIOS_DEVICE_NOT_FOUND;
1579
1580 /* Check if we have a link */
1581 if ((bus->number != port->hose->first_busno) && !port->link)
1582 return PCIBIOS_DEVICE_NOT_FOUND;
1583
1584 return 0;
1585 }
1586
1587 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1588 struct pci_bus *bus,
1589 unsigned int devfn)
1590 {
1591 int relbus;
1592
1593 /* Remove the casts when we finally remove the stupid volatile
1594 * in struct pci_controller
1595 */
1596 if (bus->number == port->hose->first_busno)
1597 return (void __iomem *)port->hose->cfg_addr;
1598
1599 relbus = bus->number - (port->hose->first_busno + 1);
1600 return (void __iomem *)port->hose->cfg_data +
1601 ((relbus << 20) | (devfn << 12));
1602 }
1603
1604 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1605 int offset, int len, u32 *val)
1606 {
1607 struct pci_controller *hose = pci_bus_to_host(bus);
1608 struct ppc4xx_pciex_port *port =
1609 &ppc4xx_pciex_ports[hose->indirect_type];
1610 void __iomem *addr;
1611 u32 gpl_cfg;
1612
1613 BUG_ON(hose != port->hose);
1614
1615 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1616 return PCIBIOS_DEVICE_NOT_FOUND;
1617
1618 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1619
1620 /*
1621 * Reading from configuration space of non-existing device can
1622 * generate transaction errors. For the read duration we suppress
1623 * assertion of machine check exceptions to avoid those.
1624 */
1625 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1626 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1627
1628 /* Make sure no CRS is recorded */
1629 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1630
1631 switch (len) {
1632 case 1:
1633 *val = in_8((u8 *)(addr + offset));
1634 break;
1635 case 2:
1636 *val = in_le16((u16 *)(addr + offset));
1637 break;
1638 default:
1639 *val = in_le32((u32 *)(addr + offset));
1640 break;
1641 }
1642
1643 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1644 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1645 bus->number, hose->first_busno, hose->last_busno,
1646 devfn, offset, len, addr + offset, *val);
1647
1648 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1649 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1650 pr_debug("Got CRS !\n");
1651 if (len != 4 || offset != 0)
1652 return PCIBIOS_DEVICE_NOT_FOUND;
1653 *val = 0xffff0001;
1654 }
1655
1656 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1657
1658 return PCIBIOS_SUCCESSFUL;
1659 }
1660
1661 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1662 int offset, int len, u32 val)
1663 {
1664 struct pci_controller *hose = pci_bus_to_host(bus);
1665 struct ppc4xx_pciex_port *port =
1666 &ppc4xx_pciex_ports[hose->indirect_type];
1667 void __iomem *addr;
1668 u32 gpl_cfg;
1669
1670 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1671 return PCIBIOS_DEVICE_NOT_FOUND;
1672
1673 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1674
1675 /*
1676 * Reading from configuration space of non-existing device can
1677 * generate transaction errors. For the read duration we suppress
1678 * assertion of machine check exceptions to avoid those.
1679 */
1680 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1681 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1682
1683 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1684 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1685 bus->number, hose->first_busno, hose->last_busno,
1686 devfn, offset, len, addr + offset, val);
1687
1688 switch (len) {
1689 case 1:
1690 out_8((u8 *)(addr + offset), val);
1691 break;
1692 case 2:
1693 out_le16((u16 *)(addr + offset), val);
1694 break;
1695 default:
1696 out_le32((u32 *)(addr + offset), val);
1697 break;
1698 }
1699
1700 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1701
1702 return PCIBIOS_SUCCESSFUL;
1703 }
1704
1705 static struct pci_ops ppc4xx_pciex_pci_ops =
1706 {
1707 .read = ppc4xx_pciex_read_config,
1708 .write = ppc4xx_pciex_write_config,
1709 };
1710
1711 static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
1712 struct pci_controller *hose,
1713 void __iomem *mbase,
1714 u64 plb_addr,
1715 u64 pci_addr,
1716 u64 size,
1717 unsigned int flags,
1718 int index)
1719 {
1720 u32 lah, lal, pciah, pcial, sa;
1721
1722 if (!is_power_of_2(size) ||
1723 (index < 2 && size < 0x100000) ||
1724 (index == 2 && size < 0x100) ||
1725 (plb_addr & (size - 1)) != 0) {
1726 printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn);
1727 return -1;
1728 }
1729
1730 /* Calculate register values */
1731 lah = RES_TO_U32_HIGH(plb_addr);
1732 lal = RES_TO_U32_LOW(plb_addr);
1733 pciah = RES_TO_U32_HIGH(pci_addr);
1734 pcial = RES_TO_U32_LOW(pci_addr);
1735 sa = (0xffffffffu << ilog2(size)) | 0x1;
1736
1737 /* Program register values */
1738 switch (index) {
1739 case 0:
1740 out_le32(mbase + PECFG_POM0LAH, pciah);
1741 out_le32(mbase + PECFG_POM0LAL, pcial);
1742 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1743 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1744 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1745 /*Enabled and single region */
1746 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
1747 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1748 sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
1749 | DCRO_PEGPL_OMRxMSKL_VAL);
1750 else if (of_device_is_compatible(
1751 port->node, "ibm,plb-pciex-476fpe") ||
1752 of_device_is_compatible(
1753 port->node, "ibm,plb-pciex-476gtr"))
1754 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1755 sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT
1756 | DCRO_PEGPL_OMRxMSKL_VAL);
1757 else
1758 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1759 sa | DCRO_PEGPL_OMR1MSKL_UOT
1760 | DCRO_PEGPL_OMRxMSKL_VAL);
1761 break;
1762 case 1:
1763 out_le32(mbase + PECFG_POM1LAH, pciah);
1764 out_le32(mbase + PECFG_POM1LAL, pcial);
1765 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1766 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1767 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1768 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,
1769 sa | DCRO_PEGPL_OMRxMSKL_VAL);
1770 break;
1771 case 2:
1772 out_le32(mbase + PECFG_POM2LAH, pciah);
1773 out_le32(mbase + PECFG_POM2LAL, pcial);
1774 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1775 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1776 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1777 /* Note that 3 here means enabled | IO space !!! */
1778 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,
1779 sa | DCRO_PEGPL_OMR3MSKL_IO
1780 | DCRO_PEGPL_OMRxMSKL_VAL);
1781 break;
1782 }
1783
1784 return 0;
1785 }
1786
1787 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1788 struct pci_controller *hose,
1789 void __iomem *mbase)
1790 {
1791 int i, j, found_isa_hole = 0;
1792
1793 /* Setup outbound memory windows */
1794 for (i = j = 0; i < 3; i++) {
1795 struct resource *res = &hose->mem_resources[i];
1796 resource_size_t offset = hose->mem_offset[i];
1797
1798 /* we only care about memory windows */
1799 if (!(res->flags & IORESOURCE_MEM))
1800 continue;
1801 if (j > 1) {
1802 printk(KERN_WARNING "%pOF: Too many ranges\n",
1803 port->node);
1804 break;
1805 }
1806
1807 /* Configure the resource */
1808 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1809 res->start,
1810 res->start - offset,
1811 resource_size(res),
1812 res->flags,
1813 j) == 0) {
1814 j++;
1815
1816 /* If the resource PCI address is 0 then we have our
1817 * ISA memory hole
1818 */
1819 if (res->start == offset)
1820 found_isa_hole = 1;
1821 }
1822 }
1823
1824 /* Handle ISA memory hole if not already covered */
1825 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
1826 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1827 hose->isa_mem_phys, 0,
1828 hose->isa_mem_size, 0, j) == 0)
1829 printk(KERN_INFO "%pOF: Legacy ISA memory support enabled\n",
1830 hose->dn);
1831
1832 /* Configure IO, always 64K starting at 0. We hard wire it to 64K !
1833 * Note also that it -has- to be region index 2 on this HW
1834 */
1835 if (hose->io_resource.flags & IORESOURCE_IO)
1836 ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1837 hose->io_base_phys, 0,
1838 0x10000, IORESOURCE_IO, 2);
1839 }
1840
1841 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1842 struct pci_controller *hose,
1843 void __iomem *mbase,
1844 struct resource *res)
1845 {
1846 resource_size_t size = resource_size(res);
1847 u64 sa;
1848
1849 if (port->endpoint) {
1850 resource_size_t ep_addr = 0;
1851 resource_size_t ep_size = 32 << 20;
1852
1853 /* Currently we map a fixed 64MByte window to PLB address
1854 * 0 (SDRAM). This should probably be configurable via a dts
1855 * property.
1856 */
1857
1858 /* Calculate window size */
1859 sa = (0xffffffffffffffffull << ilog2(ep_size));
1860
1861 /* Setup BAR0 */
1862 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1863 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1864 PCI_BASE_ADDRESS_MEM_TYPE_64);
1865
1866 /* Disable BAR1 & BAR2 */
1867 out_le32(mbase + PECFG_BAR1MPA, 0);
1868 out_le32(mbase + PECFG_BAR2HMPA, 0);
1869 out_le32(mbase + PECFG_BAR2LMPA, 0);
1870
1871 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1872 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1873
1874 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1875 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1876 } else {
1877 /* Calculate window size */
1878 sa = (0xffffffffffffffffull << ilog2(size));
1879 if (res->flags & IORESOURCE_PREFETCH)
1880 sa |= PCI_BASE_ADDRESS_MEM_PREFETCH;
1881
1882 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
1883 of_device_is_compatible(
1884 port->node, "ibm,plb-pciex-476fpe") ||
1885 of_device_is_compatible(
1886 port->node, "ibm,plb-pciex-476gtr"))
1887 sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
1888
1889 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1890 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1891
1892 /* The setup of the split looks weird to me ... let's see
1893 * if it works
1894 */
1895 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1896 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1897 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1898 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1899 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1900 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1901
1902 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1903 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1904 }
1905
1906 /* Enable inbound mapping */
1907 out_le32(mbase + PECFG_PIMEN, 0x1);
1908
1909 /* Enable I/O, Mem, and Busmaster cycles */
1910 out_le16(mbase + PCI_COMMAND,
1911 in_le16(mbase + PCI_COMMAND) |
1912 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1913 }
1914
1915 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1916 {
1917 struct resource dma_window;
1918 struct pci_controller *hose = NULL;
1919 const int *bus_range;
1920 int primary = 0, busses;
1921 void __iomem *mbase = NULL, *cfg_data = NULL;
1922 const u32 *pval;
1923 u32 val;
1924
1925 /* Check if primary bridge */
1926 if (of_get_property(port->node, "primary", NULL))
1927 primary = 1;
1928
1929 /* Get bus range if any */
1930 bus_range = of_get_property(port->node, "bus-range", NULL);
1931
1932 /* Allocate the host controller data structure */
1933 hose = pcibios_alloc_controller(port->node);
1934 if (!hose)
1935 goto fail;
1936
1937 /* We stick the port number in "indirect_type" so the config space
1938 * ops can retrieve the port data structure easily
1939 */
1940 hose->indirect_type = port->index;
1941
1942 /* Get bus range */
1943 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1944 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1945
1946 /* Because of how big mapping the config space is (1M per bus), we
1947 * limit how many busses we support. In the long run, we could replace
1948 * that with something akin to kmap_atomic instead. We set aside 1 bus
1949 * for the host itself too.
1950 */
1951 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1952 if (busses > MAX_PCIE_BUS_MAPPED) {
1953 busses = MAX_PCIE_BUS_MAPPED;
1954 hose->last_busno = hose->first_busno + busses;
1955 }
1956
1957 if (!port->endpoint) {
1958 /* Only map the external config space in cfg_data for
1959 * PCIe root-complexes. External space is 1M per bus
1960 */
1961 cfg_data = ioremap(port->cfg_space.start +
1962 (hose->first_busno + 1) * 0x100000,
1963 busses * 0x100000);
1964 if (cfg_data == NULL) {
1965 printk(KERN_ERR "%pOF: Can't map external config space !",
1966 port->node);
1967 goto fail;
1968 }
1969 hose->cfg_data = cfg_data;
1970 }
1971
1972 /* Always map the host config space in cfg_addr.
1973 * Internal space is 4K
1974 */
1975 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1976 if (mbase == NULL) {
1977 printk(KERN_ERR "%pOF: Can't map internal config space !",
1978 port->node);
1979 goto fail;
1980 }
1981 hose->cfg_addr = mbase;
1982
1983 pr_debug("PCIE %pOF, bus %d..%d\n", port->node,
1984 hose->first_busno, hose->last_busno);
1985 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1986 hose->cfg_addr, hose->cfg_data);
1987
1988 /* Setup config space */
1989 hose->ops = &ppc4xx_pciex_pci_ops;
1990 port->hose = hose;
1991 mbase = (void __iomem *)hose->cfg_addr;
1992
1993 if (!port->endpoint) {
1994 /*
1995 * Set bus numbers on our root port
1996 */
1997 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1998 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1999 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
2000 }
2001
2002 /*
2003 * OMRs are already reset, also disable PIMs
2004 */
2005 out_le32(mbase + PECFG_PIMEN, 0);
2006
2007 /* Parse outbound mapping resources */
2008 pci_process_bridge_OF_ranges(hose, port->node, primary);
2009
2010 /* Parse inbound mapping resources */
2011 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
2012 goto fail;
2013
2014 /* Configure outbound ranges POMs */
2015 ppc4xx_configure_pciex_POMs(port, hose, mbase);
2016
2017 /* Configure inbound ranges PIMs */
2018 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
2019
2020 /* The root complex doesn't show up if we don't set some vendor
2021 * and device IDs into it. The defaults below are the same bogus
2022 * one that the initial code in arch/ppc had. This can be
2023 * overwritten by setting the "vendor-id/device-id" properties
2024 * in the pciex node.
2025 */
2026
2027 /* Get the (optional) vendor-/device-id from the device-tree */
2028 pval = of_get_property(port->node, "vendor-id", NULL);
2029 if (pval) {
2030 val = *pval;
2031 } else {
2032 if (!port->endpoint)
2033 val = 0xaaa0 + port->index;
2034 else
2035 val = 0xeee0 + port->index;
2036 }
2037 out_le16(mbase + 0x200, val);
2038
2039 pval = of_get_property(port->node, "device-id", NULL);
2040 if (pval) {
2041 val = *pval;
2042 } else {
2043 if (!port->endpoint)
2044 val = 0xbed0 + port->index;
2045 else
2046 val = 0xfed0 + port->index;
2047 }
2048 out_le16(mbase + 0x202, val);
2049
2050 /* Enable Bus master, memory, and io space */
2051 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
2052 out_le16(mbase + 0x204, 0x7);
2053
2054 if (!port->endpoint) {
2055 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
2056 out_le32(mbase + 0x208, 0x06040001);
2057
2058 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
2059 port->index);
2060 } else {
2061 /* Set Class Code to Processor/PPC */
2062 out_le32(mbase + 0x208, 0x0b200001);
2063
2064 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
2065 port->index);
2066 }
2067
2068 return;
2069 fail:
2070 if (hose)
2071 pcibios_free_controller(hose);
2072 if (cfg_data)
2073 iounmap(cfg_data);
2074 if (mbase)
2075 iounmap(mbase);
2076 }
2077
2078 static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
2079 {
2080 struct ppc4xx_pciex_port *port;
2081 const u32 *pval;
2082 int portno;
2083 unsigned int dcrs;
2084 const char *val;
2085
2086 /* First, proceed to core initialization as we assume there's
2087 * only one PCIe core in the system
2088 */
2089 if (ppc4xx_pciex_check_core_init(np))
2090 return;
2091
2092 /* Get the port number from the device-tree */
2093 pval = of_get_property(np, "port", NULL);
2094 if (pval == NULL) {
2095 printk(KERN_ERR "PCIE: Can't find port number for %pOF\n", np);
2096 return;
2097 }
2098 portno = *pval;
2099 if (portno >= ppc4xx_pciex_port_count) {
2100 printk(KERN_ERR "PCIE: port number out of range for %pOF\n",
2101 np);
2102 return;
2103 }
2104 port = &ppc4xx_pciex_ports[portno];
2105 port->index = portno;
2106
2107 /*
2108 * Check if device is enabled
2109 */
2110 if (!of_device_is_available(np)) {
2111 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
2112 return;
2113 }
2114
2115 port->node = of_node_get(np);
2116 if (ppc4xx_pciex_hwops->want_sdr) {
2117 pval = of_get_property(np, "sdr-base", NULL);
2118 if (pval == NULL) {
2119 printk(KERN_ERR "PCIE: missing sdr-base for %pOF\n",
2120 np);
2121 return;
2122 }
2123 port->sdr_base = *pval;
2124 }
2125
2126 /* Check if device_type property is set to "pci" or "pci-endpoint".
2127 * Resulting from this setup this PCIe port will be configured
2128 * as root-complex or as endpoint.
2129 */
2130 val = of_get_property(port->node, "device_type", NULL);
2131 if (!strcmp(val, "pci-endpoint")) {
2132 port->endpoint = 1;
2133 } else if (!strcmp(val, "pci")) {
2134 port->endpoint = 0;
2135 } else {
2136 printk(KERN_ERR "PCIE: missing or incorrect device_type for %pOF\n",
2137 np);
2138 return;
2139 }
2140
2141 /* Fetch config space registers address */
2142 if (of_address_to_resource(np, 0, &port->cfg_space)) {
2143 printk(KERN_ERR "%pOF: Can't get PCI-E config space !", np);
2144 return;
2145 }
2146 /* Fetch host bridge internal registers address */
2147 if (of_address_to_resource(np, 1, &port->utl_regs)) {
2148 printk(KERN_ERR "%pOF: Can't get UTL register base !", np);
2149 return;
2150 }
2151
2152 /* Map DCRs */
2153 dcrs = dcr_resource_start(np, 0);
2154 if (dcrs == 0) {
2155 printk(KERN_ERR "%pOF: Can't get DCR register base !", np);
2156 return;
2157 }
2158 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
2159
2160 /* Initialize the port specific registers */
2161 if (ppc4xx_pciex_port_init(port)) {
2162 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
2163 return;
2164 }
2165
2166 /* Setup the linux hose data structure */
2167 ppc4xx_pciex_port_setup_hose(port);
2168 }
2169
2170 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
2171
2172 static int __init ppc4xx_pci_find_bridges(void)
2173 {
2174 struct device_node *np;
2175
2176 pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
2177
2178 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
2179 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
2180 ppc4xx_probe_pciex_bridge(np);
2181 #endif
2182 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
2183 ppc4xx_probe_pcix_bridge(np);
2184 for_each_compatible_node(np, NULL, "ibm,plb-pci")
2185 ppc4xx_probe_pci_bridge(np);
2186
2187 return 0;
2188 }
2189 arch_initcall(ppc4xx_pci_find_bridges);
2190
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