arch/powerpc/platforms/chrp/setup.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1995  Linus Torvalds
   4  *  Adapted from 'alpha' version by Gary Thomas
   5  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   6  */
   7
   8 /*
   9  * bootup setup stuff..
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/sched.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mm.h>
  16 #include <linux/stddef.h>
  17 #include <linux/unistd.h>
  18 #include <linux/ptrace.h>
  19 #include <linux/user.h>
  20 #include <linux/tty.h>
  21 #include <linux/major.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/reboot.h>
  24 #include <linux/init.h>
  25 #include <linux/pci.h>
  26 #include <generated/utsrelease.h>
  27 #include <linux/adb.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/console.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/root_dev.h>
  33 #include <linux/initrd.h>
  34 #include <linux/timer.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/prom.h>
  39 #include <asm/pci-bridge.h>
  40 #include <asm/dma.h>
  41 #include <asm/machdep.h>
  42 #include <asm/irq.h>
  43 #include <asm/hydra.h>
  44 #include <asm/sections.h>
  45 #include <asm/time.h>
  46 #include <asm/i8259.h>
  47 #include <asm/mpic.h>
  48 #include <asm/rtas.h>
  49 #include <asm/xmon.h>
  50
  51 #include "chrp.h"
  52 #include "gg2.h"
  53
  54 void rtas_indicator_progress(char *, unsigned short);
  55
  56 int _chrp_type;
  57 EXPORT_SYMBOL(_chrp_type);
  58
  59 static struct mpic *chrp_mpic;
  60
  61 /* Used for doing CHRP event-scans */
  62 DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
  63 unsigned long event_scan_interval;
  64
  65 extern unsigned long loops_per_jiffy;
  66
  67 /* To be replaced by RTAS when available */
  68 static unsigned int __iomem *briq_SPOR;
  69
  70 #ifdef CONFIG_SMP
  71 extern struct smp_ops_t chrp_smp_ops;
  72 #endif
  73
  74 static const char *gg2_memtypes[4] = {
  75         "FPM", "SDRAM", "EDO", "BEDO"
  76 };
  77 static const char *gg2_cachesizes[4] = {
  78         "256 KB", "512 KB", "1 MB", "Reserved"
  79 };
  80 static const char *gg2_cachetypes[4] = {
  81         "Asynchronous", "Reserved", "Flow-Through Synchronous",
  82         "Pipelined Synchronous"
  83 };
  84 static const char *gg2_cachemodes[4] = {
  85         "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
  86 };
  87
  88 static const char *chrp_names[] = {
  89         "Unknown",
  90         "","","",
  91         "Motorola",
  92         "IBM or Longtrail",
  93         "Genesi Pegasos",
  94         "Total Impact Briq"
  95 };
  96
  97 void chrp_show_cpuinfo(struct seq_file *m)
  98 {
  99         int i, sdramen;
 100         unsigned int t;
 101         struct device_node *root;
 102         const char *model = "";
 103
 104         root = of_find_node_by_path("/");
 105         if (root)
 106                 model = of_get_property(root, "model", NULL);
 107         seq_printf(m, "machine\t\t: CHRP %s\n", model);
 108
 109         /* longtrail (goldengate) stuff */
 110         if (model && !strncmp(model, "IBM,LongTrail", 13)) {
 111                 /* VLSI VAS96011/12 `Golden Gate 2' */
 112                 /* Memory banks */
 113                 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
 114                            >>31) & 1;
 115                 for (i = 0; i < (sdramen ? 4 : 6); i++) {
 116                         t = in_le32(gg2_pci_config_base+
 117                                                  GG2_PCI_DRAM_BANK0+
 118                                                  i*4);
 119                         if (!(t & 1))
 120                                 continue;
 121                         switch ((t>>8) & 0x1f) {
 122                         case 0x1f:
 123                                 model = "4 MB";
 124                                 break;
 125                         case 0x1e:
 126                                 model = "8 MB";
 127                                 break;
 128                         case 0x1c:
 129                                 model = "16 MB";
 130                                 break;
 131                         case 0x18:
 132                                 model = "32 MB";
 133                                 break;
 134                         case 0x10:
 135                                 model = "64 MB";
 136                                 break;
 137                         case 0x00:
 138                                 model = "128 MB";
 139                                 break;
 140                         default:
 141                                 model = "Reserved";
 142                                 break;
 143                         }
 144                         seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
 145                                    gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
 146                 }
 147                 /* L2 cache */
 148                 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
 149                 seq_printf(m, "board l2\t: %s %s (%s)\n",
 150                            gg2_cachesizes[(t>>7) & 3],
 151                            gg2_cachetypes[(t>>2) & 3],
 152                            gg2_cachemodes[t & 3]);
 153         }
 154         of_node_put(root);
 155 }
 156
 157 /*
 158  *  Fixes for the National Semiconductor PC78308VUL SuperI/O
 159  *
 160  *  Some versions of Open Firmware incorrectly initialize the IRQ settings
 161  *  for keyboard and mouse
 162  */
 163 static inline void __init sio_write(u8 val, u8 index)
 164 {
 165         outb(index, 0x15c);
 166         outb(val, 0x15d);
 167 }
 168
 169 static inline u8 __init sio_read(u8 index)
 170 {
 171         outb(index, 0x15c);
 172         return inb(0x15d);
 173 }
 174
 175 static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
 176                                      u8 type)
 177 {
 178         u8 level0, type0, active;
 179
 180         /* select logical device */
 181         sio_write(device, 0x07);
 182         active = sio_read(0x30);
 183         level0 = sio_read(0x70);
 184         type0 = sio_read(0x71);
 185         if (level0 != level || type0 != type || !active) {
 186                 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
 187                        "remapping to level %d, type %d, active\n",
 188                        name, level0, type0, !active ? "in" : "", level, type);
 189                 sio_write(0x01, 0x30);
 190                 sio_write(level, 0x70);
 191                 sio_write(type, 0x71);
 192         }
 193 }
 194
 195 static void __init sio_init(void)
 196 {
 197         struct device_node *root;
 198         const char *model;
 199
 200         root = of_find_node_by_path("/");
 201         if (!root)
 202                 return;
 203
 204         model = of_get_property(root, "model", NULL);
 205         if (model && !strncmp(model, "IBM,LongTrail", 13)) {
 206                 /* logical device 0 (KBC/Keyboard) */
 207                 sio_fixup_irq("keyboard", 0, 1, 2);
 208                 /* select logical device 1 (KBC/Mouse) */
 209                 sio_fixup_irq("mouse", 1, 12, 2);
 210         }
 211
 212         of_node_put(root);
 213 }
 214
 215
 216 static void __init pegasos_set_l2cr(void)
 217 {
 218         struct device_node *np;
 219
 220         /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
 221         if (_chrp_type != _CHRP_Pegasos)
 222                 return;
 223
 224         /* Enable L2 cache if needed */
 225         np = of_find_node_by_type(NULL, "cpu");
 226         if (np != NULL) {
 227                 const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
 228                 if (l2cr == NULL) {
 229                         printk ("Pegasos l2cr : no cpu l2cr property found\n");
 230                         goto out;
 231                 }
 232                 if (!((*l2cr) & 0x80000000)) {
 233                         printk ("Pegasos l2cr : L2 cache was not active, "
 234                                 "activating\n");
 235                         _set_L2CR(0);
 236                         _set_L2CR((*l2cr) | 0x80000000);
 237                 }
 238         }
 239 out:
 240         of_node_put(np);
 241 }
 242
 243 static void __noreturn briq_restart(char *cmd)
 244 {
 245         local_irq_disable();
 246         if (briq_SPOR)
 247                 out_be32(briq_SPOR, 0);
 248         for(;;);
 249 }
 250
 251 /*
 252  * Per default, input/output-device points to the keyboard/screen
 253  * If no card is installed, the built-in serial port is used as a fallback.
 254  * But unfortunately, the firmware does not connect /chosen/{stdin,stdout}
 255  * the the built-in serial node. Instead, a /failsafe node is created.
 256  */
 257 static __init void chrp_init(void)
 258 {
 259         struct device_node *node;
 260         const char *property;
 261
 262         if (strstr(boot_command_line, "console="))
 263                 return;
 264         /* find the boot console from /chosen/stdout */
 265         if (!of_chosen)
 266                 return;
 267         node = of_find_node_by_path("/");
 268         if (!node)
 269                 return;
 270         property = of_get_property(node, "model", NULL);
 271         if (!property)
 272                 goto out_put;
 273         if (strcmp(property, "Pegasos2"))
 274                 goto out_put;
 275         /* this is a Pegasos2 */
 276         property = of_get_property(of_chosen, "linux,stdout-path", NULL);
 277         if (!property)
 278                 goto out_put;
 279         of_node_put(node);
 280         node = of_find_node_by_path(property);
 281         if (!node)
 282                 return;
 283         property = of_get_property(node, "device_type", NULL);
 284         if (!property)
 285                 goto out_put;
 286         if (strcmp(property, "serial"))
 287                 goto out_put;
 288         /*
 289          * The 9pin connector is either /failsafe
 290          * or /pci@80000000/isa@C/serial@i2F8
 291          * The optional graphics card has also type 'serial' in VGA mode.
 292          */
 293         property = of_get_property(node, "name", NULL);
 294         if (!property)
 295                 goto out_put;
 296         if (!strcmp(property, "failsafe") || !strcmp(property, "serial"))
 297                 add_preferred_console("ttyS", 0, NULL);
 298 out_put:
 299         of_node_put(node);
 300 }
 301
 302 void __init chrp_setup_arch(void)
 303 {
 304         struct device_node *root = of_find_node_by_path("/");
 305         const char *machine = NULL;
 306
 307         /* init to some ~sane value until calibrate_delay() runs */
 308         loops_per_jiffy = 50000000/HZ;
 309
 310         if (root)
 311                 machine = of_get_property(root, "model", NULL);
 312         if (machine && strncmp(machine, "Pegasos", 7) == 0) {
 313                 _chrp_type = _CHRP_Pegasos;
 314         } else if (machine && strncmp(machine, "IBM", 3) == 0) {
 315                 _chrp_type = _CHRP_IBM;
 316         } else if (machine && strncmp(machine, "MOT", 3) == 0) {
 317                 _chrp_type = _CHRP_Motorola;
 318         } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
 319                 _chrp_type = _CHRP_briq;
 320                 /* Map the SPOR register on briq and change the restart hook */
 321                 briq_SPOR = ioremap(0xff0000e8, 4);
 322                 ppc_md.restart = briq_restart;
 323         } else {
 324                 /* Let's assume it is an IBM chrp if all else fails */
 325                 _chrp_type = _CHRP_IBM;
 326         }
 327         of_node_put(root);
 328         printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
 329
 330         rtas_initialize();
 331         if (rtas_token("display-character") >= 0)
 332                 ppc_md.progress = rtas_progress;
 333
 334         /* use RTAS time-of-day routines if available */
 335         if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
 336                 ppc_md.get_boot_time    = rtas_get_boot_time;
 337                 ppc_md.get_rtc_time     = rtas_get_rtc_time;
 338                 ppc_md.set_rtc_time     = rtas_set_rtc_time;
 339         }
 340
 341         /* On pegasos, enable the L2 cache if not already done by OF */
 342         pegasos_set_l2cr();
 343
 344         /* Lookup PCI host bridges */
 345         chrp_find_bridges();
 346
 347         /*
 348          *  Temporary fixes for PCI devices.
 349          *  -- Geert
 350          */
 351         hydra_init();           /* Mac I/O */
 352
 353         /*
 354          *  Fix the Super I/O configuration
 355          */
 356         sio_init();
 357
 358         pci_create_OF_bus_map();
 359
 360         /*
 361          * Print the banner, then scroll down so boot progress
 362          * can be printed.  -- Cort
 363          */
 364         if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
 365 }
 366
 367 static void chrp_8259_cascade(struct irq_desc *desc)
 368 {
 369         struct irq_chip *chip = irq_desc_get_chip(desc);
 370         unsigned int cascade_irq = i8259_irq();
 371
 372         if (cascade_irq)
 373                 generic_handle_irq(cascade_irq);
 374
 375         chip->irq_eoi(&desc->irq_data);
 376 }
 377
 378 /*
 379  * Finds the open-pic node and sets up the mpic driver.
 380  */
 381 static void __init chrp_find_openpic(void)
 382 {
 383         struct device_node *np, *root;
 384         int len, i, j;
 385         int isu_size, idu_size;
 386         const unsigned int *iranges, *opprop = NULL;
 387         int oplen = 0;
 388         unsigned long opaddr;
 389         int na = 1;
 390
 391         np = of_find_node_by_type(NULL, "open-pic");
 392         if (np == NULL)
 393                 return;
 394         root = of_find_node_by_path("/");
 395         if (root) {
 396                 opprop = of_get_property(root, "platform-open-pic", &oplen);
 397                 na = of_n_addr_cells(root);
 398         }
 399         if (opprop && oplen >= na * sizeof(unsigned int)) {
 400                 opaddr = opprop[na-1];  /* assume 32-bit */
 401                 oplen /= na * sizeof(unsigned int);
 402         } else {
 403                 struct resource r;
 404                 if (of_address_to_resource(np, 0, &r)) {
 405                         goto bail;
 406                 }
 407                 opaddr = r.start;
 408                 oplen = 0;
 409         }
 410
 411         printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
 412
 413         iranges = of_get_property(np, "interrupt-ranges", &len);
 414         if (iranges == NULL)
 415                 len = 0;        /* non-distributed mpic */
 416         else
 417                 len /= 2 * sizeof(unsigned int);
 418
 419         /*
 420          * The first pair of cells in interrupt-ranges refers to the
 421          * IDU; subsequent pairs refer to the ISUs.
 422          */
 423         if (oplen < len) {
 424                 printk(KERN_ERR "Insufficient addresses for distributed"
 425                        " OpenPIC (%d < %d)\n", oplen, len);
 426                 len = oplen;
 427         }
 428
 429         isu_size = 0;
 430         idu_size = 0;
 431         if (len > 0 && iranges[1] != 0) {
 432                 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
 433                        iranges[0], iranges[0] + iranges[1] - 1);
 434                 idu_size = iranges[1];
 435         }
 436         if (len > 1)
 437                 isu_size = iranges[3];
 438
 439         chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET,
 440                         isu_size, 0, " MPIC    ");
 441         if (chrp_mpic == NULL) {
 442                 printk(KERN_ERR "Failed to allocate MPIC structure\n");
 443                 goto bail;
 444         }
 445         j = na - 1;
 446         for (i = 1; i < len; ++i) {
 447                 iranges += 2;
 448                 j += na;
 449                 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
 450                        iranges[0], iranges[0] + iranges[1] - 1,
 451                        opprop[j]);
 452                 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
 453         }
 454
 455         mpic_init(chrp_mpic);
 456         ppc_md.get_irq = mpic_get_irq;
 457  bail:
 458         of_node_put(root);
 459         of_node_put(np);
 460 }
 461
 462 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
 463 static struct irqaction xmon_irqaction = {
 464         .handler = xmon_irq,
 465         .name = "XMON break",
 466 };
 467 #endif
 468
 469 static void __init chrp_find_8259(void)
 470 {
 471         struct device_node *np, *pic = NULL;
 472         unsigned long chrp_int_ack = 0;
 473         unsigned int cascade_irq;
 474
 475         /* Look for cascade */
 476         for_each_node_by_type(np, "interrupt-controller")
 477                 if (of_device_is_compatible(np, "chrp,iic")) {
 478                         pic = np;
 479                         break;
 480                 }
 481         /* Ok, 8259 wasn't found. We need to handle the case where
 482          * we have a pegasos that claims to be chrp but doesn't have
 483          * a proper interrupt tree
 484          */
 485         if (pic == NULL && chrp_mpic != NULL) {
 486                 printk(KERN_ERR "i8259: Not found in device-tree"
 487                        " assuming no legacy interrupts\n");
 488                 return;
 489         }
 490
 491         /* Look for intack. In a perfect world, we would look for it on
 492          * the ISA bus that holds the 8259 but heh... Works that way. If
 493          * we ever see a problem, we can try to re-use the pSeries code here.
 494          * Also, Pegasos-type platforms don't have a proper node to start
 495          * from anyway
 496          */
 497         for_each_node_by_name(np, "pci") {
 498                 const unsigned int *addrp = of_get_property(np,
 499                                 "8259-interrupt-acknowledge", NULL);
 500
 501                 if (addrp == NULL)
 502                         continue;
 503                 chrp_int_ack = addrp[of_n_addr_cells(np)-1];
 504                 break;
 505         }
 506         of_node_put(np);
 507         if (np == NULL)
 508                 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
 509                        " address, polling\n");
 510
 511         i8259_init(pic, chrp_int_ack);
 512         if (ppc_md.get_irq == NULL) {
 513                 ppc_md.get_irq = i8259_irq;
 514                 irq_set_default_host(i8259_get_host());
 515         }
 516         if (chrp_mpic != NULL) {
 517                 cascade_irq = irq_of_parse_and_map(pic, 0);
 518                 if (!cascade_irq)
 519                         printk(KERN_ERR "i8259: failed to map cascade irq\n");
 520                 else
 521                         irq_set_chained_handler(cascade_irq,
 522                                                 chrp_8259_cascade);
 523         }
 524 }
 525
 526 void __init chrp_init_IRQ(void)
 527 {
 528 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
 529         struct device_node *kbd;
 530 #endif
 531         chrp_find_openpic();
 532         chrp_find_8259();
 533
 534 #ifdef CONFIG_SMP
 535         /* Pegasos has no MPIC, those ops would make it crash. It might be an
 536          * option to move setting them to after we probe the PIC though
 537          */
 538         if (chrp_mpic != NULL)
 539                 smp_ops = &chrp_smp_ops;
 540 #endif /* CONFIG_SMP */
 541
 542         if (_chrp_type == _CHRP_Pegasos)
 543                 ppc_md.get_irq        = i8259_irq;
 544
 545 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
 546         /* see if there is a keyboard in the device tree
 547            with a parent of type "adb" */
 548         for_each_node_by_name(kbd, "keyboard")
 549                 if (kbd->parent && kbd->parent->type
 550                     && strcmp(kbd->parent->type, "adb") == 0)
 551                         break;
 552         of_node_put(kbd);
 553         if (kbd)
 554                 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
 555 #endif
 556 }
 557
 558 void __init
 559 chrp_init2(void)
 560 {
 561 #ifdef CONFIG_NVRAM
 562         chrp_nvram_init();
 563 #endif
 564
 565         request_region(0x20,0x20,"pic1");
 566         request_region(0xa0,0x20,"pic2");
 567         request_region(0x00,0x20,"dma1");
 568         request_region(0x40,0x20,"timer");
 569         request_region(0x80,0x10,"dma page reg");
 570         request_region(0xc0,0x20,"dma2");
 571
 572         if (ppc_md.progress)
 573                 ppc_md.progress("  Have fun!    ", 0x7777);
 574 }
 575
 576 static int __init chrp_probe(void)
 577 {
 578         const char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
 579                                                 "device_type", NULL);
 580         if (dtype == NULL)
 581                 return 0;
 582         if (strcmp(dtype, "chrp"))
 583                 return 0;
 584
 585         ISA_DMA_THRESHOLD = ~0L;
 586         DMA_MODE_READ = 0x44;
 587         DMA_MODE_WRITE = 0x48;
 588
 589         pm_power_off = rtas_power_off;
 590
 591         chrp_init();
 592
 593         return 1;
 594 }
 595
 596 define_machine(chrp) {
 597         .name                   = "CHRP",
 598         .probe                  = chrp_probe,
 599         .setup_arch             = chrp_setup_arch,
 600         .init                   = chrp_init2,
 601         .show_cpuinfo           = chrp_show_cpuinfo,
 602         .init_IRQ               = chrp_init_IRQ,
 603         .restart                = rtas_restart,
 604         .halt                   = rtas_halt,
 605         .time_init              = chrp_time_init,
 606         .set_rtc_time           = chrp_set_rtc_time,
 607         .get_rtc_time           = chrp_get_rtc_time,
 608         .calibrate_decr         = generic_calibrate_decr,
 609         .phys_mem_access_prot   = pci_phys_mem_access_prot,
 610 };