Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / arch / powerpc / platforms / embedded6xx / hlwd-pic.c
blob89c54de88b7a0f3a13ebd851d91f481fcb82d47b
1 /*
2 * arch/powerpc/platforms/embedded6xx/hlwd-pic.c
4 * Nintendo Wii "Hollywood" interrupt controller support.
5 * Copyright (C) 2009 The GameCube Linux Team
6 * Copyright (C) 2009 Albert Herranz
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
14 #define DRV_MODULE_NAME "hlwd-pic"
15 #define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <asm/io.h>
24 #include "hlwd-pic.h"
26 #define HLWD_NR_IRQS 32
29 * Each interrupt has a corresponding bit in both
30 * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
32 * Enabling/disabling an interrupt line involves asserting/clearing
33 * the corresponding bit in IMR. ACK'ing a request simply involves
34 * asserting the corresponding bit in ICR.
36 #define HW_BROADWAY_ICR 0x00
37 #define HW_BROADWAY_IMR 0x04
41 * IRQ chip hooks.
45 static void hlwd_pic_mask_and_ack(struct irq_data *d)
47 int irq = irqd_to_hwirq(d);
48 void __iomem *io_base = irq_data_get_irq_chip_data(d);
49 u32 mask = 1 << irq;
51 clrbits32(io_base + HW_BROADWAY_IMR, mask);
52 out_be32(io_base + HW_BROADWAY_ICR, mask);
55 static void hlwd_pic_ack(struct irq_data *d)
57 int irq = irqd_to_hwirq(d);
58 void __iomem *io_base = irq_data_get_irq_chip_data(d);
60 out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
63 static void hlwd_pic_mask(struct irq_data *d)
65 int irq = irqd_to_hwirq(d);
66 void __iomem *io_base = irq_data_get_irq_chip_data(d);
68 clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
71 static void hlwd_pic_unmask(struct irq_data *d)
73 int irq = irqd_to_hwirq(d);
74 void __iomem *io_base = irq_data_get_irq_chip_data(d);
76 setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
80 static struct irq_chip hlwd_pic = {
81 .name = "hlwd-pic",
82 .irq_ack = hlwd_pic_ack,
83 .irq_mask_ack = hlwd_pic_mask_and_ack,
84 .irq_mask = hlwd_pic_mask,
85 .irq_unmask = hlwd_pic_unmask,
89 * IRQ host hooks.
93 static struct irq_domain *hlwd_irq_host;
95 static int hlwd_pic_map(struct irq_domain *h, unsigned int virq,
96 irq_hw_number_t hwirq)
98 irq_set_chip_data(virq, h->host_data);
99 irq_set_status_flags(virq, IRQ_LEVEL);
100 irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
101 return 0;
104 static const struct irq_domain_ops hlwd_irq_domain_ops = {
105 .map = hlwd_pic_map,
108 static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
110 void __iomem *io_base = h->host_data;
111 int irq;
112 u32 irq_status;
114 irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
115 in_be32(io_base + HW_BROADWAY_IMR);
116 if (irq_status == 0)
117 return 0; /* no more IRQs pending */
119 irq = __ffs(irq_status);
120 return irq_linear_revmap(h, irq);
123 static void hlwd_pic_irq_cascade(struct irq_desc *desc)
125 struct irq_chip *chip = irq_desc_get_chip(desc);
126 struct irq_domain *irq_domain = irq_desc_get_handler_data(desc);
127 unsigned int virq;
129 raw_spin_lock(&desc->lock);
130 chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */
131 raw_spin_unlock(&desc->lock);
133 virq = __hlwd_pic_get_irq(irq_domain);
134 if (virq)
135 generic_handle_irq(virq);
136 else
137 pr_err("spurious interrupt!\n");
139 raw_spin_lock(&desc->lock);
140 chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
141 if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
142 chip->irq_unmask(&desc->irq_data);
143 raw_spin_unlock(&desc->lock);
147 * Platform hooks.
151 static void __hlwd_quiesce(void __iomem *io_base)
153 /* mask and ack all IRQs */
154 out_be32(io_base + HW_BROADWAY_IMR, 0);
155 out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
158 struct irq_domain *hlwd_pic_init(struct device_node *np)
160 struct irq_domain *irq_domain;
161 struct resource res;
162 void __iomem *io_base;
163 int retval;
165 retval = of_address_to_resource(np, 0, &res);
166 if (retval) {
167 pr_err("no io memory range found\n");
168 return NULL;
170 io_base = ioremap(res.start, resource_size(&res));
171 if (!io_base) {
172 pr_err("ioremap failed\n");
173 return NULL;
176 pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
178 __hlwd_quiesce(io_base);
180 irq_domain = irq_domain_add_linear(np, HLWD_NR_IRQS,
181 &hlwd_irq_domain_ops, io_base);
182 if (!irq_domain) {
183 pr_err("failed to allocate irq_domain\n");
184 iounmap(io_base);
185 return NULL;
188 return irq_domain;
191 unsigned int hlwd_pic_get_irq(void)
193 return __hlwd_pic_get_irq(hlwd_irq_host);
197 * Probe function.
201 void hlwd_pic_probe(void)
203 struct irq_domain *host;
204 struct device_node *np;
205 const u32 *interrupts;
206 int cascade_virq;
208 for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") {
209 interrupts = of_get_property(np, "interrupts", NULL);
210 if (interrupts) {
211 host = hlwd_pic_init(np);
212 BUG_ON(!host);
213 cascade_virq = irq_of_parse_and_map(np, 0);
214 irq_set_handler_data(cascade_virq, host);
215 irq_set_chained_handler(cascade_virq,
216 hlwd_pic_irq_cascade);
217 hlwd_irq_host = host;
218 break;
224 * hlwd_quiesce() - quiesce hollywood irq controller
226 * Mask and ack all interrupt sources.
229 void hlwd_quiesce(void)
231 void __iomem *io_base = hlwd_irq_host->host_data;
233 __hlwd_quiesce(io_base);