arch/powerpc/platforms/pseries/pci.c

   1 /*
   2  * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
   3  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   4  *
   5  * pSeries specific routines for PCI.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/ioport.h>
  24 #include <linux/kernel.h>
  25 #include <linux/pci.h>
  26 #include <linux/string.h>
  27
  28 #include <asm/eeh.h>
  29 #include <asm/pci-bridge.h>
  30 #include <asm/prom.h>
  31 #include <asm/ppc-pci.h>
  32 #include "pseries.h"
  33
  34 #if 0
  35 void pcibios_name_device(struct pci_dev *dev)
  36 {
  37         struct device_node *dn;
  38
  39         /*
  40          * Add IBM loc code (slot) as a prefix to the device names for service
  41          */
  42         dn = pci_device_to_OF_node(dev);
  43         if (dn) {
  44                 const char *loc_code = of_get_property(dn, "ibm,loc-code",
  45                                 NULL);
  46                 if (loc_code) {
  47                         int loc_len = strlen(loc_code);
  48                         if (loc_len < sizeof(dev->dev.name)) {
  49                                 memmove(dev->dev.name+loc_len+1, dev->dev.name,
  50                                         sizeof(dev->dev.name)-loc_len-1);
  51                                 memcpy(dev->dev.name, loc_code, loc_len);
  52                                 dev->dev.name[loc_len] = ' ';
  53                                 dev->dev.name[sizeof(dev->dev.name)-1] = '\0';
  54                         }
  55                 }
  56         }
  57 }
  58 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device);
  59 #endif
  60
  61 #ifdef CONFIG_PCI_IOV
  62 #define MAX_VFS_FOR_MAP_PE 256
  63 struct pe_map_bar_entry {
  64         __be64     bar;       /* Input:  Virtual Function BAR */
  65         __be16     rid;       /* Input:  Virtual Function Router ID */
  66         __be16     pe_num;    /* Output: Virtual Function PE Number */
  67         __be32     reserved;  /* Reserved Space */
  68 };
  69
  70 int pseries_send_map_pe(struct pci_dev *pdev,
  71                         u16 num_vfs,
  72                         struct pe_map_bar_entry *vf_pe_array)
  73 {
  74         struct pci_dn *pdn;
  75         int rc;
  76         unsigned long buid, addr;
  77         int ibm_map_pes = rtas_token("ibm,open-sriov-map-pe-number");
  78
  79         if (ibm_map_pes == RTAS_UNKNOWN_SERVICE)
  80                 return -EINVAL;
  81
  82         pdn = pci_get_pdn(pdev);
  83         addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
  84         buid = pdn->phb->buid;
  85         spin_lock(&rtas_data_buf_lock);
  86         memcpy(rtas_data_buf, vf_pe_array,
  87                RTAS_DATA_BUF_SIZE);
  88         rc = rtas_call(ibm_map_pes, 5, 1, NULL, addr,
  89                        BUID_HI(buid), BUID_LO(buid),
  90                        rtas_data_buf,
  91                        num_vfs * sizeof(struct pe_map_bar_entry));
  92         memcpy(vf_pe_array, rtas_data_buf, RTAS_DATA_BUF_SIZE);
  93         spin_unlock(&rtas_data_buf_lock);
  94
  95         if (rc)
  96                 dev_err(&pdev->dev,
  97                         "%s: Failed to associate pes PE#%lx, rc=%x\n",
  98                         __func__,  addr, rc);
  99
 100         return rc;
 101 }
 102
 103 void pseries_set_pe_num(struct pci_dev *pdev, u16 vf_index, __be16 pe_num)
 104 {
 105         struct pci_dn *pdn;
 106
 107         pdn = pci_get_pdn(pdev);
 108         pdn->pe_num_map[vf_index] = be16_to_cpu(pe_num);
 109         dev_dbg(&pdev->dev, "VF %04x:%02x:%02x.%x associated with PE#%x\n",
 110                 pci_domain_nr(pdev->bus),
 111                 pdev->bus->number,
 112                 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
 113                 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)),
 114                 pdn->pe_num_map[vf_index]);
 115 }
 116
 117 int pseries_associate_pes(struct pci_dev *pdev, u16 num_vfs)
 118 {
 119         struct pci_dn *pdn;
 120         int i, rc, vf_index;
 121         struct pe_map_bar_entry *vf_pe_array;
 122         struct resource *res;
 123         u64 size;
 124
 125         vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
 126         if (!vf_pe_array)
 127                 return -ENOMEM;
 128
 129         pdn = pci_get_pdn(pdev);
 130         /* create firmware structure to associate pes */
 131         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
 132                 pdn->pe_num_map[vf_index] = IODA_INVALID_PE;
 133                 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 134                         res = &pdev->resource[i + PCI_IOV_RESOURCES];
 135                         if (!res->parent)
 136                                 continue;
 137                         size = pcibios_iov_resource_alignment(pdev, i +
 138                                         PCI_IOV_RESOURCES);
 139                         vf_pe_array[vf_index].bar =
 140                                 cpu_to_be64(res->start + size * vf_index);
 141                         vf_pe_array[vf_index].rid =
 142                                 cpu_to_be16((pci_iov_virtfn_bus(pdev, vf_index)
 143                                             << 8) | pci_iov_virtfn_devfn(pdev,
 144                                             vf_index));
 145                         vf_pe_array[vf_index].pe_num =
 146                                 cpu_to_be16(IODA_INVALID_PE);
 147                 }
 148         }
 149
 150         rc = pseries_send_map_pe(pdev, num_vfs, vf_pe_array);
 151         /* Only zero is success */
 152         if (!rc)
 153                 for (vf_index = 0; vf_index < num_vfs; vf_index++)
 154                         pseries_set_pe_num(pdev, vf_index,
 155                                            vf_pe_array[vf_index].pe_num);
 156
 157         kfree(vf_pe_array);
 158         return rc;
 159 }
 160
 161 int pseries_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
 162 {
 163         struct pci_dn         *pdn;
 164         int                    rc;
 165         const int *max_vfs;
 166         int max_config_vfs;
 167         struct device_node *dn = pci_device_to_OF_node(pdev);
 168
 169         max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL);
 170
 171         if (!max_vfs)
 172                 return -EINVAL;
 173
 174         /* First integer stores max config */
 175         max_config_vfs = of_read_number(&max_vfs[0], 1);
 176         if (max_config_vfs < num_vfs && num_vfs > MAX_VFS_FOR_MAP_PE) {
 177                 dev_err(&pdev->dev,
 178                         "Num VFs %x > %x Configurable VFs\n",
 179                         num_vfs, (num_vfs > MAX_VFS_FOR_MAP_PE) ?
 180                         MAX_VFS_FOR_MAP_PE : max_config_vfs);
 181                 return -EINVAL;
 182         }
 183
 184         pdn = pci_get_pdn(pdev);
 185         pdn->pe_num_map = kmalloc_array(num_vfs,
 186                                         sizeof(*pdn->pe_num_map),
 187                                         GFP_KERNEL);
 188         if (!pdn->pe_num_map)
 189                 return -ENOMEM;
 190
 191         rc = pseries_associate_pes(pdev, num_vfs);
 192
 193         /* Anything other than zero is failure */
 194         if (rc) {
 195                 dev_err(&pdev->dev, "Failure to enable sriov: %x\n", rc);
 196                 kfree(pdn->pe_num_map);
 197         } else {
 198                 pci_vf_drivers_autoprobe(pdev, false);
 199         }
 200
 201         return rc;
 202 }
 203
 204 int pseries_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
 205 {
 206         /* Allocate PCI data */
 207         add_dev_pci_data(pdev);
 208         return pseries_pci_sriov_enable(pdev, num_vfs);
 209 }
 210
 211 int pseries_pcibios_sriov_disable(struct pci_dev *pdev)
 212 {
 213         struct pci_dn         *pdn;
 214
 215         pdn = pci_get_pdn(pdev);
 216         /* Releasing pe_num_map */
 217         kfree(pdn->pe_num_map);
 218         /* Release PCI data */
 219         remove_dev_pci_data(pdev);
 220         pci_vf_drivers_autoprobe(pdev, true);
 221         return 0;
 222 }
 223 #endif
 224
 225 static void __init pSeries_request_regions(void)
 226 {
 227         if (!isa_io_base)
 228                 return;
 229
 230         request_region(0x20,0x20,"pic1");
 231         request_region(0xa0,0x20,"pic2");
 232         request_region(0x00,0x20,"dma1");
 233         request_region(0x40,0x20,"timer");
 234         request_region(0x80,0x10,"dma page reg");
 235         request_region(0xc0,0x20,"dma2");
 236 }
 237
 238 void __init pSeries_final_fixup(void)
 239 {
 240         pSeries_request_regions();
 241
 242         eeh_addr_cache_build();
 243
 244 #ifdef CONFIG_PCI_IOV
 245         ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable;
 246         ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable;
 247 #endif
 248 }
 249
 250 /*
 251  * Assume the winbond 82c105 is the IDE controller on a
 252  * p610/p615/p630. We should probably be more careful in case
 253  * someone tries to plug in a similar adapter.
 254  */
 255 static void fixup_winbond_82c105(struct pci_dev* dev)
 256 {
 257         int i;
 258         unsigned int reg;
 259
 260         if (!machine_is(pseries))
 261                 return;
 262
 263         printk("Using INTC for W82c105 IDE controller.\n");
 264         pci_read_config_dword(dev, 0x40, &reg);
 265         /* Enable LEGIRQ to use INTC instead of ISA interrupts */
 266         pci_write_config_dword(dev, 0x40, reg | (1<<11));
 267
 268         for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
 269                 /* zap the 2nd function of the winbond chip */
 270                 if (dev->resource[i].flags & IORESOURCE_IO
 271                     && dev->bus->number == 0 && dev->devfn == 0x81)
 272                         dev->resource[i].flags &= ~IORESOURCE_IO;
 273                 if (dev->resource[i].start == 0 && dev->resource[i].end) {
 274                         dev->resource[i].flags = 0;
 275                         dev->resource[i].end = 0;
 276                 }
 277         }
 278 }
 279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
 280                          fixup_winbond_82c105);
 281
 282 int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 283 {
 284         struct device_node *dn, *pdn;
 285         struct pci_bus *bus;
 286         u32 pcie_link_speed_stats[2];
 287         int rc;
 288
 289         bus = bridge->bus;
 290
 291         /* Rely on the pcibios_free_controller_deferred() callback. */
 292         pci_set_host_bridge_release(bridge, pcibios_free_controller_deferred,
 293                                         (void *) pci_bus_to_host(bus));
 294
 295         dn = pcibios_get_phb_of_node(bus);
 296         if (!dn)
 297                 return 0;
 298
 299         for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
 300                 rc = of_property_read_u32_array(pdn,
 301                                 "ibm,pcie-link-speed-stats",
 302                                 &pcie_link_speed_stats[0], 2);
 303                 if (!rc)
 304                         break;
 305         }
 306
 307         of_node_put(pdn);
 308
 309         if (rc) {
 310                 pr_debug("no ibm,pcie-link-speed-stats property\n");
 311                 return 0;
 312         }
 313
 314         switch (pcie_link_speed_stats[0]) {
 315         case 0x01:
 316                 bus->max_bus_speed = PCIE_SPEED_2_5GT;
 317                 break;
 318         case 0x02:
 319                 bus->max_bus_speed = PCIE_SPEED_5_0GT;
 320                 break;
 321         case 0x04:
 322                 bus->max_bus_speed = PCIE_SPEED_8_0GT;
 323                 break;
 324         default:
 325                 bus->max_bus_speed = PCI_SPEED_UNKNOWN;
 326                 break;
 327         }
 328
 329         switch (pcie_link_speed_stats[1]) {
 330         case 0x01:
 331                 bus->cur_bus_speed = PCIE_SPEED_2_5GT;
 332                 break;
 333         case 0x02:
 334                 bus->cur_bus_speed = PCIE_SPEED_5_0GT;
 335                 break;
 336         case 0x04:
 337                 bus->cur_bus_speed = PCIE_SPEED_8_0GT;
 338                 break;
 339         default:
 340                 bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
 341                 break;
 342         }
 343
 344         return 0;
 345 }