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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / arch / powerpc / sysdev / mpic.c
blob73067805300a26338b0868292cff95c8b78f5ce1
1 /*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation being IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16 #undef DEBUG
17 #undef DEBUG_IPI
18 #undef DEBUG_IRQ
19 #undef DEBUG_LOW
20
21 #include <linux/types.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/irq.h>
25 #include <linux/smp.h>
26 #include <linux/interrupt.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/ratelimit.h>
32
33 #include <asm/ptrace.h>
34 #include <asm/signal.h>
35 #include <asm/io.h>
36 #include <asm/pgtable.h>
37 #include <asm/irq.h>
38 #include <asm/machdep.h>
39 #include <asm/mpic.h>
40 #include <asm/smp.h>
41
42 #include "mpic.h"
43
44 #ifdef DEBUG
45 #define DBG(fmt...) printk(fmt)
46 #else
47 #define DBG(fmt...)
48 #endif
49
50 struct bus_type mpic_subsys = {
51 .name = "mpic",
52 .dev_name = "mpic",
53 };
54 EXPORT_SYMBOL_GPL(mpic_subsys);
55
56 static struct mpic *mpics;
57 static struct mpic *mpic_primary;
58 static DEFINE_RAW_SPINLOCK(mpic_lock);
59
60 #ifdef CONFIG_PPC32 /* XXX for now */
61 #ifdef CONFIG_IRQ_ALL_CPUS
62 #define distribute_irqs (1)
63 #else
64 #define distribute_irqs (0)
65 #endif
66 #endif
67
68 #ifdef CONFIG_MPIC_WEIRD
69 static u32 mpic_infos[][MPIC_IDX_END] = {
70 [0] = { /* Original OpenPIC compatible MPIC */
71 MPIC_GREG_BASE,
72 MPIC_GREG_FEATURE_0,
73 MPIC_GREG_GLOBAL_CONF_0,
74 MPIC_GREG_VENDOR_ID,
75 MPIC_GREG_IPI_VECTOR_PRI_0,
76 MPIC_GREG_IPI_STRIDE,
77 MPIC_GREG_SPURIOUS,
78 MPIC_GREG_TIMER_FREQ,
79
80 MPIC_TIMER_BASE,
81 MPIC_TIMER_STRIDE,
82 MPIC_TIMER_CURRENT_CNT,
83 MPIC_TIMER_BASE_CNT,
84 MPIC_TIMER_VECTOR_PRI,
85 MPIC_TIMER_DESTINATION,
86
87 MPIC_CPU_BASE,
88 MPIC_CPU_STRIDE,
89 MPIC_CPU_IPI_DISPATCH_0,
90 MPIC_CPU_IPI_DISPATCH_STRIDE,
91 MPIC_CPU_CURRENT_TASK_PRI,
92 MPIC_CPU_WHOAMI,
93 MPIC_CPU_INTACK,
94 MPIC_CPU_EOI,
95 MPIC_CPU_MCACK,
96
97 MPIC_IRQ_BASE,
98 MPIC_IRQ_STRIDE,
99 MPIC_IRQ_VECTOR_PRI,
100 MPIC_VECPRI_VECTOR_MASK,
101 MPIC_VECPRI_POLARITY_POSITIVE,
102 MPIC_VECPRI_POLARITY_NEGATIVE,
103 MPIC_VECPRI_SENSE_LEVEL,
104 MPIC_VECPRI_SENSE_EDGE,
105 MPIC_VECPRI_POLARITY_MASK,
106 MPIC_VECPRI_SENSE_MASK,
107 MPIC_IRQ_DESTINATION
108 },
109 [1] = { /* Tsi108/109 PIC */
110 TSI108_GREG_BASE,
111 TSI108_GREG_FEATURE_0,
112 TSI108_GREG_GLOBAL_CONF_0,
113 TSI108_GREG_VENDOR_ID,
114 TSI108_GREG_IPI_VECTOR_PRI_0,
115 TSI108_GREG_IPI_STRIDE,
116 TSI108_GREG_SPURIOUS,
117 TSI108_GREG_TIMER_FREQ,
118
119 TSI108_TIMER_BASE,
120 TSI108_TIMER_STRIDE,
121 TSI108_TIMER_CURRENT_CNT,
122 TSI108_TIMER_BASE_CNT,
123 TSI108_TIMER_VECTOR_PRI,
124 TSI108_TIMER_DESTINATION,
125
126 TSI108_CPU_BASE,
127 TSI108_CPU_STRIDE,
128 TSI108_CPU_IPI_DISPATCH_0,
129 TSI108_CPU_IPI_DISPATCH_STRIDE,
130 TSI108_CPU_CURRENT_TASK_PRI,
131 TSI108_CPU_WHOAMI,
132 TSI108_CPU_INTACK,
133 TSI108_CPU_EOI,
134 TSI108_CPU_MCACK,
135
136 TSI108_IRQ_BASE,
137 TSI108_IRQ_STRIDE,
138 TSI108_IRQ_VECTOR_PRI,
139 TSI108_VECPRI_VECTOR_MASK,
140 TSI108_VECPRI_POLARITY_POSITIVE,
141 TSI108_VECPRI_POLARITY_NEGATIVE,
142 TSI108_VECPRI_SENSE_LEVEL,
143 TSI108_VECPRI_SENSE_EDGE,
144 TSI108_VECPRI_POLARITY_MASK,
145 TSI108_VECPRI_SENSE_MASK,
146 TSI108_IRQ_DESTINATION
147 },
148 };
149
150 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
151
152 #else /* CONFIG_MPIC_WEIRD */
153
154 #define MPIC_INFO(name) MPIC_##name
155
156 #endif /* CONFIG_MPIC_WEIRD */
157
158 static inline unsigned int mpic_processor_id(struct mpic *mpic)
159 {
160 unsigned int cpu = 0;
161
162 if (!(mpic->flags & MPIC_SECONDARY))
163 cpu = hard_smp_processor_id();
164
165 return cpu;
166 }
167
168 /*
169 * Register accessor functions
170 */
171
172
173 static inline u32 _mpic_read(enum mpic_reg_type type,
174 struct mpic_reg_bank *rb,
175 unsigned int reg)
176 {
177 switch(type) {
178 #ifdef CONFIG_PPC_DCR
179 case mpic_access_dcr:
180 return dcr_read(rb->dhost, reg);
181 #endif
182 case mpic_access_mmio_be:
183 return in_be32(rb->base + (reg >> 2));
184 case mpic_access_mmio_le:
185 default:
186 return in_le32(rb->base + (reg >> 2));
187 }
188 }
189
190 static inline void _mpic_write(enum mpic_reg_type type,
191 struct mpic_reg_bank *rb,
192 unsigned int reg, u32 value)
193 {
194 switch(type) {
195 #ifdef CONFIG_PPC_DCR
196 case mpic_access_dcr:
197 dcr_write(rb->dhost, reg, value);
198 break;
199 #endif
200 case mpic_access_mmio_be:
201 out_be32(rb->base + (reg >> 2), value);
202 break;
203 case mpic_access_mmio_le:
204 default:
205 out_le32(rb->base + (reg >> 2), value);
206 break;
207 }
208 }
209
210 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
211 {
212 enum mpic_reg_type type = mpic->reg_type;
213 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
214 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
215
216 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
217 type = mpic_access_mmio_be;
218 return _mpic_read(type, &mpic->gregs, offset);
219 }
220
221 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
222 {
223 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
224 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
225
226 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
227 }
228
229 static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
230 {
231 return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
232 (tm & 3) * MPIC_INFO(TIMER_STRIDE);
233 }
234
235 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
236 {
237 unsigned int offset = mpic_tm_offset(mpic, tm) +
238 MPIC_INFO(TIMER_VECTOR_PRI);
239
240 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
241 }
242
243 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
244 {
245 unsigned int offset = mpic_tm_offset(mpic, tm) +
246 MPIC_INFO(TIMER_VECTOR_PRI);
247
248 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
249 }
250
251 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
252 {
253 unsigned int cpu = mpic_processor_id(mpic);
254
255 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
256 }
257
258 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
259 {
260 unsigned int cpu = mpic_processor_id(mpic);
261
262 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
263 }
264
265 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
266 {
267 unsigned int isu = src_no >> mpic->isu_shift;
268 unsigned int idx = src_no & mpic->isu_mask;
269 unsigned int val;
270
271 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
272 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
273 #ifdef CONFIG_MPIC_BROKEN_REGREAD
274 if (reg == 0)
275 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
276 mpic->isu_reg0_shadow[src_no];
277 #endif
278 return val;
279 }
280
281 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
282 unsigned int reg, u32 value)
283 {
284 unsigned int isu = src_no >> mpic->isu_shift;
285 unsigned int idx = src_no & mpic->isu_mask;
286
287 _mpic_write(mpic->reg_type, &mpic->isus[isu],
288 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
289
290 #ifdef CONFIG_MPIC_BROKEN_REGREAD
291 if (reg == 0)
292 mpic->isu_reg0_shadow[src_no] =
293 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
294 #endif
295 }
296
297 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
298 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
299 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
300 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
301 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
302 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
303 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
304 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
305 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
306 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
307
308
309 /*
310 * Low level utility functions
311 */
312
313
314 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
315 struct mpic_reg_bank *rb, unsigned int offset,
316 unsigned int size)
317 {
318 rb->base = ioremap(phys_addr + offset, size);
319 BUG_ON(rb->base == NULL);
320 }
321
322 #ifdef CONFIG_PPC_DCR
323 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
324 unsigned int offset, unsigned int size)
325 {
326 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
327 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
328 BUG_ON(!DCR_MAP_OK(rb->dhost));
329 }
330
331 static inline void mpic_map(struct mpic *mpic,
332 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
333 unsigned int offset, unsigned int size)
334 {
335 if (mpic->flags & MPIC_USES_DCR)
336 _mpic_map_dcr(mpic, rb, offset, size);
337 else
338 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
339 }
340 #else /* CONFIG_PPC_DCR */
341 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
342 #endif /* !CONFIG_PPC_DCR */
343
344
345
346 /* Check if we have one of those nice broken MPICs with a flipped endian on
347 * reads from IPI registers
348 */
349 static void __init mpic_test_broken_ipi(struct mpic *mpic)
350 {
351 u32 r;
352
353 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
354 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
355
356 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
357 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
358 mpic->flags |= MPIC_BROKEN_IPI;
359 }
360 }
361
362 #ifdef CONFIG_MPIC_U3_HT_IRQS
363
364 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
365 * to force the edge setting on the MPIC and do the ack workaround.
366 */
367 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
368 {
369 if (source >= 128 || !mpic->fixups)
370 return 0;
371 return mpic->fixups[source].base != NULL;
372 }
373
374
375 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
376 {
377 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
378
379 if (fixup->applebase) {
380 unsigned int soff = (fixup->index >> 3) & ~3;
381 unsigned int mask = 1U << (fixup->index & 0x1f);
382 writel(mask, fixup->applebase + soff);
383 } else {
384 raw_spin_lock(&mpic->fixup_lock);
385 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
386 writel(fixup->data, fixup->base + 4);
387 raw_spin_unlock(&mpic->fixup_lock);
388 }
389 }
390
391 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
392 bool level)
393 {
394 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
395 unsigned long flags;
396 u32 tmp;
397
398 if (fixup->base == NULL)
399 return;
400
401 DBG("startup_ht_interrupt(0x%x) index: %d\n",
402 source, fixup->index);
403 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
404 /* Enable and configure */
405 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
406 tmp = readl(fixup->base + 4);
407 tmp &= ~(0x23U);
408 if (level)
409 tmp |= 0x22;
410 writel(tmp, fixup->base + 4);
411 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
412
413 #ifdef CONFIG_PM
414 /* use the lowest bit inverted to the actual HW,
415 * set if this fixup was enabled, clear otherwise */
416 mpic->save_data[source].fixup_data = tmp | 1;
417 #endif
418 }
419
420 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
421 {
422 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
423 unsigned long flags;
424 u32 tmp;
425
426 if (fixup->base == NULL)
427 return;
428
429 DBG("shutdown_ht_interrupt(0x%x)\n", source);
430
431 /* Disable */
432 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
433 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
434 tmp = readl(fixup->base + 4);
435 tmp |= 1;
436 writel(tmp, fixup->base + 4);
437 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
438
439 #ifdef CONFIG_PM
440 /* use the lowest bit inverted to the actual HW,
441 * set if this fixup was enabled, clear otherwise */
442 mpic->save_data[source].fixup_data = tmp & ~1;
443 #endif
444 }
445
446 #ifdef CONFIG_PCI_MSI
447 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
448 unsigned int devfn)
449 {
450 u8 __iomem *base;
451 u8 pos, flags;
452 u64 addr = 0;
453
454 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
455 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
456 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
457 if (id == PCI_CAP_ID_HT) {
458 id = readb(devbase + pos + 3);
459 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
460 break;
461 }
462 }
463
464 if (pos == 0)
465 return;
466
467 base = devbase + pos;
468
469 flags = readb(base + HT_MSI_FLAGS);
470 if (!(flags & HT_MSI_FLAGS_FIXED)) {
471 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
472 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
473 }
474
475 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
476 PCI_SLOT(devfn), PCI_FUNC(devfn),
477 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
478
479 if (!(flags & HT_MSI_FLAGS_ENABLE))
480 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
481 }
482 #else
483 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
484 unsigned int devfn)
485 {
486 return;
487 }
488 #endif
489
490 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
491 unsigned int devfn, u32 vdid)
492 {
493 int i, irq, n;
494 u8 __iomem *base;
495 u32 tmp;
496 u8 pos;
497
498 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
499 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
500 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
501 if (id == PCI_CAP_ID_HT) {
502 id = readb(devbase + pos + 3);
503 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
504 break;
505 }
506 }
507 if (pos == 0)
508 return;
509
510 base = devbase + pos;
511 writeb(0x01, base + 2);
512 n = (readl(base + 4) >> 16) & 0xff;
513
514 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
515 " has %d irqs\n",
516 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
517
518 for (i = 0; i <= n; i++) {
519 writeb(0x10 + 2 * i, base + 2);
520 tmp = readl(base + 4);
521 irq = (tmp >> 16) & 0xff;
522 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
523 /* mask it , will be unmasked later */
524 tmp |= 0x1;
525 writel(tmp, base + 4);
526 mpic->fixups[irq].index = i;
527 mpic->fixups[irq].base = base;
528 /* Apple HT PIC has a non-standard way of doing EOIs */
529 if ((vdid & 0xffff) == 0x106b)
530 mpic->fixups[irq].applebase = devbase + 0x60;
531 else
532 mpic->fixups[irq].applebase = NULL;
533 writeb(0x11 + 2 * i, base + 2);
534 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
535 }
536 }
537
538
539 static void __init mpic_scan_ht_pics(struct mpic *mpic)
540 {
541 unsigned int devfn;
542 u8 __iomem *cfgspace;
543
544 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
545
546 /* Allocate fixups array */
547 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
548 BUG_ON(mpic->fixups == NULL);
549
550 /* Init spinlock */
551 raw_spin_lock_init(&mpic->fixup_lock);
552
553 /* Map U3 config space. We assume all IO-APICs are on the primary bus
554 * so we only need to map 64kB.
555 */
556 cfgspace = ioremap(0xf2000000, 0x10000);
557 BUG_ON(cfgspace == NULL);
558
559 /* Now we scan all slots. We do a very quick scan, we read the header
560 * type, vendor ID and device ID only, that's plenty enough
561 */
562 for (devfn = 0; devfn < 0x100; devfn++) {
563 u8 __iomem *devbase = cfgspace + (devfn << 8);
564 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
565 u32 l = readl(devbase + PCI_VENDOR_ID);
566 u16 s;
567
568 DBG("devfn %x, l: %x\n", devfn, l);
569
570 /* If no device, skip */
571 if (l == 0xffffffff || l == 0x00000000 ||
572 l == 0x0000ffff || l == 0xffff0000)
573 goto next;
574 /* Check if is supports capability lists */
575 s = readw(devbase + PCI_STATUS);
576 if (!(s & PCI_STATUS_CAP_LIST))
577 goto next;
578
579 mpic_scan_ht_pic(mpic, devbase, devfn, l);
580 mpic_scan_ht_msi(mpic, devbase, devfn);
581
582 next:
583 /* next device, if function 0 */
584 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
585 devfn += 7;
586 }
587 }
588
589 #else /* CONFIG_MPIC_U3_HT_IRQS */
590
591 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
592 {
593 return 0;
594 }
595
596 static void __init mpic_scan_ht_pics(struct mpic *mpic)
597 {
598 }
599
600 #endif /* CONFIG_MPIC_U3_HT_IRQS */
601
602 /* Find an mpic associated with a given linux interrupt */
603 static struct mpic *mpic_find(unsigned int irq)
604 {
605 if (irq < NUM_ISA_INTERRUPTS)
606 return NULL;
607
608 return irq_get_chip_data(irq);
609 }
610
611 /* Determine if the linux irq is an IPI */
612 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
613 {
614 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
615 }
616
617 /* Determine if the linux irq is a timer */
618 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
619 {
620 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
621 }
622
623 /* Convert a cpu mask from logical to physical cpu numbers. */
624 static inline u32 mpic_physmask(u32 cpumask)
625 {
626 int i;
627 u32 mask = 0;
628
629 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
630 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
631 return mask;
632 }
633
634 #ifdef CONFIG_SMP
635 /* Get the mpic structure from the IPI number */
636 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
637 {
638 return irq_data_get_irq_chip_data(d);
639 }
640 #endif
641
642 /* Get the mpic structure from the irq number */
643 static inline struct mpic * mpic_from_irq(unsigned int irq)
644 {
645 return irq_get_chip_data(irq);
646 }
647
648 /* Get the mpic structure from the irq data */
649 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
650 {
651 return irq_data_get_irq_chip_data(d);
652 }
653
654 /* Send an EOI */
655 static inline void mpic_eoi(struct mpic *mpic)
656 {
657 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
658 }
659
660 /*
661 * Linux descriptor level callbacks
662 */
663
664
665 void mpic_unmask_irq(struct irq_data *d)
666 {
667 unsigned int loops = 100000;
668 struct mpic *mpic = mpic_from_irq_data(d);
669 unsigned int src = irqd_to_hwirq(d);
670
671 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
672
673 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
674 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
675 ~MPIC_VECPRI_MASK);
676 /* make sure mask gets to controller before we return to user */
677 do {
678 if (!loops--) {
679 printk(KERN_ERR "%s: timeout on hwirq %u\n",
680 __func__, src);
681 break;
682 }
683 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
684 }
685
686 void mpic_mask_irq(struct irq_data *d)
687 {
688 unsigned int loops = 100000;
689 struct mpic *mpic = mpic_from_irq_data(d);
690 unsigned int src = irqd_to_hwirq(d);
691
692 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
693
694 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
695 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
696 MPIC_VECPRI_MASK);
697
698 /* make sure mask gets to controller before we return to user */
699 do {
700 if (!loops--) {
701 printk(KERN_ERR "%s: timeout on hwirq %u\n",
702 __func__, src);
703 break;
704 }
705 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
706 }
707
708 void mpic_end_irq(struct irq_data *d)
709 {
710 struct mpic *mpic = mpic_from_irq_data(d);
711
712 #ifdef DEBUG_IRQ
713 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
714 #endif
715 /* We always EOI on end_irq() even for edge interrupts since that
716 * should only lower the priority, the MPIC should have properly
717 * latched another edge interrupt coming in anyway
718 */
719
720 mpic_eoi(mpic);
721 }
722
723 #ifdef CONFIG_MPIC_U3_HT_IRQS
724
725 static void mpic_unmask_ht_irq(struct irq_data *d)
726 {
727 struct mpic *mpic = mpic_from_irq_data(d);
728 unsigned int src = irqd_to_hwirq(d);
729
730 mpic_unmask_irq(d);
731
732 if (irqd_is_level_type(d))
733 mpic_ht_end_irq(mpic, src);
734 }
735
736 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
737 {
738 struct mpic *mpic = mpic_from_irq_data(d);
739 unsigned int src = irqd_to_hwirq(d);
740
741 mpic_unmask_irq(d);
742 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
743
744 return 0;
745 }
746
747 static void mpic_shutdown_ht_irq(struct irq_data *d)
748 {
749 struct mpic *mpic = mpic_from_irq_data(d);
750 unsigned int src = irqd_to_hwirq(d);
751
752 mpic_shutdown_ht_interrupt(mpic, src);
753 mpic_mask_irq(d);
754 }
755
756 static void mpic_end_ht_irq(struct irq_data *d)
757 {
758 struct mpic *mpic = mpic_from_irq_data(d);
759 unsigned int src = irqd_to_hwirq(d);
760
761 #ifdef DEBUG_IRQ
762 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
763 #endif
764 /* We always EOI on end_irq() even for edge interrupts since that
765 * should only lower the priority, the MPIC should have properly
766 * latched another edge interrupt coming in anyway
767 */
768
769 if (irqd_is_level_type(d))
770 mpic_ht_end_irq(mpic, src);
771 mpic_eoi(mpic);
772 }
773 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
774
775 #ifdef CONFIG_SMP
776
777 static void mpic_unmask_ipi(struct irq_data *d)
778 {
779 struct mpic *mpic = mpic_from_ipi(d);
780 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
781
782 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
783 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
784 }
785
786 static void mpic_mask_ipi(struct irq_data *d)
787 {
788 /* NEVER disable an IPI... that's just plain wrong! */
789 }
790
791 static void mpic_end_ipi(struct irq_data *d)
792 {
793 struct mpic *mpic = mpic_from_ipi(d);
794
795 /*
796 * IPIs are marked IRQ_PER_CPU. This has the side effect of
797 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
798 * applying to them. We EOI them late to avoid re-entering.
799 */
800 mpic_eoi(mpic);
801 }
802
803 #endif /* CONFIG_SMP */
804
805 static void mpic_unmask_tm(struct irq_data *d)
806 {
807 struct mpic *mpic = mpic_from_irq_data(d);
808 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
809
810 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
811 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
812 mpic_tm_read(src);
813 }
814
815 static void mpic_mask_tm(struct irq_data *d)
816 {
817 struct mpic *mpic = mpic_from_irq_data(d);
818 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
819
820 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
821 mpic_tm_read(src);
822 }
823
824 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
825 bool force)
826 {
827 struct mpic *mpic = mpic_from_irq_data(d);
828 unsigned int src = irqd_to_hwirq(d);
829
830 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
831 int cpuid = irq_choose_cpu(cpumask);
832
833 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
834 } else {
835 u32 mask = cpumask_bits(cpumask)[0];
836
837 mask &= cpumask_bits(cpu_online_mask)[0];
838
839 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
840 mpic_physmask(mask));
841 }
842
843 return IRQ_SET_MASK_OK;
844 }
845
846 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
847 {
848 /* Now convert sense value */
849 switch(type & IRQ_TYPE_SENSE_MASK) {
850 case IRQ_TYPE_EDGE_RISING:
851 return MPIC_INFO(VECPRI_SENSE_EDGE) |
852 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
853 case IRQ_TYPE_EDGE_FALLING:
854 case IRQ_TYPE_EDGE_BOTH:
855 return MPIC_INFO(VECPRI_SENSE_EDGE) |
856 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
857 case IRQ_TYPE_LEVEL_HIGH:
858 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
859 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
860 case IRQ_TYPE_LEVEL_LOW:
861 default:
862 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
863 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
864 }
865 }
866
867 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
868 {
869 struct mpic *mpic = mpic_from_irq_data(d);
870 unsigned int src = irqd_to_hwirq(d);
871 unsigned int vecpri, vold, vnew;
872
873 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
874 mpic, d->irq, src, flow_type);
875
876 if (src >= mpic->num_sources)
877 return -EINVAL;
878
879 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
880
881 /* We don't support "none" type */
882 if (flow_type == IRQ_TYPE_NONE)
883 flow_type = IRQ_TYPE_DEFAULT;
884
885 /* Default: read HW settings */
886 if (flow_type == IRQ_TYPE_DEFAULT) {
887 int vold_ps;
888
889 vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
890 MPIC_INFO(VECPRI_SENSE_MASK));
891
892 if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
893 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
894 flow_type = IRQ_TYPE_EDGE_RISING;
895 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
896 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
897 flow_type = IRQ_TYPE_EDGE_FALLING;
898 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
899 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
900 flow_type = IRQ_TYPE_LEVEL_HIGH;
901 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
902 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
903 flow_type = IRQ_TYPE_LEVEL_LOW;
904 else
905 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
906 }
907
908 /* Apply to irq desc */
909 irqd_set_trigger_type(d, flow_type);
910
911 /* Apply to HW */
912 if (mpic_is_ht_interrupt(mpic, src))
913 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
914 MPIC_VECPRI_SENSE_EDGE;
915 else
916 vecpri = mpic_type_to_vecpri(mpic, flow_type);
917
918 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
919 MPIC_INFO(VECPRI_SENSE_MASK));
920 vnew |= vecpri;
921 if (vold != vnew)
922 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
923
924 return IRQ_SET_MASK_OK_NOCOPY;
925 }
926
927 void mpic_set_vector(unsigned int virq, unsigned int vector)
928 {
929 struct mpic *mpic = mpic_from_irq(virq);
930 unsigned int src = virq_to_hw(virq);
931 unsigned int vecpri;
932
933 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
934 mpic, virq, src, vector);
935
936 if (src >= mpic->num_sources)
937 return;
938
939 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
940 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
941 vecpri |= vector;
942 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
943 }
944
945 static void mpic_set_destination(unsigned int virq, unsigned int cpuid)
946 {
947 struct mpic *mpic = mpic_from_irq(virq);
948 unsigned int src = virq_to_hw(virq);
949
950 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
951 mpic, virq, src, cpuid);
952
953 if (src >= mpic->num_sources)
954 return;
955
956 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
957 }
958
959 static struct irq_chip mpic_irq_chip = {
960 .irq_mask = mpic_mask_irq,
961 .irq_unmask = mpic_unmask_irq,
962 .irq_eoi = mpic_end_irq,
963 .irq_set_type = mpic_set_irq_type,
964 };
965
966 #ifdef CONFIG_SMP
967 static struct irq_chip mpic_ipi_chip = {
968 .irq_mask = mpic_mask_ipi,
969 .irq_unmask = mpic_unmask_ipi,
970 .irq_eoi = mpic_end_ipi,
971 };
972 #endif /* CONFIG_SMP */
973
974 static struct irq_chip mpic_tm_chip = {
975 .irq_mask = mpic_mask_tm,
976 .irq_unmask = mpic_unmask_tm,
977 .irq_eoi = mpic_end_irq,
978 };
979
980 #ifdef CONFIG_MPIC_U3_HT_IRQS
981 static struct irq_chip mpic_irq_ht_chip = {
982 .irq_startup = mpic_startup_ht_irq,
983 .irq_shutdown = mpic_shutdown_ht_irq,
984 .irq_mask = mpic_mask_irq,
985 .irq_unmask = mpic_unmask_ht_irq,
986 .irq_eoi = mpic_end_ht_irq,
987 .irq_set_type = mpic_set_irq_type,
988 };
989 #endif /* CONFIG_MPIC_U3_HT_IRQS */
990
991
992 static int mpic_host_match(struct irq_domain *h, struct device_node *node,
993 enum irq_domain_bus_token bus_token)
994 {
995 /* Exact match, unless mpic node is NULL */
996 struct device_node *of_node = irq_domain_get_of_node(h);
997 return of_node == NULL || of_node == node;
998 }
999
1000 static int mpic_host_map(struct irq_domain *h, unsigned int virq,
1001 irq_hw_number_t hw)
1002 {
1003 struct mpic *mpic = h->host_data;
1004 struct irq_chip *chip;
1005
1006 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1007
1008 if (hw == mpic->spurious_vec)
1009 return -EINVAL;
1010 if (mpic->protected && test_bit(hw, mpic->protected)) {
1011 pr_warn("mpic: Mapping of source 0x%x failed, source protected by firmware !\n",
1012 (unsigned int)hw);
1013 return -EPERM;
1014 }
1015
1016 #ifdef CONFIG_SMP
1017 else if (hw >= mpic->ipi_vecs[0]) {
1018 WARN_ON(mpic->flags & MPIC_SECONDARY);
1019
1020 DBG("mpic: mapping as IPI\n");
1021 irq_set_chip_data(virq, mpic);
1022 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1023 handle_percpu_irq);
1024 return 0;
1025 }
1026 #endif /* CONFIG_SMP */
1027
1028 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1029 WARN_ON(mpic->flags & MPIC_SECONDARY);
1030
1031 DBG("mpic: mapping as timer\n");
1032 irq_set_chip_data(virq, mpic);
1033 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1034 handle_fasteoi_irq);
1035 return 0;
1036 }
1037
1038 if (mpic_map_error_int(mpic, virq, hw))
1039 return 0;
1040
1041 if (hw >= mpic->num_sources) {
1042 pr_warn("mpic: Mapping of source 0x%x failed, source out of range !\n",
1043 (unsigned int)hw);
1044 return -EINVAL;
1045 }
1046
1047 mpic_msi_reserve_hwirq(mpic, hw);
1048
1049 /* Default chip */
1050 chip = &mpic->hc_irq;
1051
1052 #ifdef CONFIG_MPIC_U3_HT_IRQS
1053 /* Check for HT interrupts, override vecpri */
1054 if (mpic_is_ht_interrupt(mpic, hw))
1055 chip = &mpic->hc_ht_irq;
1056 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1057
1058 DBG("mpic: mapping to irq chip @%p\n", chip);
1059
1060 irq_set_chip_data(virq, mpic);
1061 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1062
1063 /* Set default irq type */
1064 irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1065
1066 /* If the MPIC was reset, then all vectors have already been
1067 * initialized. Otherwise, a per source lazy initialization
1068 * is done here.
1069 */
1070 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1071 int cpu;
1072
1073 preempt_disable();
1074 cpu = mpic_processor_id(mpic);
1075 preempt_enable();
1076
1077 mpic_set_vector(virq, hw);
1078 mpic_set_destination(virq, cpu);
1079 mpic_irq_set_priority(virq, 8);
1080 }
1081
1082 return 0;
1083 }
1084
1085 static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1086 const u32 *intspec, unsigned int intsize,
1087 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1088
1089 {
1090 struct mpic *mpic = h->host_data;
1091 static unsigned char map_mpic_senses[4] = {
1092 IRQ_TYPE_EDGE_RISING,
1093 IRQ_TYPE_LEVEL_LOW,
1094 IRQ_TYPE_LEVEL_HIGH,
1095 IRQ_TYPE_EDGE_FALLING,
1096 };
1097
1098 *out_hwirq = intspec[0];
1099 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1100 /*
1101 * Freescale MPIC with extended intspec:
1102 * First two cells are as usual. Third specifies
1103 * an "interrupt type". Fourth is type-specific data.
1104 *
1105 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1106 */
1107 switch (intspec[2]) {
1108 case 0:
1109 break;
1110 case 1:
1111 if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1112 break;
1113
1114 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1115 return -EINVAL;
1116
1117 *out_hwirq = mpic->err_int_vecs[intspec[3]];
1118
1119 break;
1120 case 2:
1121 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1122 return -EINVAL;
1123
1124 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1125 break;
1126 case 3:
1127 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1128 return -EINVAL;
1129
1130 *out_hwirq = mpic->timer_vecs[intspec[0]];
1131 break;
1132 default:
1133 pr_debug("%s: unknown irq type %u\n",
1134 __func__, intspec[2]);
1135 return -EINVAL;
1136 }
1137
1138 *out_flags = map_mpic_senses[intspec[1] & 3];
1139 } else if (intsize > 1) {
1140 u32 mask = 0x3;
1141
1142 /* Apple invented a new race of encoding on machines with
1143 * an HT APIC. They encode, among others, the index within
1144 * the HT APIC. We don't care about it here since thankfully,
1145 * it appears that they have the APIC already properly
1146 * configured, and thus our current fixup code that reads the
1147 * APIC config works fine. However, we still need to mask out
1148 * bits in the specifier to make sure we only get bit 0 which
1149 * is the level/edge bit (the only sense bit exposed by Apple),
1150 * as their bit 1 means something else.
1151 */
1152 if (machine_is(powermac))
1153 mask = 0x1;
1154 *out_flags = map_mpic_senses[intspec[1] & mask];
1155 } else
1156 *out_flags = IRQ_TYPE_NONE;
1157
1158 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1159 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1160
1161 return 0;
1162 }
1163
1164 /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1165 static void mpic_cascade(struct irq_desc *desc)
1166 {
1167 struct irq_chip *chip = irq_desc_get_chip(desc);
1168 struct mpic *mpic = irq_desc_get_handler_data(desc);
1169 unsigned int virq;
1170
1171 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1172
1173 virq = mpic_get_one_irq(mpic);
1174 if (virq)
1175 generic_handle_irq(virq);
1176
1177 chip->irq_eoi(&desc->irq_data);
1178 }
1179
1180 static const struct irq_domain_ops mpic_host_ops = {
1181 .match = mpic_host_match,
1182 .map = mpic_host_map,
1183 .xlate = mpic_host_xlate,
1184 };
1185
1186 static u32 fsl_mpic_get_version(struct mpic *mpic)
1187 {
1188 u32 brr1;
1189
1190 if (!(mpic->flags & MPIC_FSL))
1191 return 0;
1192
1193 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1194 MPIC_FSL_BRR1);
1195
1196 return brr1 & MPIC_FSL_BRR1_VER;
1197 }
1198
1199 /*
1200 * Exported functions
1201 */
1202
1203 u32 fsl_mpic_primary_get_version(void)
1204 {
1205 struct mpic *mpic = mpic_primary;
1206
1207 if (mpic)
1208 return fsl_mpic_get_version(mpic);
1209
1210 return 0;
1211 }
1212
1213 struct mpic * __init mpic_alloc(struct device_node *node,
1214 phys_addr_t phys_addr,
1215 unsigned int flags,
1216 unsigned int isu_size,
1217 unsigned int irq_count,
1218 const char *name)
1219 {
1220 int i, psize, intvec_top;
1221 struct mpic *mpic;
1222 u32 greg_feature;
1223 const char *vers;
1224 const u32 *psrc;
1225 u32 last_irq;
1226 u32 fsl_version = 0;
1227
1228 /* Default MPIC search parameters */
1229 static const struct of_device_id __initconst mpic_device_id[] = {
1230 { .type = "open-pic", },
1231 { .compatible = "open-pic", },
1232 {},
1233 };
1234
1235 /*
1236 * If we were not passed a device-tree node, then perform the default
1237 * search for standardized a standardized OpenPIC.
1238 */
1239 if (node) {
1240 node = of_node_get(node);
1241 } else {
1242 node = of_find_matching_node(NULL, mpic_device_id);
1243 if (!node)
1244 return NULL;
1245 }
1246
1247 /* Pick the physical address from the device tree if unspecified */
1248 if (!phys_addr) {
1249 /* Check if it is DCR-based */
1250 if (of_property_read_bool(node, "dcr-reg")) {
1251 flags |= MPIC_USES_DCR;
1252 } else {
1253 struct resource r;
1254 if (of_address_to_resource(node, 0, &r))
1255 goto err_of_node_put;
1256 phys_addr = r.start;
1257 }
1258 }
1259
1260 /* Read extra device-tree properties into the flags variable */
1261 if (of_get_property(node, "big-endian", NULL))
1262 flags |= MPIC_BIG_ENDIAN;
1263 if (of_get_property(node, "pic-no-reset", NULL))
1264 flags |= MPIC_NO_RESET;
1265 if (of_get_property(node, "single-cpu-affinity", NULL))
1266 flags |= MPIC_SINGLE_DEST_CPU;
1267 if (of_device_is_compatible(node, "fsl,mpic")) {
1268 flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1269 mpic_irq_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
1270 mpic_tm_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
1271 }
1272
1273 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1274 if (mpic == NULL)
1275 goto err_of_node_put;
1276
1277 mpic->name = name;
1278 mpic->node = node;
1279 mpic->paddr = phys_addr;
1280 mpic->flags = flags;
1281
1282 mpic->hc_irq = mpic_irq_chip;
1283 mpic->hc_irq.name = name;
1284 if (!(mpic->flags & MPIC_SECONDARY))
1285 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1286 #ifdef CONFIG_MPIC_U3_HT_IRQS
1287 mpic->hc_ht_irq = mpic_irq_ht_chip;
1288 mpic->hc_ht_irq.name = name;
1289 if (!(mpic->flags & MPIC_SECONDARY))
1290 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1291 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1292
1293 #ifdef CONFIG_SMP
1294 mpic->hc_ipi = mpic_ipi_chip;
1295 mpic->hc_ipi.name = name;
1296 #endif /* CONFIG_SMP */
1297
1298 mpic->hc_tm = mpic_tm_chip;
1299 mpic->hc_tm.name = name;
1300
1301 mpic->num_sources = 0; /* so far */
1302
1303 if (mpic->flags & MPIC_LARGE_VECTORS)
1304 intvec_top = 2047;
1305 else
1306 intvec_top = 255;
1307
1308 mpic->timer_vecs[0] = intvec_top - 12;
1309 mpic->timer_vecs[1] = intvec_top - 11;
1310 mpic->timer_vecs[2] = intvec_top - 10;
1311 mpic->timer_vecs[3] = intvec_top - 9;
1312 mpic->timer_vecs[4] = intvec_top - 8;
1313 mpic->timer_vecs[5] = intvec_top - 7;
1314 mpic->timer_vecs[6] = intvec_top - 6;
1315 mpic->timer_vecs[7] = intvec_top - 5;
1316 mpic->ipi_vecs[0] = intvec_top - 4;
1317 mpic->ipi_vecs[1] = intvec_top - 3;
1318 mpic->ipi_vecs[2] = intvec_top - 2;
1319 mpic->ipi_vecs[3] = intvec_top - 1;
1320 mpic->spurious_vec = intvec_top;
1321
1322 /* Look for protected sources */
1323 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1324 if (psrc) {
1325 /* Allocate a bitmap with one bit per interrupt */
1326 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1327 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1328 BUG_ON(mpic->protected == NULL);
1329 for (i = 0; i < psize/sizeof(u32); i++) {
1330 if (psrc[i] > intvec_top)
1331 continue;
1332 __set_bit(psrc[i], mpic->protected);
1333 }
1334 }
1335
1336 #ifdef CONFIG_MPIC_WEIRD
1337 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1338 #endif
1339
1340 /* default register type */
1341 if (mpic->flags & MPIC_BIG_ENDIAN)
1342 mpic->reg_type = mpic_access_mmio_be;
1343 else
1344 mpic->reg_type = mpic_access_mmio_le;
1345
1346 /*
1347 * An MPIC with a "dcr-reg" property must be accessed that way, but
1348 * only if the kernel includes DCR support.
1349 */
1350 #ifdef CONFIG_PPC_DCR
1351 if (mpic->flags & MPIC_USES_DCR)
1352 mpic->reg_type = mpic_access_dcr;
1353 #else
1354 BUG_ON(mpic->flags & MPIC_USES_DCR);
1355 #endif
1356
1357 /* Map the global registers */
1358 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1359 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1360
1361 if (mpic->flags & MPIC_FSL) {
1362 int ret;
1363
1364 /*
1365 * Yes, Freescale really did put global registers in the
1366 * magic per-cpu area -- and they don't even show up in the
1367 * non-magic per-cpu copies that this driver normally uses.
1368 */
1369 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1370 MPIC_CPU_THISBASE, 0x1000);
1371
1372 fsl_version = fsl_mpic_get_version(mpic);
1373
1374 /* Error interrupt mask register (EIMR) is required for
1375 * handling individual device error interrupts. EIMR
1376 * was added in MPIC version 4.1.
1377 *
1378 * Over here we reserve vector number space for error
1379 * interrupt vectors. This space is stolen from the
1380 * global vector number space, as in case of ipis
1381 * and timer interrupts.
1382 *
1383 * Available vector space = intvec_top - 12, where 12
1384 * is the number of vectors which have been consumed by
1385 * ipis and timer interrupts.
1386 */
1387 if (fsl_version >= 0x401) {
1388 ret = mpic_setup_error_int(mpic, intvec_top - 12);
1389 if (ret)
1390 return NULL;
1391 }
1392
1393 }
1394
1395 /*
1396 * EPR is only available starting with v4.0. To support
1397 * platforms that don't know the MPIC version at compile-time,
1398 * such as qemu-e500, turn off coreint if this MPIC doesn't
1399 * support it. Note that we never enable it if it wasn't
1400 * requested in the first place.
1401 *
1402 * This is done outside the MPIC_FSL check, so that we
1403 * also disable coreint if the MPIC node doesn't have
1404 * an "fsl,mpic" compatible at all. This will be the case
1405 * with device trees generated by older versions of QEMU.
1406 * fsl_version will be zero if MPIC_FSL is not set.
1407 */
1408 if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) {
1409 WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq);
1410 ppc_md.get_irq = mpic_get_irq;
1411 }
1412
1413 /* Reset */
1414
1415 /* When using a device-node, reset requests are only honored if the MPIC
1416 * is allowed to reset.
1417 */
1418 if (!(mpic->flags & MPIC_NO_RESET)) {
1419 printk(KERN_DEBUG "mpic: Resetting\n");
1420 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1421 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1422 | MPIC_GREG_GCONF_RESET);
1423 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1424 & MPIC_GREG_GCONF_RESET)
1425 mb();
1426 }
1427
1428 /* CoreInt */
1429 if (mpic->flags & MPIC_ENABLE_COREINT)
1430 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1431 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1432 | MPIC_GREG_GCONF_COREINT);
1433
1434 if (mpic->flags & MPIC_ENABLE_MCK)
1435 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1436 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1437 | MPIC_GREG_GCONF_MCK);
1438
1439 /*
1440 * The MPIC driver will crash if there are more cores than we
1441 * can initialize, so we may as well catch that problem here.
1442 */
1443 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1444
1445 /* Map the per-CPU registers */
1446 for_each_possible_cpu(i) {
1447 unsigned int cpu = get_hard_smp_processor_id(i);
1448
1449 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1450 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1451 0x1000);
1452 }
1453
1454 /*
1455 * Read feature register. For non-ISU MPICs, num sources as well. On
1456 * ISU MPICs, sources are counted as ISUs are added
1457 */
1458 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1459
1460 /*
1461 * By default, the last source number comes from the MPIC, but the
1462 * device-tree and board support code can override it on buggy hw.
1463 * If we get passed an isu_size (multi-isu MPIC) then we use that
1464 * as a default instead of the value read from the HW.
1465 */
1466 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1467 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1468 if (isu_size)
1469 last_irq = isu_size * MPIC_MAX_ISU - 1;
1470 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1471 if (irq_count)
1472 last_irq = irq_count - 1;
1473
1474 /* Initialize main ISU if none provided */
1475 if (!isu_size) {
1476 isu_size = last_irq + 1;
1477 mpic->num_sources = isu_size;
1478 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1479 MPIC_INFO(IRQ_BASE),
1480 MPIC_INFO(IRQ_STRIDE) * isu_size);
1481 }
1482
1483 mpic->isu_size = isu_size;
1484 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1485 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1486
1487 mpic->irqhost = irq_domain_add_linear(mpic->node,
1488 intvec_top,
1489 &mpic_host_ops, mpic);
1490
1491 /*
1492 * FIXME: The code leaks the MPIC object and mappings here; this
1493 * is very unlikely to fail but it ought to be fixed anyways.
1494 */
1495 if (mpic->irqhost == NULL)
1496 return NULL;
1497
1498 /* Display version */
1499 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1500 case 1:
1501 vers = "1.0";
1502 break;
1503 case 2:
1504 vers = "1.2";
1505 break;
1506 case 3:
1507 vers = "1.3";
1508 break;
1509 default:
1510 vers = "<unknown>";
1511 break;
1512 }
1513 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1514 " max %d CPUs\n",
1515 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1516 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1517 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1518
1519 mpic->next = mpics;
1520 mpics = mpic;
1521
1522 if (!(mpic->flags & MPIC_SECONDARY)) {
1523 mpic_primary = mpic;
1524 irq_set_default_host(mpic->irqhost);
1525 }
1526
1527 return mpic;
1528
1529 err_of_node_put:
1530 of_node_put(node);
1531 return NULL;
1532 }
1533
1534 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1535 phys_addr_t paddr)
1536 {
1537 unsigned int isu_first = isu_num * mpic->isu_size;
1538
1539 BUG_ON(isu_num >= MPIC_MAX_ISU);
1540
1541 mpic_map(mpic,
1542 paddr, &mpic->isus[isu_num], 0,
1543 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1544
1545 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1546 mpic->num_sources = isu_first + mpic->isu_size;
1547 }
1548
1549 void __init mpic_init(struct mpic *mpic)
1550 {
1551 int i, cpu;
1552 int num_timers = 4;
1553
1554 BUG_ON(mpic->num_sources == 0);
1555
1556 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1557
1558 /* Set current processor priority to max */
1559 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1560
1561 if (mpic->flags & MPIC_FSL) {
1562 u32 version = fsl_mpic_get_version(mpic);
1563
1564 /*
1565 * Timer group B is present at the latest in MPIC 3.1 (e.g.
1566 * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544).
1567 * I don't know about the status of intermediate versions (or
1568 * whether they even exist).
1569 */
1570 if (version >= 0x0301)
1571 num_timers = 8;
1572 }
1573
1574 /* Initialize timers to our reserved vectors and mask them for now */
1575 for (i = 0; i < num_timers; i++) {
1576 unsigned int offset = mpic_tm_offset(mpic, i);
1577
1578 mpic_write(mpic->tmregs,
1579 offset + MPIC_INFO(TIMER_DESTINATION),
1580 1 << hard_smp_processor_id());
1581 mpic_write(mpic->tmregs,
1582 offset + MPIC_INFO(TIMER_VECTOR_PRI),
1583 MPIC_VECPRI_MASK |
1584 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1585 (mpic->timer_vecs[0] + i));
1586 }
1587
1588 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1589 mpic_test_broken_ipi(mpic);
1590 for (i = 0; i < 4; i++) {
1591 mpic_ipi_write(i,
1592 MPIC_VECPRI_MASK |
1593 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1594 (mpic->ipi_vecs[0] + i));
1595 }
1596
1597 /* Do the HT PIC fixups on U3 broken mpic */
1598 DBG("MPIC flags: %x\n", mpic->flags);
1599 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1600 mpic_scan_ht_pics(mpic);
1601 mpic_u3msi_init(mpic);
1602 }
1603
1604 mpic_pasemi_msi_init(mpic);
1605
1606 cpu = mpic_processor_id(mpic);
1607
1608 if (!(mpic->flags & MPIC_NO_RESET)) {
1609 for (i = 0; i < mpic->num_sources; i++) {
1610 /* start with vector = source number, and masked */
1611 u32 vecpri = MPIC_VECPRI_MASK | i |
1612 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1613
1614 /* check if protected */
1615 if (mpic->protected && test_bit(i, mpic->protected))
1616 continue;
1617 /* init hw */
1618 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1619 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1620 }
1621 }
1622
1623 /* Init spurious vector */
1624 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1625
1626 /* Disable 8259 passthrough, if supported */
1627 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1628 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1629 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1630 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1631
1632 if (mpic->flags & MPIC_NO_BIAS)
1633 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1634 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1635 | MPIC_GREG_GCONF_NO_BIAS);
1636
1637 /* Set current processor priority to 0 */
1638 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1639
1640 #ifdef CONFIG_PM
1641 /* allocate memory to save mpic state */
1642 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1643 GFP_KERNEL);
1644 BUG_ON(mpic->save_data == NULL);
1645 #endif
1646
1647 /* Check if this MPIC is chained from a parent interrupt controller */
1648 if (mpic->flags & MPIC_SECONDARY) {
1649 int virq = irq_of_parse_and_map(mpic->node, 0);
1650 if (virq) {
1651 printk(KERN_INFO "%pOF: hooking up to IRQ %d\n",
1652 mpic->node, virq);
1653 irq_set_handler_data(virq, mpic);
1654 irq_set_chained_handler(virq, &mpic_cascade);
1655 }
1656 }
1657
1658 /* FSL mpic error interrupt initialization */
1659 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1660 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1661 }
1662
1663 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1664 {
1665 struct mpic *mpic = mpic_find(irq);
1666 unsigned int src = virq_to_hw(irq);
1667 unsigned long flags;
1668 u32 reg;
1669
1670 if (!mpic)
1671 return;
1672
1673 raw_spin_lock_irqsave(&mpic_lock, flags);
1674 if (mpic_is_ipi(mpic, src)) {
1675 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1676 ~MPIC_VECPRI_PRIORITY_MASK;
1677 mpic_ipi_write(src - mpic->ipi_vecs[0],
1678 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1679 } else if (mpic_is_tm(mpic, src)) {
1680 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1681 ~MPIC_VECPRI_PRIORITY_MASK;
1682 mpic_tm_write(src - mpic->timer_vecs[0],
1683 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1684 } else {
1685 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1686 & ~MPIC_VECPRI_PRIORITY_MASK;
1687 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1688 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1689 }
1690 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1691 }
1692
1693 void mpic_setup_this_cpu(void)
1694 {
1695 #ifdef CONFIG_SMP
1696 struct mpic *mpic = mpic_primary;
1697 unsigned long flags;
1698 u32 msk = 1 << hard_smp_processor_id();
1699 unsigned int i;
1700
1701 BUG_ON(mpic == NULL);
1702
1703 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1704
1705 raw_spin_lock_irqsave(&mpic_lock, flags);
1706
1707 /* let the mpic know we want intrs. default affinity is 0xffffffff
1708 * until changed via /proc. That's how it's done on x86. If we want
1709 * it differently, then we should make sure we also change the default
1710 * values of irq_desc[].affinity in irq.c.
1711 */
1712 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1713 for (i = 0; i < mpic->num_sources ; i++)
1714 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1715 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1716 }
1717
1718 /* Set current processor priority to 0 */
1719 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1720
1721 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1722 #endif /* CONFIG_SMP */
1723 }
1724
1725 int mpic_cpu_get_priority(void)
1726 {
1727 struct mpic *mpic = mpic_primary;
1728
1729 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1730 }
1731
1732 void mpic_cpu_set_priority(int prio)
1733 {
1734 struct mpic *mpic = mpic_primary;
1735
1736 prio &= MPIC_CPU_TASKPRI_MASK;
1737 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1738 }
1739
1740 void mpic_teardown_this_cpu(int secondary)
1741 {
1742 struct mpic *mpic = mpic_primary;
1743 unsigned long flags;
1744 u32 msk = 1 << hard_smp_processor_id();
1745 unsigned int i;
1746
1747 BUG_ON(mpic == NULL);
1748
1749 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1750 raw_spin_lock_irqsave(&mpic_lock, flags);
1751
1752 /* let the mpic know we don't want intrs. */
1753 for (i = 0; i < mpic->num_sources ; i++)
1754 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1755 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1756
1757 /* Set current processor priority to max */
1758 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1759 /* We need to EOI the IPI since not all platforms reset the MPIC
1760 * on boot and new interrupts wouldn't get delivered otherwise.
1761 */
1762 mpic_eoi(mpic);
1763
1764 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1765 }
1766
1767
1768 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1769 {
1770 u32 src;
1771
1772 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1773 #ifdef DEBUG_LOW
1774 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1775 #endif
1776 if (unlikely(src == mpic->spurious_vec)) {
1777 if (mpic->flags & MPIC_SPV_EOI)
1778 mpic_eoi(mpic);
1779 return 0;
1780 }
1781 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1782 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1783 mpic->name, (int)src);
1784 mpic_eoi(mpic);
1785 return 0;
1786 }
1787
1788 return irq_linear_revmap(mpic->irqhost, src);
1789 }
1790
1791 unsigned int mpic_get_one_irq(struct mpic *mpic)
1792 {
1793 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1794 }
1795
1796 unsigned int mpic_get_irq(void)
1797 {
1798 struct mpic *mpic = mpic_primary;
1799
1800 BUG_ON(mpic == NULL);
1801
1802 return mpic_get_one_irq(mpic);
1803 }
1804
1805 unsigned int mpic_get_coreint_irq(void)
1806 {
1807 #ifdef CONFIG_BOOKE
1808 struct mpic *mpic = mpic_primary;
1809 u32 src;
1810
1811 BUG_ON(mpic == NULL);
1812
1813 src = mfspr(SPRN_EPR);
1814
1815 if (unlikely(src == mpic->spurious_vec)) {
1816 if (mpic->flags & MPIC_SPV_EOI)
1817 mpic_eoi(mpic);
1818 return 0;
1819 }
1820 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1821 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1822 mpic->name, (int)src);
1823 return 0;
1824 }
1825
1826 return irq_linear_revmap(mpic->irqhost, src);
1827 #else
1828 return 0;
1829 #endif
1830 }
1831
1832 unsigned int mpic_get_mcirq(void)
1833 {
1834 struct mpic *mpic = mpic_primary;
1835
1836 BUG_ON(mpic == NULL);
1837
1838 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1839 }
1840
1841 #ifdef CONFIG_SMP
1842 void mpic_request_ipis(void)
1843 {
1844 struct mpic *mpic = mpic_primary;
1845 int i;
1846 BUG_ON(mpic == NULL);
1847
1848 printk(KERN_INFO "mpic: requesting IPIs...\n");
1849
1850 for (i = 0; i < 4; i++) {
1851 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1852 mpic->ipi_vecs[0] + i);
1853 if (!vipi) {
1854 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1855 continue;
1856 }
1857 smp_request_message_ipi(vipi, i);
1858 }
1859 }
1860
1861 void smp_mpic_message_pass(int cpu, int msg)
1862 {
1863 struct mpic *mpic = mpic_primary;
1864 u32 physmask;
1865
1866 BUG_ON(mpic == NULL);
1867
1868 /* make sure we're sending something that translates to an IPI */
1869 if ((unsigned int)msg > 3) {
1870 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1871 smp_processor_id(), msg);
1872 return;
1873 }
1874
1875 #ifdef DEBUG_IPI
1876 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1877 #endif
1878
1879 physmask = 1 << get_hard_smp_processor_id(cpu);
1880
1881 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1882 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1883 }
1884
1885 void __init smp_mpic_probe(void)
1886 {
1887 int nr_cpus;
1888
1889 DBG("smp_mpic_probe()...\n");
1890
1891 nr_cpus = num_possible_cpus();
1892
1893 DBG("nr_cpus: %d\n", nr_cpus);
1894
1895 if (nr_cpus > 1)
1896 mpic_request_ipis();
1897 }
1898
1899 void smp_mpic_setup_cpu(int cpu)
1900 {
1901 mpic_setup_this_cpu();
1902 }
1903
1904 void mpic_reset_core(int cpu)
1905 {
1906 struct mpic *mpic = mpic_primary;
1907 u32 pir;
1908 int cpuid = get_hard_smp_processor_id(cpu);
1909 int i;
1910
1911 /* Set target bit for core reset */
1912 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1913 pir |= (1 << cpuid);
1914 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1915 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1916
1917 /* Restore target bit after reset complete */
1918 pir &= ~(1 << cpuid);
1919 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1920 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1921
1922 /* Perform 15 EOI on each reset core to clear pending interrupts.
1923 * This is required for FSL CoreNet based devices */
1924 if (mpic->flags & MPIC_FSL) {
1925 for (i = 0; i < 15; i++) {
1926 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1927 MPIC_CPU_EOI, 0);
1928 }
1929 }
1930 }
1931 #endif /* CONFIG_SMP */
1932
1933 #ifdef CONFIG_PM
1934 static void mpic_suspend_one(struct mpic *mpic)
1935 {
1936 int i;
1937
1938 for (i = 0; i < mpic->num_sources; i++) {
1939 mpic->save_data[i].vecprio =
1940 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1941 mpic->save_data[i].dest =
1942 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1943 }
1944 }
1945
1946 static int mpic_suspend(void)
1947 {
1948 struct mpic *mpic = mpics;
1949
1950 while (mpic) {
1951 mpic_suspend_one(mpic);
1952 mpic = mpic->next;
1953 }
1954
1955 return 0;
1956 }
1957
1958 static void mpic_resume_one(struct mpic *mpic)
1959 {
1960 int i;
1961
1962 for (i = 0; i < mpic->num_sources; i++) {
1963 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1964 mpic->save_data[i].vecprio);
1965 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1966 mpic->save_data[i].dest);
1967
1968 #ifdef CONFIG_MPIC_U3_HT_IRQS
1969 if (mpic->fixups) {
1970 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1971
1972 if (fixup->base) {
1973 /* we use the lowest bit in an inverted meaning */
1974 if ((mpic->save_data[i].fixup_data & 1) == 0)
1975 continue;
1976
1977 /* Enable and configure */
1978 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1979
1980 writel(mpic->save_data[i].fixup_data & ~1,
1981 fixup->base + 4);
1982 }
1983 }
1984 #endif
1985 } /* end for loop */
1986 }
1987
1988 static void mpic_resume(void)
1989 {
1990 struct mpic *mpic = mpics;
1991
1992 while (mpic) {
1993 mpic_resume_one(mpic);
1994 mpic = mpic->next;
1995 }
1996 }
1997
1998 static struct syscore_ops mpic_syscore_ops = {
1999 .resume = mpic_resume,
2000 .suspend = mpic_suspend,
2001 };
2002
2003 static int mpic_init_sys(void)
2004 {
2005 int rc;
2006
2007 register_syscore_ops(&mpic_syscore_ops);
2008 rc = subsys_system_register(&mpic_subsys, NULL);
2009 if (rc) {
2010 unregister_syscore_ops(&mpic_syscore_ops);
2011 pr_err("mpic: Failed to register subsystem!\n");
2012 return rc;
2013 }
2014
2015 return 0;
2016 }
2017
2018 device_initcall(mpic_init_sys);
2019 #endif
CRIS linux kernel tree