arch/powerpc/sysdev/xics/xics-common.c

   1 /*
   2  * Copyright 2011 IBM Corporation.
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  *
   9  */
  10 #include <linux/types.h>
  11 #include <linux/threads.h>
  12 #include <linux/kernel.h>
  13 #include <linux/irq.h>
  14 #include <linux/debugfs.h>
  15 #include <linux/smp.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/init.h>
  19 #include <linux/cpu.h>
  20 #include <linux/of.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24
  25 #include <asm/prom.h>
  26 #include <asm/io.h>
  27 #include <asm/smp.h>
  28 #include <asm/machdep.h>
  29 #include <asm/irq.h>
  30 #include <asm/errno.h>
  31 #include <asm/rtas.h>
  32 #include <asm/xics.h>
  33 #include <asm/firmware.h>
  34
  35 /* Globals common to all ICP/ICS implementations */
  36 const struct icp_ops    *icp_ops;
  37
  38 unsigned int xics_default_server                = 0xff;
  39 unsigned int xics_default_distrib_server        = 0;
  40 unsigned int xics_interrupt_server_size         = 8;
  41
  42 DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
  43
  44 struct irq_domain *xics_host;
  45
  46 static LIST_HEAD(ics_list);
  47
  48 void xics_update_irq_servers(void)
  49 {
  50         int i, j;
  51         struct device_node *np;
  52         u32 ilen;
  53         const __be32 *ireg;
  54         u32 hcpuid;
  55
  56         /* Find the server numbers for the boot cpu. */
  57         np = of_get_cpu_node(boot_cpuid, NULL);
  58         BUG_ON(!np);
  59
  60         hcpuid = get_hard_smp_processor_id(boot_cpuid);
  61         xics_default_server = xics_default_distrib_server = hcpuid;
  62
  63         pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server);
  64
  65         ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
  66         if (!ireg) {
  67                 of_node_put(np);
  68                 return;
  69         }
  70
  71         i = ilen / sizeof(int);
  72
  73         /* Global interrupt distribution server is specified in the last
  74          * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
  75          * entry fom this property for current boot cpu id and use it as
  76          * default distribution server
  77          */
  78         for (j = 0; j < i; j += 2) {
  79                 if (be32_to_cpu(ireg[j]) == hcpuid) {
  80                         xics_default_distrib_server = be32_to_cpu(ireg[j+1]);
  81                         break;
  82                 }
  83         }
  84         pr_devel("xics: xics_default_distrib_server = 0x%x\n",
  85                  xics_default_distrib_server);
  86         of_node_put(np);
  87 }
  88
  89 /* GIQ stuff, currently only supported on RTAS setups, will have
  90  * to be sorted properly for bare metal
  91  */
  92 void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
  93 {
  94 #ifdef CONFIG_PPC_RTAS
  95         int index;
  96         int status;
  97
  98         if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
  99                 return;
 100
 101         index = (1UL << xics_interrupt_server_size) - 1 - gserver;
 102
 103         status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
 104
 105         WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
 106              GLOBAL_INTERRUPT_QUEUE, index, join, status);
 107 #endif
 108 }
 109
 110 void xics_setup_cpu(void)
 111 {
 112         icp_ops->set_priority(LOWEST_PRIORITY);
 113
 114         xics_set_cpu_giq(xics_default_distrib_server, 1);
 115 }
 116
 117 void xics_mask_unknown_vec(unsigned int vec)
 118 {
 119         struct ics *ics;
 120
 121         pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec);
 122
 123         list_for_each_entry(ics, &ics_list, link)
 124                 ics->mask_unknown(ics, vec);
 125 }
 126
 127
 128 #ifdef CONFIG_SMP
 129
 130 static void xics_request_ipi(void)
 131 {
 132         unsigned int ipi;
 133
 134         ipi = irq_create_mapping(xics_host, XICS_IPI);
 135         BUG_ON(!ipi);
 136
 137         /*
 138          * IPIs are marked IRQF_PERCPU. The handler was set in map.
 139          */
 140         BUG_ON(request_irq(ipi, icp_ops->ipi_action,
 141                            IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
 142 }
 143
 144 void __init xics_smp_probe(void)
 145 {
 146         /* Register all the IPIs */
 147         xics_request_ipi();
 148
 149         /* Setup cause_ipi callback based on which ICP is used */
 150         smp_ops->cause_ipi = icp_ops->cause_ipi;
 151 }
 152
 153 #endif /* CONFIG_SMP */
 154
 155 void xics_teardown_cpu(void)
 156 {
 157         struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr);
 158
 159         /*
 160          * we have to reset the cppr index to 0 because we're
 161          * not going to return from the IPI
 162          */
 163         os_cppr->index = 0;
 164         icp_ops->set_priority(0);
 165         icp_ops->teardown_cpu();
 166 }
 167
 168 void xics_kexec_teardown_cpu(int secondary)
 169 {
 170         xics_teardown_cpu();
 171
 172         icp_ops->flush_ipi();
 173
 174         /*
 175          * Some machines need to have at least one cpu in the GIQ,
 176          * so leave the master cpu in the group.
 177          */
 178         if (secondary)
 179                 xics_set_cpu_giq(xics_default_distrib_server, 0);
 180 }
 181
 182
 183 #ifdef CONFIG_HOTPLUG_CPU
 184
 185 /* Interrupts are disabled. */
 186 void xics_migrate_irqs_away(void)
 187 {
 188         int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
 189         unsigned int irq, virq;
 190         struct irq_desc *desc;
 191
 192         /* If we used to be the default server, move to the new "boot_cpuid" */
 193         if (hw_cpu == xics_default_server)
 194                 xics_update_irq_servers();
 195
 196         /* Reject any interrupt that was queued to us... */
 197         icp_ops->set_priority(0);
 198
 199         /* Remove ourselves from the global interrupt queue */
 200         xics_set_cpu_giq(xics_default_distrib_server, 0);
 201
 202         for_each_irq_desc(virq, desc) {
 203                 struct irq_chip *chip;
 204                 long server;
 205                 unsigned long flags;
 206                 struct ics *ics;
 207
 208                 /* We can't set affinity on ISA interrupts */
 209                 if (virq < NUM_ISA_INTERRUPTS)
 210                         continue;
 211                 /* We only need to migrate enabled IRQS */
 212                 if (!desc->action)
 213                         continue;
 214                 if (desc->irq_data.domain != xics_host)
 215                         continue;
 216                 irq = desc->irq_data.hwirq;
 217                 /* We need to get IPIs still. */
 218                 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 219                         continue;
 220                 chip = irq_desc_get_chip(desc);
 221                 if (!chip || !chip->irq_set_affinity)
 222                         continue;
 223
 224                 raw_spin_lock_irqsave(&desc->lock, flags);
 225
 226                 /* Locate interrupt server */
 227                 server = -1;
 228                 ics = irq_desc_get_chip_data(desc);
 229                 if (ics)
 230                         server = ics->get_server(ics, irq);
 231                 if (server < 0) {
 232                         printk(KERN_ERR "%s: Can't find server for irq %d\n",
 233                                __func__, irq);
 234                         goto unlock;
 235                 }
 236
 237                 /* We only support delivery to all cpus or to one cpu.
 238                  * The irq has to be migrated only in the single cpu
 239                  * case.
 240                  */
 241                 if (server != hw_cpu)
 242                         goto unlock;
 243
 244                 /* This is expected during cpu offline. */
 245                 if (cpu_online(cpu))
 246                         pr_warn("IRQ %u affinity broken off cpu %u\n",
 247                                 virq, cpu);
 248
 249                 /* Reset affinity to all cpus */
 250                 raw_spin_unlock_irqrestore(&desc->lock, flags);
 251                 irq_set_affinity(virq, cpu_all_mask);
 252                 continue;
 253 unlock:
 254                 raw_spin_unlock_irqrestore(&desc->lock, flags);
 255         }
 256
 257         /* Allow "sufficient" time to drop any inflight IRQ's */
 258         mdelay(5);
 259
 260         /*
 261          * Allow IPIs again. This is done at the very end, after migrating all
 262          * interrupts, the expectation is that we'll only get woken up by an IPI
 263          * interrupt beyond this point, but leave externals masked just to be
 264          * safe. If we're using icp-opal this may actually allow all
 265          * interrupts anyway, but that should be OK.
 266          */
 267         icp_ops->set_priority(DEFAULT_PRIORITY);
 268
 269 }
 270 #endif /* CONFIG_HOTPLUG_CPU */
 271
 272 #ifdef CONFIG_SMP
 273 /*
 274  * For the moment we only implement delivery to all cpus or one cpu.
 275  *
 276  * If the requested affinity is cpu_all_mask, we set global affinity.
 277  * If not we set it to the first cpu in the mask, even if multiple cpus
 278  * are set. This is so things like irqbalance (which set core and package
 279  * wide affinities) do the right thing.
 280  *
 281  * We need to fix this to implement support for the links
 282  */
 283 int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
 284                         unsigned int strict_check)
 285 {
 286
 287         if (!distribute_irqs)
 288                 return xics_default_server;
 289
 290         if (!cpumask_subset(cpu_possible_mask, cpumask)) {
 291                 int server = cpumask_first_and(cpu_online_mask, cpumask);
 292
 293                 if (server < nr_cpu_ids)
 294                         return get_hard_smp_processor_id(server);
 295
 296                 if (strict_check)
 297                         return -1;
 298         }
 299
 300         /*
 301          * Workaround issue with some versions of JS20 firmware that
 302          * deliver interrupts to cpus which haven't been started. This
 303          * happens when using the maxcpus= boot option.
 304          */
 305         if (cpumask_equal(cpu_online_mask, cpu_present_mask))
 306                 return xics_default_distrib_server;
 307
 308         return xics_default_server;
 309 }
 310 #endif /* CONFIG_SMP */
 311
 312 static int xics_host_match(struct irq_domain *h, struct device_node *node,
 313                            enum irq_domain_bus_token bus_token)
 314 {
 315         struct ics *ics;
 316
 317         list_for_each_entry(ics, &ics_list, link)
 318                 if (ics->host_match(ics, node))
 319                         return 1;
 320
 321         return 0;
 322 }
 323
 324 /* Dummies */
 325 static void xics_ipi_unmask(struct irq_data *d) { }
 326 static void xics_ipi_mask(struct irq_data *d) { }
 327
 328 static struct irq_chip xics_ipi_chip = {
 329         .name = "XICS",
 330         .irq_eoi = NULL, /* Patched at init time */
 331         .irq_mask = xics_ipi_mask,
 332         .irq_unmask = xics_ipi_unmask,
 333 };
 334
 335 static int xics_host_map(struct irq_domain *h, unsigned int virq,
 336                          irq_hw_number_t hw)
 337 {
 338         struct ics *ics;
 339
 340         pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
 341
 342         /*
 343          * Mark interrupts as edge sensitive by default so that resend
 344          * actually works. The device-tree parsing will turn the LSIs
 345          * back to level.
 346          */
 347         irq_clear_status_flags(virq, IRQ_LEVEL);
 348
 349         /* Don't call into ICS for IPIs */
 350         if (hw == XICS_IPI) {
 351                 irq_set_chip_and_handler(virq, &xics_ipi_chip,
 352                                          handle_percpu_irq);
 353                 return 0;
 354         }
 355
 356         /* Let the ICS setup the chip data */
 357         list_for_each_entry(ics, &ics_list, link)
 358                 if (ics->map(ics, virq) == 0)
 359                         return 0;
 360
 361         return -EINVAL;
 362 }
 363
 364 static int xics_host_xlate(struct irq_domain *h, struct device_node *ct,
 365                            const u32 *intspec, unsigned int intsize,
 366                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 367
 368 {
 369         *out_hwirq = intspec[0];
 370
 371         /*
 372          * If intsize is at least 2, we look for the type in the second cell,
 373          * we assume the LSB indicates a level interrupt.
 374          */
 375         if (intsize > 1) {
 376                 if (intspec[1] & 1)
 377                         *out_flags = IRQ_TYPE_LEVEL_LOW;
 378                 else
 379                         *out_flags = IRQ_TYPE_EDGE_RISING;
 380         } else
 381                 *out_flags = IRQ_TYPE_LEVEL_LOW;
 382
 383         return 0;
 384 }
 385
 386 int xics_set_irq_type(struct irq_data *d, unsigned int flow_type)
 387 {
 388         /*
 389          * We only support these. This has really no effect other than setting
 390          * the corresponding descriptor bits mind you but those will in turn
 391          * affect the resend function when re-enabling an edge interrupt.
 392          *
 393          * Set set the default to edge as explained in map().
 394          */
 395         if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
 396                 flow_type = IRQ_TYPE_EDGE_RISING;
 397
 398         if (flow_type != IRQ_TYPE_EDGE_RISING &&
 399             flow_type != IRQ_TYPE_LEVEL_LOW)
 400                 return -EINVAL;
 401
 402         irqd_set_trigger_type(d, flow_type);
 403
 404         return IRQ_SET_MASK_OK_NOCOPY;
 405 }
 406
 407 int xics_retrigger(struct irq_data *data)
 408 {
 409         /*
 410          * We need to push a dummy CPPR when retriggering, since the subsequent
 411          * EOI will try to pop it. Passing 0 works, as the function hard codes
 412          * the priority value anyway.
 413          */
 414         xics_push_cppr(0);
 415
 416         /* Tell the core to do a soft retrigger */
 417         return 0;
 418 }
 419
 420 static const struct irq_domain_ops xics_host_ops = {
 421         .match = xics_host_match,
 422         .map = xics_host_map,
 423         .xlate = xics_host_xlate,
 424 };
 425
 426 static void __init xics_init_host(void)
 427 {
 428         xics_host = irq_domain_add_tree(NULL, &xics_host_ops, NULL);
 429         BUG_ON(xics_host == NULL);
 430         irq_set_default_host(xics_host);
 431 }
 432
 433 void __init xics_register_ics(struct ics *ics)
 434 {
 435         list_add(&ics->link, &ics_list);
 436 }
 437
 438 static void __init xics_get_server_size(void)
 439 {
 440         struct device_node *np;
 441         const __be32 *isize;
 442
 443         /* We fetch the interrupt server size from the first ICS node
 444          * we find if any
 445          */
 446         np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics");
 447         if (!np)
 448                 return;
 449         isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
 450         if (!isize)
 451                 return;
 452         xics_interrupt_server_size = be32_to_cpu(*isize);
 453         of_node_put(np);
 454 }
 455
 456 void __init xics_init(void)
 457 {
 458         int rc = -1;
 459
 460         /* Fist locate ICP */
 461         if (firmware_has_feature(FW_FEATURE_LPAR))
 462                 rc = icp_hv_init();
 463         if (rc < 0) {
 464                 rc = icp_native_init();
 465                 if (rc == -ENODEV)
 466                     rc = icp_opal_init();
 467         }
 468         if (rc < 0) {
 469                 pr_warn("XICS: Cannot find a Presentation Controller !\n");
 470                 return;
 471         }
 472
 473         /* Copy get_irq callback over to ppc_md */
 474         ppc_md.get_irq = icp_ops->get_irq;
 475
 476         /* Patch up IPI chip EOI */
 477         xics_ipi_chip.irq_eoi = icp_ops->eoi;
 478
 479         /* Now locate ICS */
 480         rc = ics_rtas_init();
 481         if (rc < 0)
 482                 rc = ics_opal_init();
 483         if (rc < 0)
 484                 pr_warn("XICS: Cannot find a Source Controller !\n");
 485
 486         /* Initialize common bits */
 487         xics_get_server_size();
 488         xics_update_irq_servers();
 489         xics_init_host();
 490         xics_setup_cpu();
 491 }