arch/score/include/asm/scoreregs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_SCORE_SCOREREGS_H
   3 #define _ASM_SCORE_SCOREREGS_H
   4
   5 #include <linux/linkage.h>
   6
   7 /* TIMER register */
   8 #define TIME0BASE               0x96080000
   9 #define P_TIMER0_CTRL           (TIME0BASE + 0x00)
  10 #define P_TIMER0_CPP_CTRL       (TIME0BASE + 0x04)
  11 #define P_TIMER0_PRELOAD        (TIME0BASE + 0x08)
  12 #define P_TIMER0_CPP_REG        (TIME0BASE + 0x0C)
  13 #define P_TIMER0_UPCNT          (TIME0BASE + 0x10)
  14
  15 /* Timer Controller Register */
  16 /* bit 0 Timer enable */
  17 #define TMR_DISABLE     0x0000
  18 #define TMR_ENABLE      0x0001
  19
  20 /* bit 1 Interrupt enable */
  21 #define TMR_IE_DISABLE  0x0000
  22 #define TMR_IE_ENABLE   0x0002
  23
  24 /* bit 2 Output enable */
  25 #define TMR_OE_DISABLE  0x0004
  26 #define TMR_OE_ENABLE   0x0000
  27
  28 /* bit4 Up/Down counting selection */
  29 #define TMR_UD_DOWN     0x0000
  30 #define TMR_UD_UP       0x0010
  31
  32 /* bit5 Up/Down counting control selection */
  33 #define TMR_UDS_UD      0x0000
  34 #define TMR_UDS_EXTUD   0x0020
  35
  36 /* bit6 Time output mode */
  37 #define TMR_OM_TOGGLE   0x0000
  38 #define TMR_OM_PILSE    0x0040
  39
  40 /* bit 8..9 External input active edge selection */
  41 #define TMR_ES_PE       0x0000
  42 #define TMR_ES_NE       0x0100
  43 #define TMR_ES_BOTH     0x0200
  44
  45 /* bit 10..11 Operating mode */
  46 #define TMR_M_FREE      0x0000 /* free running timer mode */
  47 #define TMR_M_PERIODIC  0x0400 /* periodic timer mode */
  48 #define TMR_M_FC        0x0800 /* free running counter mode */
  49 #define TMR_M_PC        0x0c00 /* periodic counter mode */
  50
  51 #define SYSTEM_CLOCK            (27*1000000/4)          /* 27 MHz */
  52 #endif /* _ASM_SCORE_SCOREREGS_H */