arch/sh/include/asm/spinlock-cas.h

   1 /*
   2  * include/asm-sh/spinlock-cas.h
   3  *
   4  * Copyright (C) 2015 SEI
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #ifndef __ASM_SH_SPINLOCK_CAS_H
  11 #define __ASM_SH_SPINLOCK_CAS_H
  12
  13 #include <asm/barrier.h>
  14 #include <asm/processor.h>
  15
  16 static inline unsigned __sl_cas(volatile unsigned *p, unsigned old, unsigned new)
  17 {
  18         __asm__ __volatile__("cas.l %1,%0,@r0"
  19                 : "+r"(new)
  20                 : "r"(old), "z"(p)
  21                 : "t", "memory" );
  22         return new;
  23 }
  24
  25 /*
  26  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  27  */
  28
  29 #define arch_spin_is_locked(x)          ((x)->lock <= 0)
  30
  31 static inline void arch_spin_lock(arch_spinlock_t *lock)
  32 {
  33         while (!__sl_cas(&lock->lock, 1, 0));
  34 }
  35
  36 static inline void arch_spin_unlock(arch_spinlock_t *lock)
  37 {
  38         __sl_cas(&lock->lock, 0, 1);
  39 }
  40
  41 static inline int arch_spin_trylock(arch_spinlock_t *lock)
  42 {
  43         return __sl_cas(&lock->lock, 1, 0);
  44 }
  45
  46 /*
  47  * Read-write spinlocks, allowing multiple readers but only one writer.
  48  *
  49  * NOTE! it is quite common to have readers in interrupts but no interrupt
  50  * writers. For those circumstances we can "mix" irq-safe locks - any writer
  51  * needs to get a irq-safe write-lock, but readers can get non-irqsafe
  52  * read-locks.
  53  */
  54
  55 static inline void arch_read_lock(arch_rwlock_t *rw)
  56 {
  57         unsigned old;
  58         do old = rw->lock;
  59         while (!old || __sl_cas(&rw->lock, old, old-1) != old);
  60 }
  61
  62 static inline void arch_read_unlock(arch_rwlock_t *rw)
  63 {
  64         unsigned old;
  65         do old = rw->lock;
  66         while (__sl_cas(&rw->lock, old, old+1) != old);
  67 }
  68
  69 static inline void arch_write_lock(arch_rwlock_t *rw)
  70 {
  71         while (__sl_cas(&rw->lock, RW_LOCK_BIAS, 0) != RW_LOCK_BIAS);
  72 }
  73
  74 static inline void arch_write_unlock(arch_rwlock_t *rw)
  75 {
  76         __sl_cas(&rw->lock, 0, RW_LOCK_BIAS);
  77 }
  78
  79 static inline int arch_read_trylock(arch_rwlock_t *rw)
  80 {
  81         unsigned old;
  82         do old = rw->lock;
  83         while (old && __sl_cas(&rw->lock, old, old-1) != old);
  84         return !!old;
  85 }
  86
  87 static inline int arch_write_trylock(arch_rwlock_t *rw)
  88 {
  89         return __sl_cas(&rw->lock, RW_LOCK_BIAS, 0) == RW_LOCK_BIAS;
  90 }
  91
  92 #endif /* __ASM_SH_SPINLOCK_CAS_H */