arch/sh/kernel/cpu/sh2a/setup-sh7206.c

   1 /*
   2  * SH7206 Setup
   3  *
   4  *  Copyright (C) 2006  Yoshinori Sato
   5  *  Copyright (C) 2009  Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/io.h>
  17
  18 enum {
  19         UNUSED = 0,
  20
  21         /* interrupt sources */
  22         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  23         PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
  24         ADC_ADI0, ADC_ADI1,
  25
  26         DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
  27
  28         MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
  29         MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
  30         IIC3,
  31
  32         CMT0, CMT1, BSC, WDT,
  33
  34         MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
  35
  36         POE2_OEI3,
  37
  38         SCIF0, SCIF1, SCIF2, SCIF3,
  39
  40         /* interrupt groups */
  41         PINT,
  42 };
  43
  44 static struct intc_vect vectors[] __initdata = {
  45         INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  46         INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  47         INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
  48         INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
  49         INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
  50         INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
  51         INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
  52         INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
  53         INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
  54         INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
  55         INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
  56         INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
  57         INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
  58         INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
  59         INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
  60         INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
  61         INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
  62         INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
  63         INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
  64         INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
  65         INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
  66         INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
  67         INTC_IRQ(MTU0_VEF, 162),
  68         INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
  69         INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
  70         INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
  71         INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
  72         INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
  73         INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
  74         INTC_IRQ(MTU2_TCI3V, 184),
  75         INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
  76         INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
  77         INTC_IRQ(MTU2_TCI4V, 192),
  78         INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
  79         INTC_IRQ(MTU5, 198),
  80         INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
  81         INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
  82         INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
  83         INTC_IRQ(MTU2S_TCI3V, 208),
  84         INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
  85         INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
  86         INTC_IRQ(MTU2S_TCI4V, 216),
  87         INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
  88         INTC_IRQ(MTU5S, 222),
  89         INTC_IRQ(POE2_OEI3, 224),
  90         INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
  91         INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
  92         INTC_IRQ(IIC3, 232),
  93         INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
  94         INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
  95         INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
  96         INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
  97         INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
  98         INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
  99         INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
 100         INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
 101 };
 102
 103 static struct intc_group groups[] __initdata = {
 104         INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
 105                    PINT4, PINT5, PINT6, PINT7),
 106 };
 107
 108 static struct intc_prio_reg prio_registers[] __initdata = {
 109         { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 110         { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
 111         { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
 112         { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
 113         { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
 114         { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
 115         { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
 116                                               MTU1_AB, MTU1_VU } },
 117         { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
 118                                               MTU3_ABCD, MTU2_TCI3V } },
 119         { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
 120                                               MTU5, POE2_12 } },
 121         { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
 122                                               MTU4S_ABCD, MTU2S_TCI4V } },
 123         { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
 124         { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
 125 };
 126
 127 static struct intc_mask_reg mask_registers[] __initdata = {
 128         { 0xfffe0808, 0, 16, /* PINTER */
 129           { 0, 0, 0, 0, 0, 0, 0, 0,
 130             PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
 131 };
 132
 133 static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
 134                          mask_registers, prio_registers, NULL);
 135
 136 static struct plat_sci_port scif0_platform_data = {
 137         .scscr          = SCSCR_REIE,
 138         .type           = PORT_SCIF,
 139 };
 140
 141 static struct resource scif0_resources[] = {
 142         DEFINE_RES_MEM(0xfffe8000, 0x100),
 143         DEFINE_RES_IRQ(240),
 144 };
 145
 146 static struct platform_device scif0_device = {
 147         .name           = "sh-sci",
 148         .id             = 0,
 149         .resource       = scif0_resources,
 150         .num_resources  = ARRAY_SIZE(scif0_resources),
 151         .dev            = {
 152                 .platform_data  = &scif0_platform_data,
 153         },
 154 };
 155
 156 static struct plat_sci_port scif1_platform_data = {
 157         .scscr          = SCSCR_REIE,
 158         .type           = PORT_SCIF,
 159 };
 160
 161 static struct resource scif1_resources[] = {
 162         DEFINE_RES_MEM(0xfffe8800, 0x100),
 163         DEFINE_RES_IRQ(244),
 164 };
 165
 166 static struct platform_device scif1_device = {
 167         .name           = "sh-sci",
 168         .id             = 1,
 169         .resource       = scif1_resources,
 170         .num_resources  = ARRAY_SIZE(scif1_resources),
 171         .dev            = {
 172                 .platform_data  = &scif1_platform_data,
 173         },
 174 };
 175
 176 static struct plat_sci_port scif2_platform_data = {
 177         .scscr          = SCSCR_REIE,
 178         .type           = PORT_SCIF,
 179 };
 180
 181 static struct resource scif2_resources[] = {
 182         DEFINE_RES_MEM(0xfffe9000, 0x100),
 183         DEFINE_RES_IRQ(248),
 184 };
 185
 186 static struct platform_device scif2_device = {
 187         .name           = "sh-sci",
 188         .id             = 2,
 189         .resource       = scif2_resources,
 190         .num_resources  = ARRAY_SIZE(scif2_resources),
 191         .dev            = {
 192                 .platform_data  = &scif2_platform_data,
 193         },
 194 };
 195
 196 static struct plat_sci_port scif3_platform_data = {
 197         .scscr          = SCSCR_REIE,
 198         .type           = PORT_SCIF,
 199 };
 200
 201 static struct resource scif3_resources[] = {
 202         DEFINE_RES_MEM(0xfffe9800, 0x100),
 203         DEFINE_RES_IRQ(252),
 204 };
 205
 206 static struct platform_device scif3_device = {
 207         .name           = "sh-sci",
 208         .id             = 3,
 209         .resource       = scif3_resources,
 210         .num_resources  = ARRAY_SIZE(scif3_resources),
 211         .dev            = {
 212                 .platform_data  = &scif3_platform_data,
 213         },
 214 };
 215
 216 static struct sh_timer_config cmt_platform_data = {
 217         .channels_mask = 3,
 218 };
 219
 220 static struct resource cmt_resources[] = {
 221         DEFINE_RES_MEM(0xfffec000, 0x10),
 222         DEFINE_RES_IRQ(140),
 223         DEFINE_RES_IRQ(144),
 224 };
 225
 226 static struct platform_device cmt_device = {
 227         .name           = "sh-cmt-16",
 228         .id             = 0,
 229         .dev = {
 230                 .platform_data  = &cmt_platform_data,
 231         },
 232         .resource       = cmt_resources,
 233         .num_resources  = ARRAY_SIZE(cmt_resources),
 234 };
 235
 236 static struct resource mtu2_resources[] = {
 237         DEFINE_RES_MEM(0xfffe4000, 0x400),
 238         DEFINE_RES_IRQ_NAMED(156, "tgi0a"),
 239         DEFINE_RES_IRQ_NAMED(164, "tgi1a"),
 240         DEFINE_RES_IRQ_NAMED(180, "tgi2a"),
 241 };
 242
 243 static struct platform_device mtu2_device = {
 244         .name           = "sh-mtu2s",
 245         .id             = -1,
 246         .resource       = mtu2_resources,
 247         .num_resources  = ARRAY_SIZE(mtu2_resources),
 248 };
 249
 250 static struct platform_device *sh7206_devices[] __initdata = {
 251         &scif0_device,
 252         &scif1_device,
 253         &scif2_device,
 254         &scif3_device,
 255         &cmt_device,
 256         &mtu2_device,
 257 };
 258
 259 static int __init sh7206_devices_setup(void)
 260 {
 261         return platform_add_devices(sh7206_devices,
 262                                     ARRAY_SIZE(sh7206_devices));
 263 }
 264 arch_initcall(sh7206_devices_setup);
 265
 266 void __init plat_irq_setup(void)
 267 {
 268         register_intc_controller(&intc_desc);
 269 }
 270
 271 static struct platform_device *sh7206_early_devices[] __initdata = {
 272         &scif0_device,
 273         &scif1_device,
 274         &scif2_device,
 275         &scif3_device,
 276         &cmt_device,
 277         &mtu2_device,
 278 };
 279
 280 #define STBCR3 0xfffe0408
 281 #define STBCR4 0xfffe040c
 282
 283 void __init plat_early_device_setup(void)
 284 {
 285         /* enable CMT clock */
 286         __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
 287
 288         /* enable MTU2 clock */
 289         __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
 290
 291         early_platform_add_devices(sh7206_early_devices,
 292                                    ARRAY_SIZE(sh7206_early_devices));
 293 }