arch/sh/kernel/cpu/sh4a/setup-sh7343.c

   1 /*
   2  * SH7343 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/uio_driver.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/sh_intc.h>
  17 #include <asm/clock.h>
  18
  19 /* Serial */
  20 static struct plat_sci_port scif0_platform_data = {
  21         .scscr          = SCSCR_CKE1,
  22         .type           = PORT_SCIF,
  23 };
  24
  25 static struct resource scif0_resources[] = {
  26         DEFINE_RES_MEM(0xffe00000, 0x100),
  27         DEFINE_RES_IRQ(evt2irq(0xc00)),
  28 };
  29
  30 static struct platform_device scif0_device = {
  31         .name           = "sh-sci",
  32         .id             = 0,
  33         .resource       = scif0_resources,
  34         .num_resources  = ARRAY_SIZE(scif0_resources),
  35         .dev            = {
  36                 .platform_data  = &scif0_platform_data,
  37         },
  38 };
  39
  40 static struct plat_sci_port scif1_platform_data = {
  41         .scscr          = SCSCR_CKE1,
  42         .type           = PORT_SCIF,
  43 };
  44
  45 static struct resource scif1_resources[] = {
  46         DEFINE_RES_MEM(0xffe10000, 0x100),
  47         DEFINE_RES_IRQ(evt2irq(0xc20)),
  48 };
  49
  50 static struct platform_device scif1_device = {
  51         .name           = "sh-sci",
  52         .id             = 1,
  53         .resource       = scif1_resources,
  54         .num_resources  = ARRAY_SIZE(scif1_resources),
  55         .dev            = {
  56                 .platform_data  = &scif1_platform_data,
  57         },
  58 };
  59
  60 static struct plat_sci_port scif2_platform_data = {
  61         .scscr          = SCSCR_CKE1,
  62         .type           = PORT_SCIF,
  63 };
  64
  65 static struct resource scif2_resources[] = {
  66         DEFINE_RES_MEM(0xffe20000, 0x100),
  67         DEFINE_RES_IRQ(evt2irq(0xc40)),
  68 };
  69
  70 static struct platform_device scif2_device = {
  71         .name           = "sh-sci",
  72         .id             = 2,
  73         .resource       = scif2_resources,
  74         .num_resources  = ARRAY_SIZE(scif2_resources),
  75         .dev            = {
  76                 .platform_data  = &scif2_platform_data,
  77         },
  78 };
  79
  80 static struct plat_sci_port scif3_platform_data = {
  81         .scscr          = SCSCR_CKE1,
  82         .type           = PORT_SCIF,
  83 };
  84
  85 static struct resource scif3_resources[] = {
  86         DEFINE_RES_MEM(0xffe30000, 0x100),
  87         DEFINE_RES_IRQ(evt2irq(0xc60)),
  88 };
  89
  90 static struct platform_device scif3_device = {
  91         .name           = "sh-sci",
  92         .id             = 3,
  93         .resource       = scif3_resources,
  94         .num_resources  = ARRAY_SIZE(scif3_resources),
  95         .dev            = {
  96                 .platform_data  = &scif3_platform_data,
  97         },
  98 };
  99
 100 static struct resource iic0_resources[] = {
 101         [0] = {
 102                 .name   = "IIC0",
 103                 .start  = 0x04470000,
 104                 .end    = 0x04470017,
 105                 .flags  = IORESOURCE_MEM,
 106         },
 107         [1] = {
 108                 .start  = evt2irq(0xe00),
 109                 .end    = evt2irq(0xe60),
 110                 .flags  = IORESOURCE_IRQ,
 111        },
 112 };
 113
 114 static struct platform_device iic0_device = {
 115         .name           = "i2c-sh_mobile",
 116         .id             = 0, /* "i2c0" clock */
 117         .num_resources  = ARRAY_SIZE(iic0_resources),
 118         .resource       = iic0_resources,
 119 };
 120
 121 static struct resource iic1_resources[] = {
 122         [0] = {
 123                 .name   = "IIC1",
 124                 .start  = 0x04750000,
 125                 .end    = 0x04750017,
 126                 .flags  = IORESOURCE_MEM,
 127         },
 128         [1] = {
 129                 .start  = evt2irq(0x780),
 130                 .end    = evt2irq(0x7e0),
 131                 .flags  = IORESOURCE_IRQ,
 132        },
 133 };
 134
 135 static struct platform_device iic1_device = {
 136         .name           = "i2c-sh_mobile",
 137         .id             = 1, /* "i2c1" clock */
 138         .num_resources  = ARRAY_SIZE(iic1_resources),
 139         .resource       = iic1_resources,
 140 };
 141
 142 static struct uio_info vpu_platform_data = {
 143         .name = "VPU4",
 144         .version = "0",
 145         .irq = evt2irq(0x980),
 146 };
 147
 148 static struct resource vpu_resources[] = {
 149         [0] = {
 150                 .name   = "VPU",
 151                 .start  = 0xfe900000,
 152                 .end    = 0xfe9022eb,
 153                 .flags  = IORESOURCE_MEM,
 154         },
 155         [1] = {
 156                 /* place holder for contiguous memory */
 157         },
 158 };
 159
 160 static struct platform_device vpu_device = {
 161         .name           = "uio_pdrv_genirq",
 162         .id             = 0,
 163         .dev = {
 164                 .platform_data  = &vpu_platform_data,
 165         },
 166         .resource       = vpu_resources,
 167         .num_resources  = ARRAY_SIZE(vpu_resources),
 168 };
 169
 170 static struct uio_info veu_platform_data = {
 171         .name = "VEU",
 172         .version = "0",
 173         .irq = evt2irq(0x8c0),
 174 };
 175
 176 static struct resource veu_resources[] = {
 177         [0] = {
 178                 .name   = "VEU",
 179                 .start  = 0xfe920000,
 180                 .end    = 0xfe9200b7,
 181                 .flags  = IORESOURCE_MEM,
 182         },
 183         [1] = {
 184                 /* place holder for contiguous memory */
 185         },
 186 };
 187
 188 static struct platform_device veu_device = {
 189         .name           = "uio_pdrv_genirq",
 190         .id             = 1,
 191         .dev = {
 192                 .platform_data  = &veu_platform_data,
 193         },
 194         .resource       = veu_resources,
 195         .num_resources  = ARRAY_SIZE(veu_resources),
 196 };
 197
 198 static struct uio_info jpu_platform_data = {
 199         .name = "JPU",
 200         .version = "0",
 201         .irq = evt2irq(0x560),
 202 };
 203
 204 static struct resource jpu_resources[] = {
 205         [0] = {
 206                 .name   = "JPU",
 207                 .start  = 0xfea00000,
 208                 .end    = 0xfea102d3,
 209                 .flags  = IORESOURCE_MEM,
 210         },
 211         [1] = {
 212                 /* place holder for contiguous memory */
 213         },
 214 };
 215
 216 static struct platform_device jpu_device = {
 217         .name           = "uio_pdrv_genirq",
 218         .id             = 2,
 219         .dev = {
 220                 .platform_data  = &jpu_platform_data,
 221         },
 222         .resource       = jpu_resources,
 223         .num_resources  = ARRAY_SIZE(jpu_resources),
 224 };
 225
 226 static struct sh_timer_config cmt_platform_data = {
 227         .channels_mask = 0x20,
 228 };
 229
 230 static struct resource cmt_resources[] = {
 231         DEFINE_RES_MEM(0x044a0000, 0x70),
 232         DEFINE_RES_IRQ(evt2irq(0xf00)),
 233 };
 234
 235 static struct platform_device cmt_device = {
 236         .name           = "sh-cmt-32",
 237         .id             = 0,
 238         .dev = {
 239                 .platform_data  = &cmt_platform_data,
 240         },
 241         .resource       = cmt_resources,
 242         .num_resources  = ARRAY_SIZE(cmt_resources),
 243 };
 244
 245 static struct sh_timer_config tmu0_platform_data = {
 246         .channels_mask = 7,
 247 };
 248
 249 static struct resource tmu0_resources[] = {
 250         DEFINE_RES_MEM(0xffd80000, 0x2c),
 251         DEFINE_RES_IRQ(evt2irq(0x400)),
 252         DEFINE_RES_IRQ(evt2irq(0x420)),
 253         DEFINE_RES_IRQ(evt2irq(0x440)),
 254 };
 255
 256 static struct platform_device tmu0_device = {
 257         .name           = "sh-tmu",
 258         .id             = 0,
 259         .dev = {
 260                 .platform_data  = &tmu0_platform_data,
 261         },
 262         .resource       = tmu0_resources,
 263         .num_resources  = ARRAY_SIZE(tmu0_resources),
 264 };
 265
 266 static struct platform_device *sh7343_devices[] __initdata = {
 267         &scif0_device,
 268         &scif1_device,
 269         &scif2_device,
 270         &scif3_device,
 271         &cmt_device,
 272         &tmu0_device,
 273         &iic0_device,
 274         &iic1_device,
 275         &vpu_device,
 276         &veu_device,
 277         &jpu_device,
 278 };
 279
 280 static int __init sh7343_devices_setup(void)
 281 {
 282         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 283         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 284         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 285
 286         return platform_add_devices(sh7343_devices,
 287                                     ARRAY_SIZE(sh7343_devices));
 288 }
 289 arch_initcall(sh7343_devices_setup);
 290
 291 static struct platform_device *sh7343_early_devices[] __initdata = {
 292         &scif0_device,
 293         &scif1_device,
 294         &scif2_device,
 295         &scif3_device,
 296         &cmt_device,
 297         &tmu0_device,
 298 };
 299
 300 void __init plat_early_device_setup(void)
 301 {
 302         early_platform_add_devices(sh7343_early_devices,
 303                                    ARRAY_SIZE(sh7343_early_devices));
 304 }
 305
 306 enum {
 307         UNUSED = 0,
 308         ENABLED,
 309         DISABLED,
 310
 311         /* interrupt sources */
 312         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 313         DMAC0, DMAC1, DMAC2, DMAC3,
 314         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 315         MFI, VPU, TPU, Z3D4, USBI0, USBI1,
 316         MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
 317         DMAC4, DMAC5, DMAC_DADERR,
 318         KEYSC,
 319         SCIF, SCIF1, SCIF2, SCIF3,
 320         SIOF0, SIOF1, SIO,
 321         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 322         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
 323         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
 324         SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
 325         IRDA, SDHI, CMT, TSIF, SIU,
 326         TMU0, TMU1, TMU2,
 327         JPU, LCDC,
 328
 329         /* interrupt groups */
 330
 331         DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
 332 };
 333
 334 static struct intc_vect vectors[] __initdata = {
 335         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 336         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 337         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 338         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 339         INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
 340         INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
 341         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 342         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 343         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 344         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 345         INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
 346         INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
 347         INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
 348         INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
 349         INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
 350         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 351         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 352         INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
 353         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
 354         INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
 355         INTC_VECT(SIO, 0xd00),
 356         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 357         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 358         INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
 359         INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
 360         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
 361         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
 362         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 363         INTC_VECT(SIU, 0xf80),
 364         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 365         INTC_VECT(TMU2, 0x440),
 366         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 367 };
 368
 369 static struct intc_group groups[] __initdata = {
 370         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 371         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 372         INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
 373         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 374         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 375                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 376         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
 377         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
 378         INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
 379         INTC_GROUP(USB, USBI0, USBI1),
 380 };
 381
 382 static struct intc_mask_reg mask_registers[] __initdata = {
 383         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 384           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 385         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 386           { 0, 0, 0, VPU, 0, 0, 0, MFI } },
 387         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 388           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 389         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 390           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 391         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 392           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
 393         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 394           { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
 395         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 396           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
 397             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 398         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 399           { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
 400         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 401           { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
 402         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 403           { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
 404         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 405           { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
 406         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 407           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 408 };
 409
 410 static struct intc_prio_reg prio_registers[] __initdata = {
 411         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
 412         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 413         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
 414         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 415         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
 416         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
 417         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
 418         { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
 419         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
 420         { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
 421         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 422           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 423 };
 424
 425 static struct intc_sense_reg sense_registers[] __initdata = {
 426         { 0xa414001c, 16, 2, /* ICR1 */
 427           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 428 };
 429
 430 static struct intc_mask_reg ack_registers[] __initdata = {
 431         { 0xa4140024, 0, 8, /* INTREQ00 */
 432           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 433 };
 434
 435 static struct intc_desc intc_desc __initdata = {
 436         .name = "sh7343",
 437         .force_enable = ENABLED,
 438         .force_disable = DISABLED,
 439         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 440                            prio_registers, sense_registers, ack_registers),
 441 };
 442
 443 void __init plat_irq_setup(void)
 444 {
 445         register_intc_controller(&intc_desc);
 446 }