arch/sh/kernel/cpu/sh4a/setup-sh7734.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/setup-sh7734.c
   3
   4  * SH7734 Setup
   5  *
   6  * Copyright (C) 2011,2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   7  * Copyright (C) 2011,2012 Renesas Solutions Corp.
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13
  14 #include <linux/platform_device.h>
  15 #include <linux/init.h>
  16 #include <linux/serial.h>
  17 #include <linux/mm.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/serial_sci.h>
  20 #include <linux/sh_timer.h>
  21 #include <linux/io.h>
  22 #include <asm/clock.h>
  23 #include <asm/irq.h>
  24 #include <cpu/sh7734.h>
  25
  26 /* SCIF */
  27 static struct plat_sci_port scif0_platform_data = {
  28         .scscr          = SCSCR_REIE,
  29         .type           = PORT_SCIF,
  30         .regtype        = SCIx_SH4_SCIF_BRG_REGTYPE,
  31 };
  32
  33 static struct resource scif0_resources[] = {
  34         DEFINE_RES_MEM(0xffe40000, 0x100),
  35         DEFINE_RES_IRQ(evt2irq(0x8c0)),
  36 };
  37
  38 static struct platform_device scif0_device = {
  39         .name           = "sh-sci",
  40         .id             = 0,
  41         .resource       = scif0_resources,
  42         .num_resources  = ARRAY_SIZE(scif0_resources),
  43         .dev            = {
  44                 .platform_data  = &scif0_platform_data,
  45         },
  46 };
  47
  48 static struct plat_sci_port scif1_platform_data = {
  49         .scscr          = SCSCR_REIE,
  50         .type           = PORT_SCIF,
  51         .regtype        = SCIx_SH4_SCIF_BRG_REGTYPE,
  52 };
  53
  54 static struct resource scif1_resources[] = {
  55         DEFINE_RES_MEM(0xffe41000, 0x100),
  56         DEFINE_RES_IRQ(evt2irq(0x8e0)),
  57 };
  58
  59 static struct platform_device scif1_device = {
  60         .name           = "sh-sci",
  61         .id             = 1,
  62         .resource       = scif1_resources,
  63         .num_resources  = ARRAY_SIZE(scif1_resources),
  64         .dev            = {
  65                 .platform_data = &scif1_platform_data,
  66         },
  67 };
  68
  69 static struct plat_sci_port scif2_platform_data = {
  70         .scscr          = SCSCR_REIE,
  71         .type           = PORT_SCIF,
  72         .regtype        = SCIx_SH4_SCIF_BRG_REGTYPE,
  73 };
  74
  75 static struct resource scif2_resources[] = {
  76         DEFINE_RES_MEM(0xffe42000, 0x100),
  77         DEFINE_RES_IRQ(evt2irq(0x900)),
  78 };
  79
  80 static struct platform_device scif2_device = {
  81         .name           = "sh-sci",
  82         .id             = 2,
  83         .resource       = scif2_resources,
  84         .num_resources  = ARRAY_SIZE(scif2_resources),
  85         .dev            = {
  86                 .platform_data = &scif2_platform_data,
  87         },
  88 };
  89
  90 static struct plat_sci_port scif3_platform_data = {
  91         .scscr          = SCSCR_REIE | SCSCR_TOIE,
  92         .type           = PORT_SCIF,
  93         .regtype        = SCIx_SH4_SCIF_BRG_REGTYPE,
  94 };
  95
  96 static struct resource scif3_resources[] = {
  97         DEFINE_RES_MEM(0xffe43000, 0x100),
  98         DEFINE_RES_IRQ(evt2irq(0x920)),
  99 };
 100
 101 static struct platform_device scif3_device = {
 102         .name           = "sh-sci",
 103         .id             = 3,
 104         .resource       = scif3_resources,
 105         .num_resources  = ARRAY_SIZE(scif3_resources),
 106         .dev            = {
 107                 .platform_data  = &scif3_platform_data,
 108         },
 109 };
 110
 111 static struct plat_sci_port scif4_platform_data = {
 112         .scscr          = SCSCR_REIE,
 113         .type           = PORT_SCIF,
 114         .regtype        = SCIx_SH4_SCIF_BRG_REGTYPE,
 115 };
 116
 117 static struct resource scif4_resources[] = {
 118         DEFINE_RES_MEM(0xffe44000, 0x100),
 119         DEFINE_RES_IRQ(evt2irq(0x940)),
 120 };
 121
 122 static struct platform_device scif4_device = {
 123         .name           = "sh-sci",
 124         .id             = 4,
 125         .resource       = scif4_resources,
 126         .num_resources  = ARRAY_SIZE(scif4_resources),
 127         .dev            = {
 128                 .platform_data  = &scif4_platform_data,
 129         },
 130 };
 131
 132 static struct plat_sci_port scif5_platform_data = {
 133         .scscr          = SCSCR_REIE,
 134         .type           = PORT_SCIF,
 135         .regtype        = SCIx_SH4_SCIF_BRG_REGTYPE,
 136 };
 137
 138 static struct resource scif5_resources[] = {
 139         DEFINE_RES_MEM(0xffe43000, 0x100),
 140         DEFINE_RES_IRQ(evt2irq(0x960)),
 141 };
 142
 143 static struct platform_device scif5_device = {
 144         .name           = "sh-sci",
 145         .id             = 5,
 146         .resource       = scif5_resources,
 147         .num_resources  = ARRAY_SIZE(scif5_resources),
 148         .dev            = {
 149                 .platform_data  = &scif5_platform_data,
 150         },
 151 };
 152
 153 /* RTC */
 154 static struct resource rtc_resources[] = {
 155         [0] = {
 156                 .name   = "rtc",
 157                 .start  = 0xFFFC5000,
 158                 .end    = 0xFFFC5000 + 0x26 - 1,
 159                 .flags  = IORESOURCE_IO,
 160         },
 161         [1] = {
 162                 .start  = evt2irq(0xC00),
 163                 .flags  = IORESOURCE_IRQ,
 164         },
 165 };
 166
 167 static struct platform_device rtc_device = {
 168         .name           = "sh-rtc",
 169         .id             = -1,
 170         .num_resources  = ARRAY_SIZE(rtc_resources),
 171         .resource       = rtc_resources,
 172 };
 173
 174 /* I2C 0 */
 175 static struct resource i2c0_resources[] = {
 176         [0] = {
 177                 .name   = "IIC0",
 178                 .start  = 0xFFC70000,
 179                 .end    = 0xFFC7000A - 1,
 180                 .flags  = IORESOURCE_MEM,
 181         },
 182         [1] = {
 183                 .start  = evt2irq(0x860),
 184                 .flags  = IORESOURCE_IRQ,
 185         },
 186 };
 187
 188 static struct platform_device i2c0_device = {
 189         .name           = "i2c-sh7734",
 190         .id             = 0,
 191         .num_resources  = ARRAY_SIZE(i2c0_resources),
 192         .resource       = i2c0_resources,
 193 };
 194
 195 /* TMU */
 196 static struct sh_timer_config tmu0_platform_data = {
 197         .channels_mask = 7,
 198 };
 199
 200 static struct resource tmu0_resources[] = {
 201         DEFINE_RES_MEM(0xffd80000, 0x30),
 202         DEFINE_RES_IRQ(evt2irq(0x400)),
 203         DEFINE_RES_IRQ(evt2irq(0x420)),
 204         DEFINE_RES_IRQ(evt2irq(0x440)),
 205 };
 206
 207 static struct platform_device tmu0_device = {
 208         .name           = "sh-tmu",
 209         .id             = 0,
 210         .dev = {
 211                 .platform_data  = &tmu0_platform_data,
 212         },
 213         .resource       = tmu0_resources,
 214         .num_resources  = ARRAY_SIZE(tmu0_resources),
 215 };
 216
 217 static struct sh_timer_config tmu1_platform_data = {
 218         .channels_mask = 7,
 219 };
 220
 221 static struct resource tmu1_resources[] = {
 222         DEFINE_RES_MEM(0xffd81000, 0x30),
 223         DEFINE_RES_IRQ(evt2irq(0x480)),
 224         DEFINE_RES_IRQ(evt2irq(0x4a0)),
 225         DEFINE_RES_IRQ(evt2irq(0x4c0)),
 226 };
 227
 228 static struct platform_device tmu1_device = {
 229         .name           = "sh-tmu",
 230         .id             = 1,
 231         .dev = {
 232                 .platform_data  = &tmu1_platform_data,
 233         },
 234         .resource       = tmu1_resources,
 235         .num_resources  = ARRAY_SIZE(tmu1_resources),
 236 };
 237
 238 static struct sh_timer_config tmu2_platform_data = {
 239         .channels_mask = 7,
 240 };
 241
 242 static struct resource tmu2_resources[] = {
 243         DEFINE_RES_MEM(0xffd82000, 0x30),
 244         DEFINE_RES_IRQ(evt2irq(0x500)),
 245         DEFINE_RES_IRQ(evt2irq(0x520)),
 246         DEFINE_RES_IRQ(evt2irq(0x540)),
 247 };
 248
 249 static struct platform_device tmu2_device = {
 250         .name           = "sh-tmu",
 251         .id             = 2,
 252         .dev = {
 253                 .platform_data  = &tmu2_platform_data,
 254         },
 255         .resource       = tmu2_resources,
 256         .num_resources  = ARRAY_SIZE(tmu2_resources),
 257 };
 258
 259 static struct platform_device *sh7734_devices[] __initdata = {
 260         &scif0_device,
 261         &scif1_device,
 262         &scif2_device,
 263         &scif3_device,
 264         &scif4_device,
 265         &scif5_device,
 266         &tmu0_device,
 267         &tmu1_device,
 268         &tmu2_device,
 269         &rtc_device,
 270 };
 271
 272 static struct platform_device *sh7734_early_devices[] __initdata = {
 273         &scif0_device,
 274         &scif1_device,
 275         &scif2_device,
 276         &scif3_device,
 277         &scif4_device,
 278         &scif5_device,
 279         &tmu0_device,
 280         &tmu1_device,
 281         &tmu2_device,
 282 };
 283
 284 void __init plat_early_device_setup(void)
 285 {
 286         early_platform_add_devices(sh7734_early_devices,
 287                 ARRAY_SIZE(sh7734_early_devices));
 288 }
 289
 290 #define GROUP 0
 291 enum {
 292         UNUSED = 0,
 293
 294         /* interrupt sources */
 295
 296         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 297         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 298         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 299         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 300
 301         IRQ0, IRQ1, IRQ2, IRQ3,
 302         DU,
 303         TMU00, TMU10, TMU20, TMU21,
 304         TMU30, TMU40, TMU50, TMU51,
 305         TMU60, TMU70, TMU80,
 306         RESET_WDT,
 307         USB,
 308         HUDI,
 309         SHDMAC,
 310         SSI0, SSI1,     SSI2, SSI3,
 311         VIN0,
 312         RGPVG,
 313         _2DG,
 314         MMC,
 315         HSPI,
 316         LBSCATA,
 317         I2C0,
 318         RCAN0,
 319         MIMLB,
 320         SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
 321         LBSCDMAC0, LBSCDMAC1, LBSCDMAC2,
 322         RCAN1,
 323         SDHI0, SDHI1,
 324         IEBUS,
 325         HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22, HPBDMAC23_25_27_28,
 326         RTC,
 327         VIN1,
 328         LCDC,
 329         SRC0, SRC1,
 330         GETHER,
 331         SDHI2,
 332         GPIO0_3, GPIO4_5,
 333         STIF0, STIF1,
 334         ADMAC,
 335         HIF,
 336         FLCTL,
 337         ADC,
 338         MTU2,
 339         RSPI,
 340         QSPI,
 341         HSCIF,
 342         VEU3F_VE3,
 343
 344         /* Group */
 345         /* Mask */
 346         STIF_M,
 347         GPIO_M,
 348         HPBDMAC_M,
 349         LBSCDMAC_M,
 350         RCAN_M,
 351         SRC_M,
 352         SCIF_M,
 353         LCDC_M,
 354         _2DG_M,
 355         VIN_M,
 356         TMU_3_M,
 357         TMU_0_M,
 358
 359         /* Priority */
 360         RCAN_P,
 361         LBSCDMAC_P,
 362
 363         /* Common */
 364         SDHI,
 365         SSI,
 366         SPI,
 367 };
 368
 369 static struct intc_vect vectors[] __initdata = {
 370         INTC_VECT(DU, 0x3E0),
 371         INTC_VECT(TMU00, 0x400),
 372         INTC_VECT(TMU10, 0x420),
 373         INTC_VECT(TMU20, 0x440),
 374         INTC_VECT(TMU30, 0x480),
 375         INTC_VECT(TMU40, 0x4A0),
 376         INTC_VECT(TMU50, 0x4C0),
 377         INTC_VECT(TMU51, 0x4E0),
 378         INTC_VECT(TMU60, 0x500),
 379         INTC_VECT(TMU70, 0x520),
 380         INTC_VECT(TMU80, 0x540),
 381         INTC_VECT(RESET_WDT, 0x560),
 382         INTC_VECT(USB, 0x580),
 383         INTC_VECT(HUDI, 0x600),
 384         INTC_VECT(SHDMAC, 0x620),
 385         INTC_VECT(SSI0, 0x6C0),
 386         INTC_VECT(SSI1, 0x6E0),
 387         INTC_VECT(SSI2, 0x700),
 388         INTC_VECT(SSI3, 0x720),
 389         INTC_VECT(VIN0, 0x740),
 390         INTC_VECT(RGPVG, 0x760),
 391         INTC_VECT(_2DG, 0x780),
 392         INTC_VECT(MMC, 0x7A0),
 393         INTC_VECT(HSPI, 0x7E0),
 394         INTC_VECT(LBSCATA, 0x840),
 395         INTC_VECT(I2C0, 0x860),
 396         INTC_VECT(RCAN0, 0x880),
 397         INTC_VECT(SCIF0, 0x8A0),
 398         INTC_VECT(SCIF1, 0x8C0),
 399         INTC_VECT(SCIF2, 0x900),
 400         INTC_VECT(SCIF3, 0x920),
 401         INTC_VECT(SCIF4, 0x940),
 402         INTC_VECT(SCIF5, 0x960),
 403         INTC_VECT(LBSCDMAC0, 0x9E0),
 404         INTC_VECT(LBSCDMAC1, 0xA00),
 405         INTC_VECT(LBSCDMAC2, 0xA20),
 406         INTC_VECT(RCAN1, 0xA60),
 407         INTC_VECT(SDHI0, 0xAE0),
 408         INTC_VECT(SDHI1, 0xB00),
 409         INTC_VECT(IEBUS, 0xB20),
 410         INTC_VECT(HPBDMAC0_3, 0xB60),
 411         INTC_VECT(HPBDMAC4_10, 0xB80),
 412         INTC_VECT(HPBDMAC11_18, 0xBA0),
 413         INTC_VECT(HPBDMAC19_22, 0xBC0),
 414         INTC_VECT(HPBDMAC23_25_27_28, 0xBE0),
 415         INTC_VECT(RTC, 0xC00),
 416         INTC_VECT(VIN1, 0xC20),
 417         INTC_VECT(LCDC, 0xC40),
 418         INTC_VECT(SRC0, 0xC60),
 419         INTC_VECT(SRC1, 0xC80),
 420         INTC_VECT(GETHER, 0xCA0),
 421         INTC_VECT(SDHI2, 0xCC0),
 422         INTC_VECT(GPIO0_3, 0xCE0),
 423         INTC_VECT(GPIO4_5, 0xD00),
 424         INTC_VECT(STIF0, 0xD20),
 425         INTC_VECT(STIF1, 0xD40),
 426         INTC_VECT(ADMAC, 0xDA0),
 427         INTC_VECT(HIF, 0xDC0),
 428         INTC_VECT(FLCTL, 0xDE0),
 429         INTC_VECT(ADC, 0xE00),
 430         INTC_VECT(MTU2, 0xE20),
 431         INTC_VECT(RSPI, 0xE40),
 432         INTC_VECT(QSPI, 0xE60),
 433         INTC_VECT(HSCIF, 0xFC0),
 434         INTC_VECT(VEU3F_VE3, 0xF40),
 435 };
 436
 437 static struct intc_group groups[] __initdata = {
 438         /* Common */
 439         INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2),
 440         INTC_GROUP(SPI, HSPI, RSPI, QSPI),
 441         INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3),
 442
 443         /* Mask group */
 444         INTC_GROUP(STIF_M, STIF0, STIF1), /* 22 */
 445         INTC_GROUP(GPIO_M, GPIO0_3, GPIO4_5), /* 21 */
 446         INTC_GROUP(HPBDMAC_M, HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18,
 447                         HPBDMAC19_22, HPBDMAC23_25_27_28), /* 19 */
 448         INTC_GROUP(LBSCDMAC_M, LBSCDMAC0, LBSCDMAC1, LBSCDMAC2), /* 18 */
 449         INTC_GROUP(RCAN_M, RCAN0, RCAN1, IEBUS), /* 17 */
 450         INTC_GROUP(SRC_M, SRC0, SRC1), /* 16 */
 451         INTC_GROUP(SCIF_M, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
 452                         HSCIF), /* 14 */
 453         INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */
 454         INTC_GROUP(_2DG_M, _2DG, RGPVG), /* 12 */
 455         INTC_GROUP(VIN_M, VIN0, VIN1), /* 10 */
 456         INTC_GROUP(TMU_3_M, TMU30, TMU40, TMU50, TMU51,
 457                         TMU60, TMU60, TMU70, TMU80), /* 2 */
 458         INTC_GROUP(TMU_0_M, TMU00, TMU10, TMU20, TMU21), /* 1 */
 459
 460         /* Priority group*/
 461         INTC_GROUP(RCAN_P, RCAN0, RCAN1), /* INT2PRI5 */
 462         INTC_GROUP(LBSCDMAC_P, LBSCDMAC0, LBSCDMAC1), /* INT2PRI5 */
 463 };
 464
 465 static struct intc_mask_reg mask_registers[] __initdata = {
 466         { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */
 467           { 0,
 468                 VEU3F_VE3,
 469                 SDHI, /* SDHI 0-2 */
 470                 ADMAC,
 471                 FLCTL,
 472                 RESET_WDT,
 473                 HIF,
 474                 ADC,
 475                 MTU2,
 476                 STIF_M, /* STIF 0,1 */
 477                 GPIO_M, /* GPIO 0-5*/
 478                 GETHER,
 479                 HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */
 480                 LBSCDMAC_M, /* LBSCDMAC 0 - 2 */
 481                 RCAN_M, /* RCAN, IEBUS */
 482                 SRC_M,  /* SRC 0,1 */
 483                 LBSCATA,
 484                 SCIF_M, /* SCIF 0-5, HSCIF */
 485                 LCDC_M, /* LCDC, MIMLB */
 486                 _2DG_M, /* 2DG, RGPVG */
 487                 SPI, /* HSPI, RSPI, QSPI */
 488                 VIN_M,  /* VIN0, 1 */
 489                 SSI,    /* SSI 0-3 */
 490                 USB,
 491                 SHDMAC,
 492                 HUDI,
 493                 MMC,
 494                 RTC,
 495                 I2C0, /* I2C */ /* I2C 0, 1*/
 496                 TMU_3_M, /* TMU30 - TMU80 */
 497                 TMU_0_M, /* TMU00 - TMU21 */
 498                 DU } },
 499 };
 500
 501 static struct intc_prio_reg prio_registers[] __initdata = {
 502         { 0xFF804000, 0, 32, 8, /* INT2PRI0 */
 503                 { DU, TMU00, TMU10, TMU20 } },
 504         { 0xFF804004, 0, 32, 8, /* INT2PRI1 */
 505                 { TMU30, TMU60, RTC, SDHI } },
 506         { 0xFF804008, 0, 32, 8, /* INT2PRI2 */
 507                 { HUDI, SHDMAC, USB, SSI } },
 508         { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */
 509                 { VIN0, SPI, _2DG, LBSCATA } },
 510         { 0xFF804010, 0, 32, 8, /* INT2PRI4 */
 511                 { SCIF0, SCIF3, HSCIF, LCDC } },
 512         { 0xFF804014, 0, 32, 8, /* INT2PRI5 */
 513                 { RCAN_P, LBSCDMAC_P, LBSCDMAC2, MMC } },
 514         { 0xFF804018, 0, 32, 8, /* INT2PRI6 */
 515                 { HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22 } },
 516         { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */
 517                 { HPBDMAC23_25_27_28, I2C0, SRC0, SRC1 } },
 518         { 0xFF804020, 0, 32, 8, /* INT2PRI8 */
 519                 { 0 /* ADIF */, VIN1, RESET_WDT, HIF } },
 520         { 0xFF804024, 0, 32, 8, /* INT2PRI9 */
 521                 { ADMAC, FLCTL, GPIO0_3, GPIO4_5 } },
 522         { 0xFF804028, 0, 32, 8, /* INT2PRI10 */
 523                 { STIF0, STIF1, VEU3F_VE3, GETHER } },
 524         { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */
 525                 { MTU2, RGPVG, MIMLB, IEBUS } },
 526 };
 527
 528 static DECLARE_INTC_DESC(intc_desc, "sh7734", vectors, groups,
 529         mask_registers, prio_registers, NULL);
 530
 531 /* Support for external interrupt pins in IRQ mode */
 532
 533 static struct intc_vect irq3210_vectors[] __initdata = {
 534         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 535         INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300),
 536 };
 537
 538 static struct intc_sense_reg irq3210_sense_registers[] __initdata = {
 539         { 0xFF80201C, 32, 2, /* ICR1 */
 540         { IRQ0, IRQ1, IRQ2, IRQ3, } },
 541 };
 542
 543 static struct intc_mask_reg irq3210_ack_registers[] __initdata = {
 544         { 0xFF802024, 0, 32, /* INTREQ */
 545         { IRQ0, IRQ1, IRQ2, IRQ3, } },
 546 };
 547
 548 static struct intc_mask_reg irq3210_mask_registers[] __initdata = {
 549         { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */
 550         { IRQ0, IRQ1, IRQ2, IRQ3, } },
 551 };
 552
 553 static struct intc_prio_reg irq3210_prio_registers[] __initdata = {
 554         { 0xFF802010, 0, 32, 4, /* INTPRI */
 555         { IRQ0, IRQ1, IRQ2, IRQ3, } },
 556 };
 557
 558 static DECLARE_INTC_DESC_ACK(intc_desc_irq3210, "sh7734-irq3210",
 559         irq3210_vectors, NULL,
 560         irq3210_mask_registers, irq3210_prio_registers,
 561         irq3210_sense_registers, irq3210_ack_registers);
 562
 563 /* External interrupt pins in IRL mode */
 564
 565 static struct intc_vect vectors_irl3210[] __initdata = {
 566         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 567         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 568         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 569         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 570         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 571         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 572         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 573         INTC_VECT(IRL0_HHHL, 0x3c0),
 574 };
 575
 576 static DECLARE_INTC_DESC(intc_desc_irl3210, "sh7734-irl3210",
 577         vectors_irl3210, NULL, mask_registers, NULL, NULL);
 578
 579 #define INTC_ICR0               0xFF802000
 580 #define INTC_INTMSK0    0xFF802044
 581 #define INTC_INTMSK1    0xFF802048
 582 #define INTC_INTMSKCLR0 0xFF802064
 583 #define INTC_INTMSKCLR1 0xFF802068
 584
 585 void __init plat_irq_setup(void)
 586 {
 587         /* disable IRQ3-0 */
 588         __raw_writel(0xF0000000, INTC_INTMSK0);
 589
 590         /* disable IRL3-0 */
 591         __raw_writel(0x80000000, INTC_INTMSK1);
 592
 593         /* select IRL mode for IRL3-0 */
 594         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0);
 595
 596         /* disable holding function, ie enable "SH-4 Mode (LVLMODE)" */
 597         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 598
 599         register_intc_controller(&intc_desc);
 600 }
 601
 602 void __init plat_irq_setup_pins(int mode)
 603 {
 604         switch (mode) {
 605         case IRQ_MODE_IRQ3210:
 606                 /* select IRQ mode for IRL3-0 */
 607                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 608                 register_intc_controller(&intc_desc_irq3210);
 609                 break;
 610         case IRQ_MODE_IRL3210:
 611                 /* enable IRL0-3 but don't provide any masking */
 612                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 613                 __raw_writel(0xf0000000, INTC_INTMSKCLR0);
 614                 break;
 615         case IRQ_MODE_IRL3210_MASK:
 616                 /* enable IRL0-3 and mask using cpu intc controller */
 617                 __raw_writel(0x80000000, INTC_INTMSKCLR0);
 618                 register_intc_controller(&intc_desc_irl3210);
 619                 break;
 620         default:
 621                 BUG();
 622         }
 623 }