4 * Copyright (C) 2008 - 2012 Paul Mundt
6 * Single stepping taken from the old stub by Henry Bell and Jeremy Siegel.
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/kgdb.h>
13 #include <linux/kdebug.h>
14 #include <linux/irq.h>
16 #include <linux/sched.h>
17 #include <linux/sched/task_stack.h>
19 #include <asm/cacheflush.h>
20 #include <asm/traps.h>
22 /* Macros for single step instruction identification */
23 #define OPCODE_BT(op) (((op) & 0xff00) == 0x8900)
24 #define OPCODE_BF(op) (((op) & 0xff00) == 0x8b00)
25 #define OPCODE_BTF_DISP(op) (((op) & 0x80) ? (((op) | 0xffffff80) << 1) : \
26 (((op) & 0x7f ) << 1))
27 #define OPCODE_BFS(op) (((op) & 0xff00) == 0x8f00)
28 #define OPCODE_BTS(op) (((op) & 0xff00) == 0x8d00)
29 #define OPCODE_BRA(op) (((op) & 0xf000) == 0xa000)
30 #define OPCODE_BRA_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \
31 (((op) & 0x7ff) << 1))
32 #define OPCODE_BRAF(op) (((op) & 0xf0ff) == 0x0023)
33 #define OPCODE_BRAF_REG(op) (((op) & 0x0f00) >> 8)
34 #define OPCODE_BSR(op) (((op) & 0xf000) == 0xb000)
35 #define OPCODE_BSR_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \
36 (((op) & 0x7ff) << 1))
37 #define OPCODE_BSRF(op) (((op) & 0xf0ff) == 0x0003)
38 #define OPCODE_BSRF_REG(op) (((op) >> 8) & 0xf)
39 #define OPCODE_JMP(op) (((op) & 0xf0ff) == 0x402b)
40 #define OPCODE_JMP_REG(op) (((op) >> 8) & 0xf)
41 #define OPCODE_JSR(op) (((op) & 0xf0ff) == 0x400b)
42 #define OPCODE_JSR_REG(op) (((op) >> 8) & 0xf)
43 #define OPCODE_RTS(op) ((op) == 0xb)
44 #define OPCODE_RTE(op) ((op) == 0x2b)
46 #define SR_T_BIT_MASK 0x1
47 #define STEP_OPCODE 0xc33d
49 /* Calculate the new address for after a step */
50 static short *get_step_address(struct pt_regs
*linux_regs
)
52 insn_size_t op
= __raw_readw(linux_regs
->pc
);
57 if (linux_regs
->sr
& SR_T_BIT_MASK
)
58 addr
= linux_regs
->pc
+ 4 + OPCODE_BTF_DISP(op
);
60 addr
= linux_regs
->pc
+ 2;
64 else if (OPCODE_BTS(op
)) {
65 if (linux_regs
->sr
& SR_T_BIT_MASK
)
66 addr
= linux_regs
->pc
+ 4 + OPCODE_BTF_DISP(op
);
68 addr
= linux_regs
->pc
+ 4; /* Not in delay slot */
72 else if (OPCODE_BF(op
)) {
73 if (!(linux_regs
->sr
& SR_T_BIT_MASK
))
74 addr
= linux_regs
->pc
+ 4 + OPCODE_BTF_DISP(op
);
76 addr
= linux_regs
->pc
+ 2;
80 else if (OPCODE_BFS(op
)) {
81 if (!(linux_regs
->sr
& SR_T_BIT_MASK
))
82 addr
= linux_regs
->pc
+ 4 + OPCODE_BTF_DISP(op
);
84 addr
= linux_regs
->pc
+ 4; /* Not in delay slot */
88 else if (OPCODE_BRA(op
))
89 addr
= linux_regs
->pc
+ 4 + OPCODE_BRA_DISP(op
);
92 else if (OPCODE_BRAF(op
))
93 addr
= linux_regs
->pc
+ 4
94 + linux_regs
->regs
[OPCODE_BRAF_REG(op
)];
97 else if (OPCODE_BSR(op
))
98 addr
= linux_regs
->pc
+ 4 + OPCODE_BSR_DISP(op
);
101 else if (OPCODE_BSRF(op
))
102 addr
= linux_regs
->pc
+ 4
103 + linux_regs
->regs
[OPCODE_BSRF_REG(op
)];
106 else if (OPCODE_JMP(op
))
107 addr
= linux_regs
->regs
[OPCODE_JMP_REG(op
)];
110 else if (OPCODE_JSR(op
))
111 addr
= linux_regs
->regs
[OPCODE_JSR_REG(op
)];
114 else if (OPCODE_RTS(op
))
115 addr
= linux_regs
->pr
;
118 else if (OPCODE_RTE(op
))
119 addr
= linux_regs
->regs
[15];
123 addr
= linux_regs
->pc
+ instruction_size(op
);
125 flush_icache_range(addr
, addr
+ instruction_size(op
));
126 return (short *)addr
;
130 * Replace the instruction immediately after the current instruction
131 * (i.e. next in the expected flow of control) with a trap instruction,
132 * so that returning will cause only a single instruction to be executed.
133 * Note that this model is slightly broken for instructions with delay
134 * slots (e.g. B[TF]S, BSR, BRA etc), where both the branch and the
135 * instruction in the delay slot will be executed.
138 static unsigned long stepped_address
;
139 static insn_size_t stepped_opcode
;
141 static void do_single_step(struct pt_regs
*linux_regs
)
143 /* Determine where the target instruction will send us to */
144 unsigned short *addr
= get_step_address(linux_regs
);
146 stepped_address
= (int)addr
;
149 stepped_opcode
= __raw_readw((long)addr
);
152 /* Flush and return */
153 flush_icache_range((long)addr
, (long)addr
+
154 instruction_size(stepped_opcode
));
157 /* Undo a single step */
158 static void undo_single_step(struct pt_regs
*linux_regs
)
160 /* If we have stepped, put back the old instruction */
161 /* Use stepped_address in case we stopped elsewhere */
162 if (stepped_opcode
!= 0) {
163 __raw_writew(stepped_opcode
, stepped_address
);
164 flush_icache_range(stepped_address
, stepped_address
+ 2);
170 struct dbg_reg_def_t dbg_reg_def
[DBG_MAX_REG_NUM
] = {
171 { "r0", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[0]) },
172 { "r1", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[1]) },
173 { "r2", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[2]) },
174 { "r3", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[3]) },
175 { "r4", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[4]) },
176 { "r5", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[5]) },
177 { "r6", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[6]) },
178 { "r7", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[7]) },
179 { "r8", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[8]) },
180 { "r9", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[9]) },
181 { "r10", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[10]) },
182 { "r11", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[11]) },
183 { "r12", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[12]) },
184 { "r13", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[13]) },
185 { "r14", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[14]) },
186 { "r15", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, regs
[15]) },
187 { "pc", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, pc
) },
188 { "pr", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, pr
) },
189 { "sr", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, sr
) },
190 { "gbr", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, gbr
) },
191 { "mach", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, mach
) },
192 { "macl", GDB_SIZEOF_REG
, offsetof(struct pt_regs
, macl
) },
193 { "vbr", GDB_SIZEOF_REG
, -1 },
196 int dbg_set_reg(int regno
, void *mem
, struct pt_regs
*regs
)
198 if (regno
< 0 || regno
>= DBG_MAX_REG_NUM
)
201 if (dbg_reg_def
[regno
].offset
!= -1)
202 memcpy((void *)regs
+ dbg_reg_def
[regno
].offset
, mem
,
203 dbg_reg_def
[regno
].size
);
208 char *dbg_get_reg(int regno
, void *mem
, struct pt_regs
*regs
)
210 if (regno
>= DBG_MAX_REG_NUM
|| regno
< 0)
213 if (dbg_reg_def
[regno
].size
!= -1)
214 memcpy(mem
, (void *)regs
+ dbg_reg_def
[regno
].offset
,
215 dbg_reg_def
[regno
].size
);
219 __asm__
__volatile__ ("stc vbr, %0" : "=r" (mem
));
223 return dbg_reg_def
[regno
].name
;
226 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs
, struct task_struct
*p
)
228 struct pt_regs
*thread_regs
= task_pt_regs(p
);
231 /* Initialize to zero */
232 for (reg
= 0; reg
< DBG_MAX_REG_NUM
; reg
++)
236 * Copy out GP regs 8 to 14.
238 * switch_to() relies on SR.RB toggling, so regs 0->7 are banked
239 * and need privileged instructions to get to. The r15 value we
240 * fetch from the thread info directly.
242 for (reg
= GDB_R8
; reg
< GDB_R15
; reg
++)
243 gdb_regs
[reg
] = thread_regs
->regs
[reg
];
245 gdb_regs
[GDB_R15
] = p
->thread
.sp
;
246 gdb_regs
[GDB_PC
] = p
->thread
.pc
;
249 * Additional registers we have context for
251 gdb_regs
[GDB_PR
] = thread_regs
->pr
;
252 gdb_regs
[GDB_GBR
] = thread_regs
->gbr
;
255 int kgdb_arch_handle_exception(int e_vector
, int signo
, int err_code
,
256 char *remcomInBuffer
, char *remcomOutBuffer
,
257 struct pt_regs
*linux_regs
)
262 /* Undo any stepping we may have done */
263 undo_single_step(linux_regs
);
265 switch (remcomInBuffer
[0]) {
268 /* try to read optional parameter, pc unchanged if no parm */
269 ptr
= &remcomInBuffer
[1];
270 if (kgdb_hex2long(&ptr
, &addr
))
271 linux_regs
->pc
= addr
;
274 atomic_set(&kgdb_cpu_doing_single_step
, -1);
276 if (remcomInBuffer
[0] == 's') {
277 do_single_step(linux_regs
);
278 kgdb_single_step
= 1;
280 atomic_set(&kgdb_cpu_doing_single_step
,
281 raw_smp_processor_id());
287 /* this means that we do not want to exit from the handler: */
291 unsigned long kgdb_arch_pc(int exception
, struct pt_regs
*regs
)
294 return instruction_pointer(regs
) - 2;
295 return instruction_pointer(regs
);
298 void kgdb_arch_set_pc(struct pt_regs
*regs
, unsigned long ip
)
304 * The primary entry points for the kgdb debug trap table entries.
306 BUILD_TRAP_HANDLER(singlestep
)
311 local_irq_save(flags
);
312 regs
->pc
-= instruction_size(__raw_readw(regs
->pc
- 4));
313 kgdb_handle_exception(0, SIGTRAP
, 0, regs
);
314 local_irq_restore(flags
);
317 static void kgdb_call_nmi_hook(void *ignored
)
319 kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
322 void kgdb_roundup_cpus(unsigned long flags
)
325 smp_call_function(kgdb_call_nmi_hook
, NULL
, 0);
329 static int __kgdb_notify(struct die_args
*args
, unsigned long cmd
)
336 * This means a user thread is single stepping
337 * a system call which should be ignored
339 if (test_thread_flag(TIF_SINGLESTEP
))
342 ret
= kgdb_handle_exception(args
->trapnr
& 0xff, args
->signr
,
343 args
->err
, args
->regs
);
354 kgdb_notify(struct notifier_block
*self
, unsigned long cmd
, void *ptr
)
359 local_irq_save(flags
);
360 ret
= __kgdb_notify(ptr
, cmd
);
361 local_irq_restore(flags
);
366 static struct notifier_block kgdb_notifier
= {
367 .notifier_call
= kgdb_notify
,
370 * Lowest-prio notifier priority, we want to be notified last:
372 .priority
= -INT_MAX
,
375 int kgdb_arch_init(void)
377 return register_die_notifier(&kgdb_notifier
);
380 void kgdb_arch_exit(void)
382 unregister_die_notifier(&kgdb_notifier
);
385 struct kgdb_arch arch_kgdb_ops
= {
386 /* Breakpoint instruction: trapa #0x3c */
387 #ifdef CONFIG_CPU_LITTLE_ENDIAN
388 .gdb_bpt_instr
= { 0x3c, 0xc3 },
390 .gdb_bpt_instr
= { 0xc3, 0x3c },