arch/sparc/kernel/rtrap_64.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * rtrap.S: Preparing for return from trap on Sparc V9.
   4  *
   5  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   7  */
   8
   9
  10 #include <asm/asi.h>
  11 #include <asm/pstate.h>
  12 #include <asm/ptrace.h>
  13 #include <asm/spitfire.h>
  14 #include <asm/head.h>
  15 #include <asm/visasm.h>
  16 #include <asm/processor.h>
  17
  18 #ifdef CONFIG_CONTEXT_TRACKING
  19 # define SCHEDULE_USER schedule_user
  20 #else
  21 # define SCHEDULE_USER schedule
  22 #endif
  23
  24                 .text
  25                 .align                  32
  26 __handle_preemption:
  27                 call                    SCHEDULE_USER
  28                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  29                 ba,pt                   %xcc, __handle_preemption_continue
  30                  wrpr                   %g0, RTRAP_PSTATE_IRQOFF, %pstate
  31
  32 __handle_user_windows:
  33                 call                    fault_in_user_windows
  34                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  35                 ba,pt                   %xcc, __handle_preemption_continue
  36                  wrpr                   %g0, RTRAP_PSTATE_IRQOFF, %pstate
  37
  38 __handle_userfpu:
  39                 rd                      %fprs, %l5
  40                 andcc                   %l5, FPRS_FEF, %g0
  41                 sethi                   %hi(TSTATE_PEF), %o0
  42                 be,a,pn                 %icc, __handle_userfpu_continue
  43                  andn                   %l1, %o0, %l1
  44                 ba,a,pt                 %xcc, __handle_userfpu_continue
  45
  46 __handle_signal:
  47                 mov                     %l5, %o1
  48                 add                     %sp, PTREGS_OFF, %o0
  49                 mov                     %l0, %o2
  50                 call                    do_notify_resume
  51                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  52                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
  53
  54                 /* Signal delivery can modify pt_regs tstate, so we must
  55                  * reload it.
  56                  */
  57                 ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
  58                 sethi                   %hi(0xf << 20), %l4
  59                 and                     %l1, %l4, %l4
  60                 ba,pt                   %xcc, __handle_preemption_continue
  61                  andn                   %l1, %l4, %l1
  62
  63                 /* When returning from a NMI (%pil==15) interrupt we want to
  64                  * avoid running softirqs, doing IRQ tracing, preempting, etc.
  65                  */
  66                 .globl                  rtrap_nmi
  67 rtrap_nmi:      ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
  68                 sethi                   %hi(0xf << 20), %l4
  69                 and                     %l1, %l4, %l4
  70                 andn                    %l1, %l4, %l1
  71                 srl                     %l4, 20, %l4
  72                 ba,pt                   %xcc, rtrap_no_irq_enable
  73                 nop
  74                 /* Do not actually set the %pil here.  We will do that
  75                  * below after we clear PSTATE_IE in the %pstate register.
  76                  * If we re-enable interrupts here, we can recurse down
  77                  * the hardirq stack potentially endlessly, causing a
  78                  * stack overflow.
  79                  */
  80
  81                 .align                  64
  82                 .globl                  rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
  83 rtrap_irq:
  84 rtrap:
  85                 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
  86                 ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
  87 rtrap_xcall:
  88                 sethi                   %hi(0xf << 20), %l4
  89                 and                     %l1, %l4, %l4
  90                 andn                    %l1, %l4, %l1
  91                 srl                     %l4, 20, %l4
  92 #ifdef CONFIG_TRACE_IRQFLAGS
  93                 brnz,pn                 %l4, rtrap_no_irq_enable
  94                  nop
  95                 call                    trace_hardirqs_on
  96                  nop
  97                 /* Do not actually set the %pil here.  We will do that
  98                  * below after we clear PSTATE_IE in the %pstate register.
  99                  * If we re-enable interrupts here, we can recurse down
 100                  * the hardirq stack potentially endlessly, causing a
 101                  * stack overflow.
 102                  *
 103                  * It is tempting to put this test and trace_hardirqs_on
 104                  * call at the 'rt_continue' label, but that will not work
 105                  * as that path hits unconditionally and we do not want to
 106                  * execute this in NMI return paths, for example.
 107                  */
 108 #endif
 109 rtrap_no_irq_enable:
 110                 andcc                   %l1, TSTATE_PRIV, %l3
 111                 bne,pn                  %icc, to_kernel
 112                  nop
 113
 114                 /* We must hold IRQs off and atomically test schedule+signal
 115                  * state, then hold them off all the way back to userspace.
 116                  * If we are returning to kernel, none of this matters.  Note
 117                  * that we are disabling interrupts via PSTATE_IE, not using
 118                  * %pil.
 119                  *
 120                  * If we do not do this, there is a window where we would do
 121                  * the tests, later the signal/resched event arrives but we do
 122                  * not process it since we are still in kernel mode.  It would
 123                  * take until the next local IRQ before the signal/resched
 124                  * event would be handled.
 125                  *
 126                  * This also means that if we have to deal with user
 127                  * windows, we have to redo all of these sched+signal checks
 128                  * with IRQs disabled.
 129                  */
 130 to_user:        wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
 131                 wrpr                    0, %pil
 132 __handle_preemption_continue:
 133                 ldx                     [%g6 + TI_FLAGS], %l0
 134                 sethi                   %hi(_TIF_USER_WORK_MASK), %o0
 135                 or                      %o0, %lo(_TIF_USER_WORK_MASK), %o0
 136                 andcc                   %l0, %o0, %g0
 137                 sethi                   %hi(TSTATE_PEF), %o0
 138                 be,pt                   %xcc, user_nowork
 139                  andcc                  %l1, %o0, %g0
 140                 andcc                   %l0, _TIF_NEED_RESCHED, %g0
 141                 bne,pn                  %xcc, __handle_preemption
 142                  andcc                  %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
 143                 bne,pn                  %xcc, __handle_signal
 144                  ldub                   [%g6 + TI_WSAVED], %o2
 145                 brnz,pn                 %o2, __handle_user_windows
 146                  nop
 147                 sethi                   %hi(TSTATE_PEF), %o0
 148                 andcc                   %l1, %o0, %g0
 149
 150                 /* This fpdepth clear is necessary for non-syscall rtraps only */
 151 user_nowork:
 152                 bne,pn                  %xcc, __handle_userfpu
 153                  stb                    %g0, [%g6 + TI_FPDEPTH]
 154 __handle_userfpu_continue:
 155
 156 rt_continue:    ldx                     [%sp + PTREGS_OFF + PT_V9_G1], %g1
 157                 ldx                     [%sp + PTREGS_OFF + PT_V9_G2], %g2
 158
 159                 ldx                     [%sp + PTREGS_OFF + PT_V9_G3], %g3
 160                 ldx                     [%sp + PTREGS_OFF + PT_V9_G4], %g4
 161                 ldx                     [%sp + PTREGS_OFF + PT_V9_G5], %g5
 162                 brz,pt                  %l3, 1f
 163                 mov                     %g6, %l2
 164
 165                 /* Must do this before thread reg is clobbered below.  */
 166                 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
 167 1:
 168                 ldx                     [%sp + PTREGS_OFF + PT_V9_G6], %g6
 169                 ldx                     [%sp + PTREGS_OFF + PT_V9_G7], %g7
 170
 171                 /* Normal globals are restored, go to trap globals.  */
 172 661:            wrpr                    %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
 173                 nop
 174                 .section                .sun4v_2insn_patch, "ax"
 175                 .word                   661b
 176                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
 177                 SET_GL(1)
 178                 .previous
 179
 180                 mov                     %l2, %g6
 181
 182                 ldx                     [%sp + PTREGS_OFF + PT_V9_I0], %i0
 183                 ldx                     [%sp + PTREGS_OFF + PT_V9_I1], %i1
 184
 185                 ldx                     [%sp + PTREGS_OFF + PT_V9_I2], %i2
 186                 ldx                     [%sp + PTREGS_OFF + PT_V9_I3], %i3
 187                 ldx                     [%sp + PTREGS_OFF + PT_V9_I4], %i4
 188                 ldx                     [%sp + PTREGS_OFF + PT_V9_I5], %i5
 189                 ldx                     [%sp + PTREGS_OFF + PT_V9_I6], %i6
 190                 ldx                     [%sp + PTREGS_OFF + PT_V9_I7], %i7
 191                 ldx                     [%sp + PTREGS_OFF + PT_V9_TPC], %l2
 192                 ldx                     [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
 193
 194                 ld                      [%sp + PTREGS_OFF + PT_V9_Y], %o3
 195                 wr                      %o3, %g0, %y
 196                 wrpr                    %l4, 0x0, %pil
 197                 wrpr                    %g0, 0x1, %tl
 198                 andn                    %l1, TSTATE_SYSCALL, %l1
 199                 wrpr                    %l1, %g0, %tstate
 200                 wrpr                    %l2, %g0, %tpc
 201                 wrpr                    %o2, %g0, %tnpc
 202
 203                 brnz,pn                 %l3, kern_rtt
 204                  mov                    PRIMARY_CONTEXT, %l7
 205
 206 661:            ldxa                    [%l7 + %l7] ASI_DMMU, %l0
 207                 .section                .sun4v_1insn_patch, "ax"
 208                 .word                   661b
 209                 ldxa                    [%l7 + %l7] ASI_MMU, %l0
 210                 .previous
 211
 212                 sethi                   %hi(sparc64_kern_pri_nuc_bits), %l1
 213                 ldx                     [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
 214                 or                      %l0, %l1, %l0
 215
 216 661:            stxa                    %l0, [%l7] ASI_DMMU
 217                 .section                .sun4v_1insn_patch, "ax"
 218                 .word                   661b
 219                 stxa                    %l0, [%l7] ASI_MMU
 220                 .previous
 221
 222                 sethi                   %hi(KERNBASE), %l7
 223                 flush                   %l7
 224                 rdpr                    %wstate, %l1
 225                 rdpr                    %otherwin, %l2
 226                 srl                     %l1, 3, %l1
 227
 228 661:            wrpr                    %l2, %g0, %canrestore
 229                 .section                .fast_win_ctrl_1insn_patch, "ax"
 230                 .word                   661b
 231                 .word                   0x89880000      ! normalw
 232                 .previous
 233
 234                 wrpr                    %l1, %g0, %wstate
 235                 brnz,pt                 %l2, user_rtt_restore
 236 661:             wrpr                   %g0, %g0, %otherwin
 237                 .section                .fast_win_ctrl_1insn_patch, "ax"
 238                 .word                   661b
 239                  nop
 240                 .previous
 241
 242                 ldx                     [%g6 + TI_FLAGS], %g3
 243                 wr                      %g0, ASI_AIUP, %asi
 244                 rdpr                    %cwp, %g1
 245                 andcc                   %g3, _TIF_32BIT, %g0
 246                 sub                     %g1, 1, %g1
 247                 bne,pt                  %xcc, user_rtt_fill_32bit
 248                  wrpr                   %g1, %cwp
 249                 ba,a,pt                 %xcc, user_rtt_fill_64bit
 250                  nop
 251
 252 user_rtt_fill_fixup_dax:
 253                 ba,pt   %xcc, user_rtt_fill_fixup_common
 254                  mov    1, %g3
 255
 256 user_rtt_fill_fixup_mna:
 257                 ba,pt   %xcc, user_rtt_fill_fixup_common
 258                  mov    2, %g3
 259
 260 user_rtt_fill_fixup:
 261                 ba,pt   %xcc, user_rtt_fill_fixup_common
 262                  clr    %g3
 263
 264 user_rtt_pre_restore:
 265                 add                     %g1, 1, %g1
 266                 wrpr                    %g1, 0x0, %cwp
 267
 268 user_rtt_restore:
 269                 restore
 270                 rdpr                    %canrestore, %g1
 271                 wrpr                    %g1, 0x0, %cleanwin
 272                 retry
 273                 nop
 274
 275 kern_rtt:       rdpr                    %canrestore, %g1
 276                 brz,pn                  %g1, kern_rtt_fill
 277                  nop
 278 kern_rtt_restore:
 279                 stw                     %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
 280                 restore
 281                 retry
 282
 283 to_kernel:
 284 #ifdef CONFIG_PREEMPT
 285                 ldsw                    [%g6 + TI_PRE_COUNT], %l5
 286                 brnz                    %l5, kern_fpucheck
 287                  ldx                    [%g6 + TI_FLAGS], %l5
 288                 andcc                   %l5, _TIF_NEED_RESCHED, %g0
 289                 be,pt                   %xcc, kern_fpucheck
 290                  nop
 291                 cmp                     %l4, 0
 292                 bne,pn                  %xcc, kern_fpucheck
 293                  nop
 294                 call                    preempt_schedule_irq
 295                  nop
 296                 ba,pt                   %xcc, rtrap
 297 #endif
 298 kern_fpucheck:  ldub                    [%g6 + TI_FPDEPTH], %l5
 299                 brz,pt                  %l5, rt_continue
 300                  srl                    %l5, 1, %o0
 301                 add                     %g6, TI_FPSAVED, %l6
 302                 ldub                    [%l6 + %o0], %l2
 303                 sub                     %l5, 2, %l5
 304
 305                 add                     %g6, TI_GSR, %o1
 306                 andcc                   %l2, (FPRS_FEF|FPRS_DU), %g0
 307                 be,pt                   %icc, 2f
 308                  and                    %l2, FPRS_DL, %l6
 309                 andcc                   %l2, FPRS_FEF, %g0
 310                 be,pn                   %icc, 5f
 311                  sll                    %o0, 3, %o5
 312                 rd                      %fprs, %g1
 313
 314                 wr                      %g1, FPRS_FEF, %fprs
 315                 ldx                     [%o1 + %o5], %g1
 316                 add                     %g6, TI_XFSR, %o1
 317                 sll                     %o0, 8, %o2
 318                 add                     %g6, TI_FPREGS, %o3
 319                 brz,pn                  %l6, 1f
 320                  add                    %g6, TI_FPREGS+0x40, %o4
 321
 322                 membar                  #Sync
 323                 ldda                    [%o3 + %o2] ASI_BLK_P, %f0
 324                 ldda                    [%o4 + %o2] ASI_BLK_P, %f16
 325                 membar                  #Sync
 326 1:              andcc                   %l2, FPRS_DU, %g0
 327                 be,pn                   %icc, 1f
 328                  wr                     %g1, 0, %gsr
 329                 add                     %o2, 0x80, %o2
 330                 membar                  #Sync
 331                 ldda                    [%o3 + %o2] ASI_BLK_P, %f32
 332                 ldda                    [%o4 + %o2] ASI_BLK_P, %f48
 333 1:              membar                  #Sync
 334                 ldx                     [%o1 + %o5], %fsr
 335 2:              stb                     %l5, [%g6 + TI_FPDEPTH]
 336                 ba,pt                   %xcc, rt_continue
 337                  nop
 338 5:              wr                      %g0, FPRS_FEF, %fprs
 339                 sll                     %o0, 8, %o2
 340
 341                 add                     %g6, TI_FPREGS+0x80, %o3
 342                 add                     %g6, TI_FPREGS+0xc0, %o4
 343                 membar                  #Sync
 344                 ldda                    [%o3 + %o2] ASI_BLK_P, %f32
 345                 ldda                    [%o4 + %o2] ASI_BLK_P, %f48
 346                 membar                  #Sync
 347                 wr                      %g0, FPRS_DU, %fprs
 348                 ba,pt                   %xcc, rt_continue
 349                  stb                    %l5, [%g6 + TI_FPDEPTH]