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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / arch / tile / kernel / unaligned.c
blob77a0b6b6a2a12e39da35735cb40c754ca2842990
1 /*
2 * Copyright 2013 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * A code-rewriter that handles unaligned exception.
15 */
16
17 #include <linux/smp.h>
18 #include <linux/ptrace.h>
19 #include <linux/slab.h>
20 #include <linux/sched/debug.h>
21 #include <linux/sched/task.h>
22 #include <linux/thread_info.h>
23 #include <linux/uaccess.h>
24 #include <linux/mman.h>
25 #include <linux/types.h>
26 #include <linux/err.h>
27 #include <linux/extable.h>
28 #include <linux/compat.h>
29 #include <linux/prctl.h>
30 #include <asm/cacheflush.h>
31 #include <asm/traps.h>
32 #include <linux/uaccess.h>
33 #include <asm/unaligned.h>
34 #include <arch/abi.h>
35 #include <arch/spr_def.h>
36 #include <arch/opcode.h>
37
38
39 /*
40 * This file handles unaligned exception for tile-Gx. The tilepro's unaligned
41 * exception is supported out of single_step.c
42 */
43
44 int unaligned_printk;
45
46 static int __init setup_unaligned_printk(char *str)
47 {
48 long val;
49 if (kstrtol(str, 0, &val) != 0)
50 return 0;
51 unaligned_printk = val;
52 pr_info("Printk for each unaligned data accesses is %s\n",
53 unaligned_printk ? "enabled" : "disabled");
54 return 1;
55 }
56 __setup("unaligned_printk=", setup_unaligned_printk);
57
58 unsigned int unaligned_fixup_count;
59
60 #ifdef __tilegx__
61
62 /*
63 * Unalign data jit fixup code fragement. Reserved space is 128 bytes.
64 * The 1st 64-bit word saves fault PC address, 2nd word is the fault
65 * instruction bundle followed by 14 JIT bundles.
66 */
67
68 struct unaligned_jit_fragment {
69 unsigned long pc;
70 tilegx_bundle_bits bundle;
71 tilegx_bundle_bits insn[14];
72 };
73
74 /*
75 * Check if a nop or fnop at bundle's pipeline X0.
76 */
77
78 static bool is_bundle_x0_nop(tilegx_bundle_bits bundle)
79 {
80 return (((get_UnaryOpcodeExtension_X0(bundle) ==
81 NOP_UNARY_OPCODE_X0) &&
82 (get_RRROpcodeExtension_X0(bundle) ==
83 UNARY_RRR_0_OPCODE_X0) &&
84 (get_Opcode_X0(bundle) ==
85 RRR_0_OPCODE_X0)) ||
86 ((get_UnaryOpcodeExtension_X0(bundle) ==
87 FNOP_UNARY_OPCODE_X0) &&
88 (get_RRROpcodeExtension_X0(bundle) ==
89 UNARY_RRR_0_OPCODE_X0) &&
90 (get_Opcode_X0(bundle) ==
91 RRR_0_OPCODE_X0)));
92 }
93
94 /*
95 * Check if nop or fnop at bundle's pipeline X1.
96 */
97
98 static bool is_bundle_x1_nop(tilegx_bundle_bits bundle)
99 {
100 return (((get_UnaryOpcodeExtension_X1(bundle) ==
101 NOP_UNARY_OPCODE_X1) &&
102 (get_RRROpcodeExtension_X1(bundle) ==
103 UNARY_RRR_0_OPCODE_X1) &&
104 (get_Opcode_X1(bundle) ==
105 RRR_0_OPCODE_X1)) ||
106 ((get_UnaryOpcodeExtension_X1(bundle) ==
107 FNOP_UNARY_OPCODE_X1) &&
108 (get_RRROpcodeExtension_X1(bundle) ==
109 UNARY_RRR_0_OPCODE_X1) &&
110 (get_Opcode_X1(bundle) ==
111 RRR_0_OPCODE_X1)));
112 }
113
114 /*
115 * Check if nop or fnop at bundle's Y0 pipeline.
116 */
117
118 static bool is_bundle_y0_nop(tilegx_bundle_bits bundle)
119 {
120 return (((get_UnaryOpcodeExtension_Y0(bundle) ==
121 NOP_UNARY_OPCODE_Y0) &&
122 (get_RRROpcodeExtension_Y0(bundle) ==
123 UNARY_RRR_1_OPCODE_Y0) &&
124 (get_Opcode_Y0(bundle) ==
125 RRR_1_OPCODE_Y0)) ||
126 ((get_UnaryOpcodeExtension_Y0(bundle) ==
127 FNOP_UNARY_OPCODE_Y0) &&
128 (get_RRROpcodeExtension_Y0(bundle) ==
129 UNARY_RRR_1_OPCODE_Y0) &&
130 (get_Opcode_Y0(bundle) ==
131 RRR_1_OPCODE_Y0)));
132 }
133
134 /*
135 * Check if nop or fnop at bundle's pipeline Y1.
136 */
137
138 static bool is_bundle_y1_nop(tilegx_bundle_bits bundle)
139 {
140 return (((get_UnaryOpcodeExtension_Y1(bundle) ==
141 NOP_UNARY_OPCODE_Y1) &&
142 (get_RRROpcodeExtension_Y1(bundle) ==
143 UNARY_RRR_1_OPCODE_Y1) &&
144 (get_Opcode_Y1(bundle) ==
145 RRR_1_OPCODE_Y1)) ||
146 ((get_UnaryOpcodeExtension_Y1(bundle) ==
147 FNOP_UNARY_OPCODE_Y1) &&
148 (get_RRROpcodeExtension_Y1(bundle) ==
149 UNARY_RRR_1_OPCODE_Y1) &&
150 (get_Opcode_Y1(bundle) ==
151 RRR_1_OPCODE_Y1)));
152 }
153
154 /*
155 * Test if a bundle's y0 and y1 pipelines are both nop or fnop.
156 */
157
158 static bool is_y0_y1_nop(tilegx_bundle_bits bundle)
159 {
160 return is_bundle_y0_nop(bundle) && is_bundle_y1_nop(bundle);
161 }
162
163 /*
164 * Test if a bundle's x0 and x1 pipelines are both nop or fnop.
165 */
166
167 static bool is_x0_x1_nop(tilegx_bundle_bits bundle)
168 {
169 return is_bundle_x0_nop(bundle) && is_bundle_x1_nop(bundle);
170 }
171
172 /*
173 * Find the destination, source registers of fault unalign access instruction
174 * at X1 or Y2. Also, allocate up to 3 scratch registers clob1, clob2 and
175 * clob3, which are guaranteed different from any register used in the fault
176 * bundle. r_alias is used to return if the other instructions other than the
177 * unalign load/store shares same register with ra, rb and rd.
178 */
179
180 static void find_regs(tilegx_bundle_bits bundle, uint64_t *rd, uint64_t *ra,
181 uint64_t *rb, uint64_t *clob1, uint64_t *clob2,
182 uint64_t *clob3, bool *r_alias)
183 {
184 int i;
185 uint64_t reg;
186 uint64_t reg_map = 0, alias_reg_map = 0, map;
187 bool alias = false;
188
189 /*
190 * Parse fault bundle, find potential used registers and mark
191 * corresponding bits in reg_map and alias_map. These 2 bit maps
192 * are used to find the scratch registers and determine if there
193 * is register alias.
194 */
195 if (bundle & TILEGX_BUNDLE_MODE_MASK) { /* Y Mode Bundle. */
196
197 reg = get_SrcA_Y2(bundle);
198 reg_map |= 1ULL << reg;
199 *ra = reg;
200 reg = get_SrcBDest_Y2(bundle);
201 reg_map |= 1ULL << reg;
202
203 if (rd) {
204 /* Load. */
205 *rd = reg;
206 alias_reg_map = (1ULL << *rd) | (1ULL << *ra);
207 } else {
208 /* Store. */
209 *rb = reg;
210 alias_reg_map = (1ULL << *ra) | (1ULL << *rb);
211 }
212
213 if (!is_bundle_y1_nop(bundle)) {
214 reg = get_SrcA_Y1(bundle);
215 reg_map |= (1ULL << reg);
216 map = (1ULL << reg);
217
218 reg = get_SrcB_Y1(bundle);
219 reg_map |= (1ULL << reg);
220 map |= (1ULL << reg);
221
222 reg = get_Dest_Y1(bundle);
223 reg_map |= (1ULL << reg);
224 map |= (1ULL << reg);
225
226 if (map & alias_reg_map)
227 alias = true;
228 }
229
230 if (!is_bundle_y0_nop(bundle)) {
231 reg = get_SrcA_Y0(bundle);
232 reg_map |= (1ULL << reg);
233 map = (1ULL << reg);
234
235 reg = get_SrcB_Y0(bundle);
236 reg_map |= (1ULL << reg);
237 map |= (1ULL << reg);
238
239 reg = get_Dest_Y0(bundle);
240 reg_map |= (1ULL << reg);
241 map |= (1ULL << reg);
242
243 if (map & alias_reg_map)
244 alias = true;
245 }
246 } else { /* X Mode Bundle. */
247
248 reg = get_SrcA_X1(bundle);
249 reg_map |= (1ULL << reg);
250 *ra = reg;
251 if (rd) {
252 /* Load. */
253 reg = get_Dest_X1(bundle);
254 reg_map |= (1ULL << reg);
255 *rd = reg;
256 alias_reg_map = (1ULL << *rd) | (1ULL << *ra);
257 } else {
258 /* Store. */
259 reg = get_SrcB_X1(bundle);
260 reg_map |= (1ULL << reg);
261 *rb = reg;
262 alias_reg_map = (1ULL << *ra) | (1ULL << *rb);
263 }
264
265 if (!is_bundle_x0_nop(bundle)) {
266 reg = get_SrcA_X0(bundle);
267 reg_map |= (1ULL << reg);
268 map = (1ULL << reg);
269
270 reg = get_SrcB_X0(bundle);
271 reg_map |= (1ULL << reg);
272 map |= (1ULL << reg);
273
274 reg = get_Dest_X0(bundle);
275 reg_map |= (1ULL << reg);
276 map |= (1ULL << reg);
277
278 if (map & alias_reg_map)
279 alias = true;
280 }
281 }
282
283 /*
284 * "alias" indicates if the unalign access registers have collision
285 * with others in the same bundle. We jsut simply test all register
286 * operands case (RRR), ignored the case with immidate. If a bundle
287 * has no register alias, we may do fixup in a simple or fast manner.
288 * So if an immidata field happens to hit with a register, we may end
289 * up fall back to the generic handling.
290 */
291
292 *r_alias = alias;
293
294 /* Flip bits on reg_map. */
295 reg_map ^= -1ULL;
296
297 /* Scan reg_map lower 54(TREG_SP) bits to find 3 set bits. */
298 for (i = 0; i < TREG_SP; i++) {
299 if (reg_map & (0x1ULL << i)) {
300 if (*clob1 == -1) {
301 *clob1 = i;
302 } else if (*clob2 == -1) {
303 *clob2 = i;
304 } else if (*clob3 == -1) {
305 *clob3 = i;
306 return;
307 }
308 }
309 }
310 }
311
312 /*
313 * Sanity check for register ra, rb, rd, clob1/2/3. Return true if any of them
314 * is unexpected.
315 */
316
317 static bool check_regs(uint64_t rd, uint64_t ra, uint64_t rb,
318 uint64_t clob1, uint64_t clob2, uint64_t clob3)
319 {
320 bool unexpected = false;
321 if ((ra >= 56) && (ra != TREG_ZERO))
322 unexpected = true;
323
324 if ((clob1 >= 56) || (clob2 >= 56) || (clob3 >= 56))
325 unexpected = true;
326
327 if (rd != -1) {
328 if ((rd >= 56) && (rd != TREG_ZERO))
329 unexpected = true;
330 } else {
331 if ((rb >= 56) && (rb != TREG_ZERO))
332 unexpected = true;
333 }
334 return unexpected;
335 }
336
337
338 #define GX_INSN_X0_MASK ((1ULL << 31) - 1)
339 #define GX_INSN_X1_MASK (((1ULL << 31) - 1) << 31)
340 #define GX_INSN_Y0_MASK ((0xFULL << 27) | (0xFFFFFULL))
341 #define GX_INSN_Y1_MASK (GX_INSN_Y0_MASK << 31)
342 #define GX_INSN_Y2_MASK ((0x7FULL << 51) | (0x7FULL << 20))
343
344 #ifdef __LITTLE_ENDIAN
345 #define GX_INSN_BSWAP(_bundle_) (_bundle_)
346 #else
347 #define GX_INSN_BSWAP(_bundle_) swab64(_bundle_)
348 #endif /* __LITTLE_ENDIAN */
349
350 /*
351 * __JIT_CODE(.) creates template bundles in .rodata.unalign_data section.
352 * The corresponding static function jix_x#_###(.) generates partial or
353 * whole bundle based on the template and given arguments.
354 */
355
356 #define __JIT_CODE(_X_) \
357 asm (".pushsection .rodata.unalign_data, \"a\"\n" \
358 _X_"\n" \
359 ".popsection\n")
360
361 __JIT_CODE("__unalign_jit_x1_mtspr: {mtspr 0, r0}");
362 static tilegx_bundle_bits jit_x1_mtspr(int spr, int reg)
363 {
364 extern tilegx_bundle_bits __unalign_jit_x1_mtspr;
365 return (GX_INSN_BSWAP(__unalign_jit_x1_mtspr) & GX_INSN_X1_MASK) |
366 create_MT_Imm14_X1(spr) | create_SrcA_X1(reg);
367 }
368
369 __JIT_CODE("__unalign_jit_x1_mfspr: {mfspr r0, 0}");
370 static tilegx_bundle_bits jit_x1_mfspr(int reg, int spr)
371 {
372 extern tilegx_bundle_bits __unalign_jit_x1_mfspr;
373 return (GX_INSN_BSWAP(__unalign_jit_x1_mfspr) & GX_INSN_X1_MASK) |
374 create_MF_Imm14_X1(spr) | create_Dest_X1(reg);
375 }
376
377 __JIT_CODE("__unalign_jit_x0_addi: {addi r0, r0, 0; iret}");
378 static tilegx_bundle_bits jit_x0_addi(int rd, int ra, int imm8)
379 {
380 extern tilegx_bundle_bits __unalign_jit_x0_addi;
381 return (GX_INSN_BSWAP(__unalign_jit_x0_addi) & GX_INSN_X0_MASK) |
382 create_Dest_X0(rd) | create_SrcA_X0(ra) |
383 create_Imm8_X0(imm8);
384 }
385
386 __JIT_CODE("__unalign_jit_x1_ldna: {ldna r0, r0}");
387 static tilegx_bundle_bits jit_x1_ldna(int rd, int ra)
388 {
389 extern tilegx_bundle_bits __unalign_jit_x1_ldna;
390 return (GX_INSN_BSWAP(__unalign_jit_x1_ldna) & GX_INSN_X1_MASK) |
391 create_Dest_X1(rd) | create_SrcA_X1(ra);
392 }
393
394 __JIT_CODE("__unalign_jit_x0_dblalign: {dblalign r0, r0 ,r0}");
395 static tilegx_bundle_bits jit_x0_dblalign(int rd, int ra, int rb)
396 {
397 extern tilegx_bundle_bits __unalign_jit_x0_dblalign;
398 return (GX_INSN_BSWAP(__unalign_jit_x0_dblalign) & GX_INSN_X0_MASK) |
399 create_Dest_X0(rd) | create_SrcA_X0(ra) |
400 create_SrcB_X0(rb);
401 }
402
403 __JIT_CODE("__unalign_jit_x1_iret: {iret}");
404 static tilegx_bundle_bits jit_x1_iret(void)
405 {
406 extern tilegx_bundle_bits __unalign_jit_x1_iret;
407 return GX_INSN_BSWAP(__unalign_jit_x1_iret) & GX_INSN_X1_MASK;
408 }
409
410 __JIT_CODE("__unalign_jit_x01_fnop: {fnop;fnop}");
411 static tilegx_bundle_bits jit_x0_fnop(void)
412 {
413 extern tilegx_bundle_bits __unalign_jit_x01_fnop;
414 return GX_INSN_BSWAP(__unalign_jit_x01_fnop) & GX_INSN_X0_MASK;
415 }
416
417 static tilegx_bundle_bits jit_x1_fnop(void)
418 {
419 extern tilegx_bundle_bits __unalign_jit_x01_fnop;
420 return GX_INSN_BSWAP(__unalign_jit_x01_fnop) & GX_INSN_X1_MASK;
421 }
422
423 __JIT_CODE("__unalign_jit_y2_dummy: {fnop; fnop; ld zero, sp}");
424 static tilegx_bundle_bits jit_y2_dummy(void)
425 {
426 extern tilegx_bundle_bits __unalign_jit_y2_dummy;
427 return GX_INSN_BSWAP(__unalign_jit_y2_dummy) & GX_INSN_Y2_MASK;
428 }
429
430 static tilegx_bundle_bits jit_y1_fnop(void)
431 {
432 extern tilegx_bundle_bits __unalign_jit_y2_dummy;
433 return GX_INSN_BSWAP(__unalign_jit_y2_dummy) & GX_INSN_Y1_MASK;
434 }
435
436 __JIT_CODE("__unalign_jit_x1_st1_add: {st1_add r1, r0, 0}");
437 static tilegx_bundle_bits jit_x1_st1_add(int ra, int rb, int imm8)
438 {
439 extern tilegx_bundle_bits __unalign_jit_x1_st1_add;
440 return (GX_INSN_BSWAP(__unalign_jit_x1_st1_add) &
441 (~create_SrcA_X1(-1)) &
442 GX_INSN_X1_MASK) | create_SrcA_X1(ra) |
443 create_SrcB_X1(rb) | create_Dest_Imm8_X1(imm8);
444 }
445
446 __JIT_CODE("__unalign_jit_x1_st: {crc32_8 r1, r0, r0; st r0, r0}");
447 static tilegx_bundle_bits jit_x1_st(int ra, int rb)
448 {
449 extern tilegx_bundle_bits __unalign_jit_x1_st;
450 return (GX_INSN_BSWAP(__unalign_jit_x1_st) & GX_INSN_X1_MASK) |
451 create_SrcA_X1(ra) | create_SrcB_X1(rb);
452 }
453
454 __JIT_CODE("__unalign_jit_x1_st_add: {st_add r1, r0, 0}");
455 static tilegx_bundle_bits jit_x1_st_add(int ra, int rb, int imm8)
456 {
457 extern tilegx_bundle_bits __unalign_jit_x1_st_add;
458 return (GX_INSN_BSWAP(__unalign_jit_x1_st_add) &
459 (~create_SrcA_X1(-1)) &
460 GX_INSN_X1_MASK) | create_SrcA_X1(ra) |
461 create_SrcB_X1(rb) | create_Dest_Imm8_X1(imm8);
462 }
463
464 __JIT_CODE("__unalign_jit_x1_ld: {crc32_8 r1, r0, r0; ld r0, r0}");
465 static tilegx_bundle_bits jit_x1_ld(int rd, int ra)
466 {
467 extern tilegx_bundle_bits __unalign_jit_x1_ld;
468 return (GX_INSN_BSWAP(__unalign_jit_x1_ld) & GX_INSN_X1_MASK) |
469 create_Dest_X1(rd) | create_SrcA_X1(ra);
470 }
471
472 __JIT_CODE("__unalign_jit_x1_ld_add: {ld_add r1, r0, 0}");
473 static tilegx_bundle_bits jit_x1_ld_add(int rd, int ra, int imm8)
474 {
475 extern tilegx_bundle_bits __unalign_jit_x1_ld_add;
476 return (GX_INSN_BSWAP(__unalign_jit_x1_ld_add) &
477 (~create_Dest_X1(-1)) &
478 GX_INSN_X1_MASK) | create_Dest_X1(rd) |
479 create_SrcA_X1(ra) | create_Imm8_X1(imm8);
480 }
481
482 __JIT_CODE("__unalign_jit_x0_bfexts: {bfexts r0, r0, 0, 0}");
483 static tilegx_bundle_bits jit_x0_bfexts(int rd, int ra, int bfs, int bfe)
484 {
485 extern tilegx_bundle_bits __unalign_jit_x0_bfexts;
486 return (GX_INSN_BSWAP(__unalign_jit_x0_bfexts) &
487 GX_INSN_X0_MASK) |
488 create_Dest_X0(rd) | create_SrcA_X0(ra) |
489 create_BFStart_X0(bfs) | create_BFEnd_X0(bfe);
490 }
491
492 __JIT_CODE("__unalign_jit_x0_bfextu: {bfextu r0, r0, 0, 0}");
493 static tilegx_bundle_bits jit_x0_bfextu(int rd, int ra, int bfs, int bfe)
494 {
495 extern tilegx_bundle_bits __unalign_jit_x0_bfextu;
496 return (GX_INSN_BSWAP(__unalign_jit_x0_bfextu) &
497 GX_INSN_X0_MASK) |
498 create_Dest_X0(rd) | create_SrcA_X0(ra) |
499 create_BFStart_X0(bfs) | create_BFEnd_X0(bfe);
500 }
501
502 __JIT_CODE("__unalign_jit_x1_addi: {bfextu r1, r1, 0, 0; addi r0, r0, 0}");
503 static tilegx_bundle_bits jit_x1_addi(int rd, int ra, int imm8)
504 {
505 extern tilegx_bundle_bits __unalign_jit_x1_addi;
506 return (GX_INSN_BSWAP(__unalign_jit_x1_addi) & GX_INSN_X1_MASK) |
507 create_Dest_X1(rd) | create_SrcA_X1(ra) |
508 create_Imm8_X1(imm8);
509 }
510
511 __JIT_CODE("__unalign_jit_x0_shrui: {shrui r0, r0, 0; iret}");
512 static tilegx_bundle_bits jit_x0_shrui(int rd, int ra, int imm6)
513 {
514 extern tilegx_bundle_bits __unalign_jit_x0_shrui;
515 return (GX_INSN_BSWAP(__unalign_jit_x0_shrui) &
516 GX_INSN_X0_MASK) |
517 create_Dest_X0(rd) | create_SrcA_X0(ra) |
518 create_ShAmt_X0(imm6);
519 }
520
521 __JIT_CODE("__unalign_jit_x0_rotli: {rotli r0, r0, 0; iret}");
522 static tilegx_bundle_bits jit_x0_rotli(int rd, int ra, int imm6)
523 {
524 extern tilegx_bundle_bits __unalign_jit_x0_rotli;
525 return (GX_INSN_BSWAP(__unalign_jit_x0_rotli) &
526 GX_INSN_X0_MASK) |
527 create_Dest_X0(rd) | create_SrcA_X0(ra) |
528 create_ShAmt_X0(imm6);
529 }
530
531 __JIT_CODE("__unalign_jit_x1_bnezt: {bnezt r0, __unalign_jit_x1_bnezt}");
532 static tilegx_bundle_bits jit_x1_bnezt(int ra, int broff)
533 {
534 extern tilegx_bundle_bits __unalign_jit_x1_bnezt;
535 return (GX_INSN_BSWAP(__unalign_jit_x1_bnezt) &
536 GX_INSN_X1_MASK) |
537 create_SrcA_X1(ra) | create_BrOff_X1(broff);
538 }
539
540 #undef __JIT_CODE
541
542 /*
543 * This function generates unalign fixup JIT.
544 *
545 * We first find unalign load/store instruction's destination, source
546 * registers: ra, rb and rd. and 3 scratch registers by calling
547 * find_regs(...). 3 scratch clobbers should not alias with any register
548 * used in the fault bundle. Then analyze the fault bundle to determine
549 * if it's a load or store, operand width, branch or address increment etc.
550 * At last generated JIT is copied into JIT code area in user space.
551 */
552
553 static
554 void jit_bundle_gen(struct pt_regs *regs, tilegx_bundle_bits bundle,
555 int align_ctl)
556 {
557 struct thread_info *info = current_thread_info();
558 struct unaligned_jit_fragment frag;
559 struct unaligned_jit_fragment *jit_code_area;
560 tilegx_bundle_bits bundle_2 = 0;
561 /* If bundle_2_enable = false, bundle_2 is fnop/nop operation. */
562 bool bundle_2_enable = true;
563 uint64_t ra = -1, rb = -1, rd = -1, clob1 = -1, clob2 = -1, clob3 = -1;
564 /*
565 * Indicate if the unalign access
566 * instruction's registers hit with
567 * others in the same bundle.
568 */
569 bool alias = false;
570 bool load_n_store = true;
571 bool load_store_signed = false;
572 unsigned int load_store_size = 8;
573 bool y1_br = false; /* True, for a branch in same bundle at Y1.*/
574 int y1_br_reg = 0;
575 /* True for link operation. i.e. jalr or lnk at Y1 */
576 bool y1_lr = false;
577 int y1_lr_reg = 0;
578 bool x1_add = false;/* True, for load/store ADD instruction at X1*/
579 int x1_add_imm8 = 0;
580 bool unexpected = false;
581 int n = 0, k;
582
583 jit_code_area =
584 (struct unaligned_jit_fragment *)(info->unalign_jit_base);
585
586 memset((void *)&frag, 0, sizeof(frag));
587
588 /* 0: X mode, Otherwise: Y mode. */
589 if (bundle & TILEGX_BUNDLE_MODE_MASK) {
590 unsigned int mod, opcode;
591
592 if (get_Opcode_Y1(bundle) == RRR_1_OPCODE_Y1 &&
593 get_RRROpcodeExtension_Y1(bundle) ==
594 UNARY_RRR_1_OPCODE_Y1) {
595
596 opcode = get_UnaryOpcodeExtension_Y1(bundle);
597
598 /*
599 * Test "jalr", "jalrp", "jr", "jrp" instruction at Y1
600 * pipeline.
601 */
602 switch (opcode) {
603 case JALR_UNARY_OPCODE_Y1:
604 case JALRP_UNARY_OPCODE_Y1:
605 y1_lr = true;
606 y1_lr_reg = 55; /* Link register. */
607 /* FALLTHROUGH */
608 case JR_UNARY_OPCODE_Y1:
609 case JRP_UNARY_OPCODE_Y1:
610 y1_br = true;
611 y1_br_reg = get_SrcA_Y1(bundle);
612 break;
613 case LNK_UNARY_OPCODE_Y1:
614 /* "lnk" at Y1 pipeline. */
615 y1_lr = true;
616 y1_lr_reg = get_Dest_Y1(bundle);
617 break;
618 }
619 }
620
621 opcode = get_Opcode_Y2(bundle);
622 mod = get_Mode(bundle);
623
624 /*
625 * bundle_2 is bundle after making Y2 as a dummy operation
626 * - ld zero, sp
627 */
628 bundle_2 = (bundle & (~GX_INSN_Y2_MASK)) | jit_y2_dummy();
629
630 /* Make Y1 as fnop if Y1 is a branch or lnk operation. */
631 if (y1_br || y1_lr) {
632 bundle_2 &= ~(GX_INSN_Y1_MASK);
633 bundle_2 |= jit_y1_fnop();
634 }
635
636 if (is_y0_y1_nop(bundle_2))
637 bundle_2_enable = false;
638
639 if (mod == MODE_OPCODE_YC2) {
640 /* Store. */
641 load_n_store = false;
642 load_store_size = 1 << opcode;
643 load_store_signed = false;
644 find_regs(bundle, 0, &ra, &rb, &clob1, &clob2,
645 &clob3, &alias);
646 if (load_store_size > 8)
647 unexpected = true;
648 } else {
649 /* Load. */
650 load_n_store = true;
651 if (mod == MODE_OPCODE_YB2) {
652 switch (opcode) {
653 case LD_OPCODE_Y2:
654 load_store_signed = false;
655 load_store_size = 8;
656 break;
657 case LD4S_OPCODE_Y2:
658 load_store_signed = true;
659 load_store_size = 4;
660 break;
661 case LD4U_OPCODE_Y2:
662 load_store_signed = false;
663 load_store_size = 4;
664 break;
665 default:
666 unexpected = true;
667 }
668 } else if (mod == MODE_OPCODE_YA2) {
669 if (opcode == LD2S_OPCODE_Y2) {
670 load_store_signed = true;
671 load_store_size = 2;
672 } else if (opcode == LD2U_OPCODE_Y2) {
673 load_store_signed = false;
674 load_store_size = 2;
675 } else
676 unexpected = true;
677 } else
678 unexpected = true;
679 find_regs(bundle, &rd, &ra, &rb, &clob1, &clob2,
680 &clob3, &alias);
681 }
682 } else {
683 unsigned int opcode;
684
685 /* bundle_2 is bundle after making X1 as "fnop". */
686 bundle_2 = (bundle & (~GX_INSN_X1_MASK)) | jit_x1_fnop();
687
688 if (is_x0_x1_nop(bundle_2))
689 bundle_2_enable = false;
690
691 if (get_Opcode_X1(bundle) == RRR_0_OPCODE_X1) {
692 opcode = get_UnaryOpcodeExtension_X1(bundle);
693
694 if (get_RRROpcodeExtension_X1(bundle) ==
695 UNARY_RRR_0_OPCODE_X1) {
696 load_n_store = true;
697 find_regs(bundle, &rd, &ra, &rb, &clob1,
698 &clob2, &clob3, &alias);
699
700 switch (opcode) {
701 case LD_UNARY_OPCODE_X1:
702 load_store_signed = false;
703 load_store_size = 8;
704 break;
705 case LD4S_UNARY_OPCODE_X1:
706 load_store_signed = true;
707 /* FALLTHROUGH */
708 case LD4U_UNARY_OPCODE_X1:
709 load_store_size = 4;
710 break;
711
712 case LD2S_UNARY_OPCODE_X1:
713 load_store_signed = true;
714 /* FALLTHROUGH */
715 case LD2U_UNARY_OPCODE_X1:
716 load_store_size = 2;
717 break;
718 default:
719 unexpected = true;
720 }
721 } else {
722 load_n_store = false;
723 load_store_signed = false;
724 find_regs(bundle, 0, &ra, &rb,
725 &clob1, &clob2, &clob3,
726 &alias);
727
728 opcode = get_RRROpcodeExtension_X1(bundle);
729 switch (opcode) {
730 case ST_RRR_0_OPCODE_X1:
731 load_store_size = 8;
732 break;
733 case ST4_RRR_0_OPCODE_X1:
734 load_store_size = 4;
735 break;
736 case ST2_RRR_0_OPCODE_X1:
737 load_store_size = 2;
738 break;
739 default:
740 unexpected = true;
741 }
742 }
743 } else if (get_Opcode_X1(bundle) == IMM8_OPCODE_X1) {
744 load_n_store = true;
745 opcode = get_Imm8OpcodeExtension_X1(bundle);
746 switch (opcode) {
747 case LD_ADD_IMM8_OPCODE_X1:
748 load_store_size = 8;
749 break;
750
751 case LD4S_ADD_IMM8_OPCODE_X1:
752 load_store_signed = true;
753 /* FALLTHROUGH */
754 case LD4U_ADD_IMM8_OPCODE_X1:
755 load_store_size = 4;
756 break;
757
758 case LD2S_ADD_IMM8_OPCODE_X1:
759 load_store_signed = true;
760 /* FALLTHROUGH */
761 case LD2U_ADD_IMM8_OPCODE_X1:
762 load_store_size = 2;
763 break;
764
765 case ST_ADD_IMM8_OPCODE_X1:
766 load_n_store = false;
767 load_store_size = 8;
768 break;
769 case ST4_ADD_IMM8_OPCODE_X1:
770 load_n_store = false;
771 load_store_size = 4;
772 break;
773 case ST2_ADD_IMM8_OPCODE_X1:
774 load_n_store = false;
775 load_store_size = 2;
776 break;
777 default:
778 unexpected = true;
779 }
780
781 if (!unexpected) {
782 x1_add = true;
783 if (load_n_store)
784 x1_add_imm8 = get_Imm8_X1(bundle);
785 else
786 x1_add_imm8 = get_Dest_Imm8_X1(bundle);
787 }
788
789 find_regs(bundle, load_n_store ? (&rd) : NULL,
790 &ra, &rb, &clob1, &clob2, &clob3, &alias);
791 } else
792 unexpected = true;
793 }
794
795 /*
796 * Some sanity check for register numbers extracted from fault bundle.
797 */
798 if (check_regs(rd, ra, rb, clob1, clob2, clob3) == true)
799 unexpected = true;
800
801 /* Give warning if register ra has an aligned address. */
802 if (!unexpected)
803 WARN_ON(!((load_store_size - 1) & (regs->regs[ra])));
804
805
806 /*
807 * Fault came from kernel space, here we only need take care of
808 * unaligned "get_user/put_user" macros defined in "uaccess.h".
809 * Basically, we will handle bundle like this:
810 * {ld/2u/4s rd, ra; movei rx, 0} or {st/2/4 ra, rb; movei rx, 0}
811 * (Refer to file "arch/tile/include/asm/uaccess.h" for details).
812 * For either load or store, byte-wise operation is performed by calling
813 * get_user() or put_user(). If the macro returns non-zero value,
814 * set the value to rx, otherwise set zero to rx. Finally make pc point
815 * to next bundle and return.
816 */
817
818 if (EX1_PL(regs->ex1) != USER_PL) {
819
820 unsigned long rx = 0;
821 unsigned long x = 0, ret = 0;
822
823 if (y1_br || y1_lr || x1_add ||
824 (load_store_signed !=
825 (load_n_store && load_store_size == 4))) {
826 /* No branch, link, wrong sign-ext or load/store add. */
827 unexpected = true;
828 } else if (!unexpected) {
829 if (bundle & TILEGX_BUNDLE_MODE_MASK) {
830 /*
831 * Fault bundle is Y mode.
832 * Check if the Y1 and Y0 is the form of
833 * { movei rx, 0; nop/fnop }, if yes,
834 * find the rx.
835 */
836
837 if ((get_Opcode_Y1(bundle) == ADDI_OPCODE_Y1)
838 && (get_SrcA_Y1(bundle) == TREG_ZERO) &&
839 (get_Imm8_Y1(bundle) == 0) &&
840 is_bundle_y0_nop(bundle)) {
841 rx = get_Dest_Y1(bundle);
842 } else if ((get_Opcode_Y0(bundle) ==
843 ADDI_OPCODE_Y0) &&
844 (get_SrcA_Y0(bundle) == TREG_ZERO) &&
845 (get_Imm8_Y0(bundle) == 0) &&
846 is_bundle_y1_nop(bundle)) {
847 rx = get_Dest_Y0(bundle);
848 } else {
849 unexpected = true;
850 }
851 } else {
852 /*
853 * Fault bundle is X mode.
854 * Check if the X0 is 'movei rx, 0',
855 * if yes, find the rx.
856 */
857
858 if ((get_Opcode_X0(bundle) == IMM8_OPCODE_X0)
859 && (get_Imm8OpcodeExtension_X0(bundle) ==
860 ADDI_IMM8_OPCODE_X0) &&
861 (get_SrcA_X0(bundle) == TREG_ZERO) &&
862 (get_Imm8_X0(bundle) == 0)) {
863 rx = get_Dest_X0(bundle);
864 } else {
865 unexpected = true;
866 }
867 }
868
869 /* rx should be less than 56. */
870 if (!unexpected && (rx >= 56))
871 unexpected = true;
872 }
873
874 if (!search_exception_tables(regs->pc)) {
875 /* No fixup in the exception tables for the pc. */
876 unexpected = true;
877 }
878
879 if (unexpected) {
880 /* Unexpected unalign kernel fault. */
881 struct task_struct *tsk = validate_current();
882
883 bust_spinlocks(1);
884
885 show_regs(regs);
886
887 if (unlikely(tsk->pid < 2)) {
888 panic("Kernel unalign fault running %s!",
889 tsk->pid ? "init" : "the idle task");
890 }
891 #ifdef SUPPORT_DIE
892 die("Oops", regs);
893 #endif
894 bust_spinlocks(1);
895
896 do_group_exit(SIGKILL);
897
898 } else {
899 unsigned long i, b = 0;
900 unsigned char *ptr =
901 (unsigned char *)regs->regs[ra];
902 if (load_n_store) {
903 /* handle get_user(x, ptr) */
904 for (i = 0; i < load_store_size; i++) {
905 ret = get_user(b, ptr++);
906 if (!ret) {
907 /* Success! update x. */
908 #ifdef __LITTLE_ENDIAN
909 x |= (b << (8 * i));
910 #else
911 x <<= 8;
912 x |= b;
913 #endif /* __LITTLE_ENDIAN */
914 } else {
915 x = 0;
916 break;
917 }
918 }
919
920 /* Sign-extend 4-byte loads. */
921 if (load_store_size == 4)
922 x = (long)(int)x;
923
924 /* Set register rd. */
925 regs->regs[rd] = x;
926
927 /* Set register rx. */
928 regs->regs[rx] = ret;
929
930 /* Bump pc. */
931 regs->pc += 8;
932
933 } else {
934 /* Handle put_user(x, ptr) */
935 x = regs->regs[rb];
936 #ifdef __LITTLE_ENDIAN
937 b = x;
938 #else
939 /*
940 * Swap x in order to store x from low
941 * to high memory same as the
942 * little-endian case.
943 */
944 switch (load_store_size) {
945 case 8:
946 b = swab64(x);
947 break;
948 case 4:
949 b = swab32(x);
950 break;
951 case 2:
952 b = swab16(x);
953 break;
954 }
955 #endif /* __LITTLE_ENDIAN */
956 for (i = 0; i < load_store_size; i++) {
957 ret = put_user(b, ptr++);
958 if (ret)
959 break;
960 /* Success! shift 1 byte. */
961 b >>= 8;
962 }
963 /* Set register rx. */
964 regs->regs[rx] = ret;
965
966 /* Bump pc. */
967 regs->pc += 8;
968 }
969 }
970
971 unaligned_fixup_count++;
972
973 if (unaligned_printk) {
974 pr_info("%s/%d - Unalign fixup for kernel access to userspace %lx\n",
975 current->comm, current->pid, regs->regs[ra]);
976 }
977
978 /* Done! Return to the exception handler. */
979 return;
980 }
981
982 if ((align_ctl == 0) || unexpected) {
983 siginfo_t info;
984
985 clear_siginfo(&info);
986 info.si_signo = SIGBUS;
987 info.si_code = BUS_ADRALN;
988 info.si_addr = (unsigned char __user *)0;
989
990 if (unaligned_printk)
991 pr_info("Unalign bundle: unexp @%llx, %llx\n",
992 (unsigned long long)regs->pc,
993 (unsigned long long)bundle);
994
995 if (ra < 56) {
996 unsigned long uaa = (unsigned long)regs->regs[ra];
997 /* Set bus Address. */
998 info.si_addr = (unsigned char __user *)uaa;
999 }
1000
1001 unaligned_fixup_count++;
1002
1003 trace_unhandled_signal("unaligned fixup trap", regs,
1004 (unsigned long)info.si_addr, SIGBUS);
1005 force_sig_info(info.si_signo, &info, current);
1006 return;
1007 }
1008
1009 #ifdef __LITTLE_ENDIAN
1010 #define UA_FIXUP_ADDR_DELTA 1
1011 #define UA_FIXUP_BFEXT_START(_B_) 0
1012 #define UA_FIXUP_BFEXT_END(_B_) (8 * (_B_) - 1)
1013 #else /* __BIG_ENDIAN */
1014 #define UA_FIXUP_ADDR_DELTA -1
1015 #define UA_FIXUP_BFEXT_START(_B_) (64 - 8 * (_B_))
1016 #define UA_FIXUP_BFEXT_END(_B_) 63
1017 #endif /* __LITTLE_ENDIAN */
1018
1019
1020
1021 if ((ra != rb) && (rd != TREG_SP) && !alias &&
1022 !y1_br && !y1_lr && !x1_add) {
1023 /*
1024 * Simple case: ra != rb and no register alias found,
1025 * and no branch or link. This will be the majority.
1026 * We can do a little better for simplae case than the
1027 * generic scheme below.
1028 */
1029 if (!load_n_store) {
1030 /*
1031 * Simple store: ra != rb, no need for scratch register.
1032 * Just store and rotate to right bytewise.
1033 */
1034 #ifdef __BIG_ENDIAN
1035 frag.insn[n++] =
1036 jit_x0_addi(ra, ra, load_store_size - 1) |
1037 jit_x1_fnop();
1038 #endif /* __BIG_ENDIAN */
1039 for (k = 0; k < load_store_size; k++) {
1040 /* Store a byte. */
1041 frag.insn[n++] =
1042 jit_x0_rotli(rb, rb, 56) |
1043 jit_x1_st1_add(ra, rb,
1044 UA_FIXUP_ADDR_DELTA);
1045 }
1046 #ifdef __BIG_ENDIAN
1047 frag.insn[n] = jit_x1_addi(ra, ra, 1);
1048 #else
1049 frag.insn[n] = jit_x1_addi(ra, ra,
1050 -1 * load_store_size);
1051 #endif /* __LITTLE_ENDIAN */
1052
1053 if (load_store_size == 8) {
1054 frag.insn[n] |= jit_x0_fnop();
1055 } else if (load_store_size == 4) {
1056 frag.insn[n] |= jit_x0_rotli(rb, rb, 32);
1057 } else { /* = 2 */
1058 frag.insn[n] |= jit_x0_rotli(rb, rb, 16);
1059 }
1060 n++;
1061 if (bundle_2_enable)
1062 frag.insn[n++] = bundle_2;
1063 frag.insn[n++] = jit_x0_fnop() | jit_x1_iret();
1064 } else {
1065 if (rd == ra) {
1066 /* Use two clobber registers: clob1/2. */
1067 frag.insn[n++] =
1068 jit_x0_addi(TREG_SP, TREG_SP, -16) |
1069 jit_x1_fnop();
1070 frag.insn[n++] =
1071 jit_x0_addi(clob1, ra, 7) |
1072 jit_x1_st_add(TREG_SP, clob1, -8);
1073 frag.insn[n++] =
1074 jit_x0_addi(clob2, ra, 0) |
1075 jit_x1_st(TREG_SP, clob2);
1076 frag.insn[n++] =
1077 jit_x0_fnop() |
1078 jit_x1_ldna(rd, ra);
1079 frag.insn[n++] =
1080 jit_x0_fnop() |
1081 jit_x1_ldna(clob1, clob1);
1082 /*
1083 * Note: we must make sure that rd must not
1084 * be sp. Recover clob1/2 from stack.
1085 */
1086 frag.insn[n++] =
1087 jit_x0_dblalign(rd, clob1, clob2) |
1088 jit_x1_ld_add(clob2, TREG_SP, 8);
1089 frag.insn[n++] =
1090 jit_x0_fnop() |
1091 jit_x1_ld_add(clob1, TREG_SP, 16);
1092 } else {
1093 /* Use one clobber register: clob1 only. */
1094 frag.insn[n++] =
1095 jit_x0_addi(TREG_SP, TREG_SP, -16) |
1096 jit_x1_fnop();
1097 frag.insn[n++] =
1098 jit_x0_addi(clob1, ra, 7) |
1099 jit_x1_st(TREG_SP, clob1);
1100 frag.insn[n++] =
1101 jit_x0_fnop() |
1102 jit_x1_ldna(rd, ra);
1103 frag.insn[n++] =
1104 jit_x0_fnop() |
1105 jit_x1_ldna(clob1, clob1);
1106 /*
1107 * Note: we must make sure that rd must not
1108 * be sp. Recover clob1 from stack.
1109 */
1110 frag.insn[n++] =
1111 jit_x0_dblalign(rd, clob1, ra) |
1112 jit_x1_ld_add(clob1, TREG_SP, 16);
1113 }
1114
1115 if (bundle_2_enable)
1116 frag.insn[n++] = bundle_2;
1117 /*
1118 * For non 8-byte load, extract corresponding bytes and
1119 * signed extension.
1120 */
1121 if (load_store_size == 4) {
1122 if (load_store_signed)
1123 frag.insn[n++] =
1124 jit_x0_bfexts(
1125 rd, rd,
1126 UA_FIXUP_BFEXT_START(4),
1127 UA_FIXUP_BFEXT_END(4)) |
1128 jit_x1_fnop();
1129 else
1130 frag.insn[n++] =
1131 jit_x0_bfextu(
1132 rd, rd,
1133 UA_FIXUP_BFEXT_START(4),
1134 UA_FIXUP_BFEXT_END(4)) |
1135 jit_x1_fnop();
1136 } else if (load_store_size == 2) {
1137 if (load_store_signed)
1138 frag.insn[n++] =
1139 jit_x0_bfexts(
1140 rd, rd,
1141 UA_FIXUP_BFEXT_START(2),
1142 UA_FIXUP_BFEXT_END(2)) |
1143 jit_x1_fnop();
1144 else
1145 frag.insn[n++] =
1146 jit_x0_bfextu(
1147 rd, rd,
1148 UA_FIXUP_BFEXT_START(2),
1149 UA_FIXUP_BFEXT_END(2)) |
1150 jit_x1_fnop();
1151 }
1152
1153 frag.insn[n++] =
1154 jit_x0_fnop() |
1155 jit_x1_iret();
1156 }
1157 } else if (!load_n_store) {
1158
1159 /*
1160 * Generic memory store cases: use 3 clobber registers.
1161 *
1162 * Alloc space for saveing clob2,1,3 on user's stack.
1163 * register clob3 points to where clob2 saved, followed by
1164 * clob1 and 3 from high to low memory.
1165 */
1166 frag.insn[n++] =
1167 jit_x0_addi(TREG_SP, TREG_SP, -32) |
1168 jit_x1_fnop();
1169 frag.insn[n++] =
1170 jit_x0_addi(clob3, TREG_SP, 16) |
1171 jit_x1_st_add(TREG_SP, clob3, 8);
1172 #ifdef __LITTLE_ENDIAN
1173 frag.insn[n++] =
1174 jit_x0_addi(clob1, ra, 0) |
1175 jit_x1_st_add(TREG_SP, clob1, 8);
1176 #else
1177 frag.insn[n++] =
1178 jit_x0_addi(clob1, ra, load_store_size - 1) |
1179 jit_x1_st_add(TREG_SP, clob1, 8);
1180 #endif
1181 if (load_store_size == 8) {
1182 /*
1183 * We save one byte a time, not for fast, but compact
1184 * code. After each store, data source register shift
1185 * right one byte. unchanged after 8 stores.
1186 */
1187 frag.insn[n++] =
1188 jit_x0_addi(clob2, TREG_ZERO, 7) |
1189 jit_x1_st_add(TREG_SP, clob2, 16);
1190 frag.insn[n++] =
1191 jit_x0_rotli(rb, rb, 56) |
1192 jit_x1_st1_add(clob1, rb, UA_FIXUP_ADDR_DELTA);
1193 frag.insn[n++] =
1194 jit_x0_addi(clob2, clob2, -1) |
1195 jit_x1_bnezt(clob2, -1);
1196 frag.insn[n++] =
1197 jit_x0_fnop() |
1198 jit_x1_addi(clob2, y1_br_reg, 0);
1199 } else if (load_store_size == 4) {
1200 frag.insn[n++] =
1201 jit_x0_addi(clob2, TREG_ZERO, 3) |
1202 jit_x1_st_add(TREG_SP, clob2, 16);
1203 frag.insn[n++] =
1204 jit_x0_rotli(rb, rb, 56) |
1205 jit_x1_st1_add(clob1, rb, UA_FIXUP_ADDR_DELTA);
1206 frag.insn[n++] =
1207 jit_x0_addi(clob2, clob2, -1) |
1208 jit_x1_bnezt(clob2, -1);
1209 /*
1210 * same as 8-byte case, but need shift another 4
1211 * byte to recover rb for 4-byte store.
1212 */
1213 frag.insn[n++] = jit_x0_rotli(rb, rb, 32) |
1214 jit_x1_addi(clob2, y1_br_reg, 0);
1215 } else { /* =2 */
1216 frag.insn[n++] =
1217 jit_x0_addi(clob2, rb, 0) |
1218 jit_x1_st_add(TREG_SP, clob2, 16);
1219 for (k = 0; k < 2; k++) {
1220 frag.insn[n++] =
1221 jit_x0_shrui(rb, rb, 8) |
1222 jit_x1_st1_add(clob1, rb,
1223 UA_FIXUP_ADDR_DELTA);
1224 }
1225 frag.insn[n++] =
1226 jit_x0_addi(rb, clob2, 0) |
1227 jit_x1_addi(clob2, y1_br_reg, 0);
1228 }
1229
1230 if (bundle_2_enable)
1231 frag.insn[n++] = bundle_2;
1232
1233 if (y1_lr) {
1234 frag.insn[n++] =
1235 jit_x0_fnop() |
1236 jit_x1_mfspr(y1_lr_reg,
1237 SPR_EX_CONTEXT_0_0);
1238 }
1239 if (y1_br) {
1240 frag.insn[n++] =
1241 jit_x0_fnop() |
1242 jit_x1_mtspr(SPR_EX_CONTEXT_0_0,
1243 clob2);
1244 }
1245 if (x1_add) {
1246 frag.insn[n++] =
1247 jit_x0_addi(ra, ra, x1_add_imm8) |
1248 jit_x1_ld_add(clob2, clob3, -8);
1249 } else {
1250 frag.insn[n++] =
1251 jit_x0_fnop() |
1252 jit_x1_ld_add(clob2, clob3, -8);
1253 }
1254 frag.insn[n++] =
1255 jit_x0_fnop() |
1256 jit_x1_ld_add(clob1, clob3, -8);
1257 frag.insn[n++] = jit_x0_fnop() | jit_x1_ld(clob3, clob3);
1258 frag.insn[n++] = jit_x0_fnop() | jit_x1_iret();
1259
1260 } else {
1261 /*
1262 * Generic memory load cases.
1263 *
1264 * Alloc space for saveing clob1,2,3 on user's stack.
1265 * register clob3 points to where clob1 saved, followed
1266 * by clob2 and 3 from high to low memory.
1267 */
1268
1269 frag.insn[n++] =
1270 jit_x0_addi(TREG_SP, TREG_SP, -32) |
1271 jit_x1_fnop();
1272 frag.insn[n++] =
1273 jit_x0_addi(clob3, TREG_SP, 16) |
1274 jit_x1_st_add(TREG_SP, clob3, 8);
1275 frag.insn[n++] =
1276 jit_x0_addi(clob2, ra, 0) |
1277 jit_x1_st_add(TREG_SP, clob2, 8);
1278
1279 if (y1_br) {
1280 frag.insn[n++] =
1281 jit_x0_addi(clob1, y1_br_reg, 0) |
1282 jit_x1_st_add(TREG_SP, clob1, 16);
1283 } else {
1284 frag.insn[n++] =
1285 jit_x0_fnop() |
1286 jit_x1_st_add(TREG_SP, clob1, 16);
1287 }
1288
1289 if (bundle_2_enable)
1290 frag.insn[n++] = bundle_2;
1291
1292 if (y1_lr) {
1293 frag.insn[n++] =
1294 jit_x0_fnop() |
1295 jit_x1_mfspr(y1_lr_reg,
1296 SPR_EX_CONTEXT_0_0);
1297 }
1298
1299 if (y1_br) {
1300 frag.insn[n++] =
1301 jit_x0_fnop() |
1302 jit_x1_mtspr(SPR_EX_CONTEXT_0_0,
1303 clob1);
1304 }
1305
1306 frag.insn[n++] =
1307 jit_x0_addi(clob1, clob2, 7) |
1308 jit_x1_ldna(rd, clob2);
1309 frag.insn[n++] =
1310 jit_x0_fnop() |
1311 jit_x1_ldna(clob1, clob1);
1312 frag.insn[n++] =
1313 jit_x0_dblalign(rd, clob1, clob2) |
1314 jit_x1_ld_add(clob1, clob3, -8);
1315 if (x1_add) {
1316 frag.insn[n++] =
1317 jit_x0_addi(ra, ra, x1_add_imm8) |
1318 jit_x1_ld_add(clob2, clob3, -8);
1319 } else {
1320 frag.insn[n++] =
1321 jit_x0_fnop() |
1322 jit_x1_ld_add(clob2, clob3, -8);
1323 }
1324
1325 frag.insn[n++] =
1326 jit_x0_fnop() |
1327 jit_x1_ld(clob3, clob3);
1328
1329 if (load_store_size == 4) {
1330 if (load_store_signed)
1331 frag.insn[n++] =
1332 jit_x0_bfexts(
1333 rd, rd,
1334 UA_FIXUP_BFEXT_START(4),
1335 UA_FIXUP_BFEXT_END(4)) |
1336 jit_x1_fnop();
1337 else
1338 frag.insn[n++] =
1339 jit_x0_bfextu(
1340 rd, rd,
1341 UA_FIXUP_BFEXT_START(4),
1342 UA_FIXUP_BFEXT_END(4)) |
1343 jit_x1_fnop();
1344 } else if (load_store_size == 2) {
1345 if (load_store_signed)
1346 frag.insn[n++] =
1347 jit_x0_bfexts(
1348 rd, rd,
1349 UA_FIXUP_BFEXT_START(2),
1350 UA_FIXUP_BFEXT_END(2)) |
1351 jit_x1_fnop();
1352 else
1353 frag.insn[n++] =
1354 jit_x0_bfextu(
1355 rd, rd,
1356 UA_FIXUP_BFEXT_START(2),
1357 UA_FIXUP_BFEXT_END(2)) |
1358 jit_x1_fnop();
1359 }
1360
1361 frag.insn[n++] = jit_x0_fnop() | jit_x1_iret();
1362 }
1363
1364 /* Max JIT bundle count is 14. */
1365 WARN_ON(n > 14);
1366
1367 if (!unexpected) {
1368 int status = 0;
1369 int idx = (regs->pc >> 3) &
1370 ((1ULL << (PAGE_SHIFT - UNALIGN_JIT_SHIFT)) - 1);
1371
1372 frag.pc = regs->pc;
1373 frag.bundle = bundle;
1374
1375 if (unaligned_printk) {
1376 pr_info("%s/%d, Unalign fixup: pc=%lx bundle=%lx %d %d %d %d %d %d %d %d\n",
1377 current->comm, current->pid,
1378 (unsigned long)frag.pc,
1379 (unsigned long)frag.bundle,
1380 (int)alias, (int)rd, (int)ra,
1381 (int)rb, (int)bundle_2_enable,
1382 (int)y1_lr, (int)y1_br, (int)x1_add);
1383
1384 for (k = 0; k < n; k += 2)
1385 pr_info("[%d] %016llx %016llx\n",
1386 k, (unsigned long long)frag.insn[k],
1387 (unsigned long long)frag.insn[k+1]);
1388 }
1389
1390 /* Swap bundle byte order for big endian sys. */
1391 #ifdef __BIG_ENDIAN
1392 frag.bundle = GX_INSN_BSWAP(frag.bundle);
1393 for (k = 0; k < n; k++)
1394 frag.insn[k] = GX_INSN_BSWAP(frag.insn[k]);
1395 #endif /* __BIG_ENDIAN */
1396
1397 status = copy_to_user((void __user *)&jit_code_area[idx],
1398 &frag, sizeof(frag));
1399 if (status) {
1400 /* Fail to copy JIT into user land. send SIGSEGV. */
1401 siginfo_t info;
1402
1403 clear_siginfo(&info);
1404 info.si_signo = SIGSEGV;
1405 info.si_code = SEGV_MAPERR;
1406 info.si_addr = (void __user *)&jit_code_area[idx];
1407
1408 pr_warn("Unalign fixup: pid=%d %s jit_code_area=%llx\n",
1409 current->pid, current->comm,
1410 (unsigned long long)&jit_code_area[idx]);
1411
1412 trace_unhandled_signal("segfault in unalign fixup",
1413 regs,
1414 (unsigned long)info.si_addr,
1415 SIGSEGV);
1416 force_sig_info(info.si_signo, &info, current);
1417 return;
1418 }
1419
1420
1421 /* Do a cheaper increment, not accurate. */
1422 unaligned_fixup_count++;
1423 __flush_icache_range((unsigned long)&jit_code_area[idx],
1424 (unsigned long)&jit_code_area[idx] +
1425 sizeof(frag));
1426
1427 /* Setup SPR_EX_CONTEXT_0_0/1 for returning to user program.*/
1428 __insn_mtspr(SPR_EX_CONTEXT_0_0, regs->pc + 8);
1429 __insn_mtspr(SPR_EX_CONTEXT_0_1, PL_ICS_EX1(USER_PL, 0));
1430
1431 /* Modify pc at the start of new JIT. */
1432 regs->pc = (unsigned long)&jit_code_area[idx].insn[0];
1433 /* Set ICS in SPR_EX_CONTEXT_K_1. */
1434 regs->ex1 = PL_ICS_EX1(USER_PL, 1);
1435 }
1436 }
1437
1438
1439 /*
1440 * C function to generate unalign data JIT. Called from unalign data
1441 * interrupt handler.
1442 *
1443 * First check if unalign fix is disabled or exception did not not come from
1444 * user space or sp register points to unalign address, if true, generate a
1445 * SIGBUS. Then map a page into user space as JIT area if it is not mapped
1446 * yet. Genenerate JIT code by calling jit_bundle_gen(). After that return
1447 * back to exception handler.
1448 *
1449 * The exception handler will "iret" to new generated JIT code after
1450 * restoring caller saved registers. In theory, the JIT code will perform
1451 * another "iret" to resume user's program.
1452 */
1453
1454 void do_unaligned(struct pt_regs *regs, int vecnum)
1455 {
1456 tilegx_bundle_bits __user *pc;
1457 tilegx_bundle_bits bundle;
1458 struct thread_info *info = current_thread_info();
1459 int align_ctl;
1460
1461 /* Checks the per-process unaligned JIT flags */
1462 align_ctl = unaligned_fixup;
1463 switch (task_thread_info(current)->align_ctl) {
1464 case PR_UNALIGN_NOPRINT:
1465 align_ctl = 1;
1466 break;
1467 case PR_UNALIGN_SIGBUS:
1468 align_ctl = 0;
1469 break;
1470 }
1471
1472 /* Enable iterrupt in order to access user land. */
1473 local_irq_enable();
1474
1475 /*
1476 * The fault came from kernel space. Two choices:
1477 * (a) unaligned_fixup < 1, we will first call get/put_user fixup
1478 * to return -EFAULT. If no fixup, simply panic the kernel.
1479 * (b) unaligned_fixup >=1, we will try to fix the unaligned access
1480 * if it was triggered by get_user/put_user() macros. Panic the
1481 * kernel if it is not fixable.
1482 */
1483
1484 if (EX1_PL(regs->ex1) != USER_PL) {
1485
1486 if (align_ctl < 1) {
1487 unaligned_fixup_count++;
1488 /* If exception came from kernel, try fix it up. */
1489 if (fixup_exception(regs)) {
1490 if (unaligned_printk)
1491 pr_info("Unalign fixup: %d %llx @%llx\n",
1492 (int)unaligned_fixup,
1493 (unsigned long long)regs->ex1,
1494 (unsigned long long)regs->pc);
1495 } else {
1496 /* Not fixable. Go panic. */
1497 panic("Unalign exception in Kernel. pc=%lx",
1498 regs->pc);
1499 }
1500 } else {
1501 /*
1502 * Try to fix the exception. If we can't, panic the
1503 * kernel.
1504 */
1505 bundle = GX_INSN_BSWAP(
1506 *((tilegx_bundle_bits *)(regs->pc)));
1507 jit_bundle_gen(regs, bundle, align_ctl);
1508 }
1509 return;
1510 }
1511
1512 /*
1513 * Fault came from user with ICS or stack is not aligned.
1514 * If so, we will trigger SIGBUS.
1515 */
1516 if ((regs->sp & 0x7) || (regs->ex1) || (align_ctl < 0)) {
1517 siginfo_t info;
1518
1519 clear_siginfo(&info);
1520 info.si_signo = SIGBUS;
1521 info.si_code = BUS_ADRALN;
1522 info.si_addr = (unsigned char __user *)0;
1523
1524 if (unaligned_printk)
1525 pr_info("Unalign fixup: %d %llx @%llx\n",
1526 (int)unaligned_fixup,
1527 (unsigned long long)regs->ex1,
1528 (unsigned long long)regs->pc);
1529
1530 unaligned_fixup_count++;
1531
1532 trace_unhandled_signal("unaligned fixup trap", regs, 0, SIGBUS);
1533 force_sig_info(info.si_signo, &info, current);
1534 return;
1535 }
1536
1537
1538 /* Read the bundle caused the exception! */
1539 pc = (tilegx_bundle_bits __user *)(regs->pc);
1540 if (get_user(bundle, pc) != 0) {
1541 /* Probably never be here since pc is valid user address.*/
1542 siginfo_t info;
1543
1544 clear_siginfo(&info);
1545 info.si_signo = SIGSEGV;
1546 info.si_code = SEGV_MAPERR;
1547 info.si_addr = (void __user *)pc;
1548
1549 pr_err("Couldn't read instruction at %p trying to step\n", pc);
1550 trace_unhandled_signal("segfault in unalign fixup", regs,
1551 (unsigned long)info.si_addr, SIGSEGV);
1552 force_sig_info(info.si_signo, &info, current);
1553 return;
1554 }
1555
1556 if (!info->unalign_jit_base) {
1557 void __user *user_page;
1558
1559 /*
1560 * Allocate a page in userland.
1561 * For 64-bit processes we try to place the mapping far
1562 * from anything else that might be going on (specifically
1563 * 64 GB below the top of the user address space). If it
1564 * happens not to be possible to put it there, it's OK;
1565 * the kernel will choose another location and we'll
1566 * remember it for later.
1567 */
1568 if (is_compat_task())
1569 user_page = NULL;
1570 else
1571 user_page = (void __user *)(TASK_SIZE - (1UL << 36)) +
1572 (current->pid << PAGE_SHIFT);
1573
1574 user_page = (void __user *) vm_mmap(NULL,
1575 (unsigned long)user_page,
1576 PAGE_SIZE,
1577 PROT_EXEC | PROT_READ |
1578 PROT_WRITE,
1579 #ifdef CONFIG_HOMECACHE
1580 MAP_CACHE_HOME_TASK |
1581 #endif
1582 MAP_PRIVATE |
1583 MAP_ANONYMOUS,
1584 0);
1585
1586 if (IS_ERR((void __force *)user_page)) {
1587 pr_err("Out of kernel pages trying do_mmap\n");
1588 return;
1589 }
1590
1591 /* Save the address in the thread_info struct */
1592 info->unalign_jit_base = user_page;
1593 if (unaligned_printk)
1594 pr_info("Unalign bundle: %d:%d, allocate page @%llx\n",
1595 raw_smp_processor_id(), current->pid,
1596 (unsigned long long)user_page);
1597 }
1598
1599 /* Generate unalign JIT */
1600 jit_bundle_gen(regs, GX_INSN_BSWAP(bundle), align_ctl);
1601 }
1602
1603 #endif /* __tilegx__ */
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