arch/unicore32/kernel/pci.c

   1 /*
   2  * linux/arch/unicore32/kernel/pci.c
   3  *
   4  * Code specific to PKUnity SoC and UniCore ISA
   5  *
   6  * Copyright (C) 2001-2010 GUAN Xue-tao
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  *  PCI bios-type initialisation for PCI machines
  13  *
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/pci.h>
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 static int debug_pci;
  24
  25 #define CONFIG_CMD(bus, devfn, where)   \
  26         (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
  27
  28 static int
  29 puv3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  30                         int size, u32 *value)
  31 {
  32         writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR);
  33         switch (size) {
  34         case 1:
  35                 *value = (readl(PCICFG_DATA) >> ((where & 3) * 8)) & 0xFF;
  36                 break;
  37         case 2:
  38                 *value = (readl(PCICFG_DATA) >> ((where & 2) * 8)) & 0xFFFF;
  39                 break;
  40         case 4:
  41                 *value = readl(PCICFG_DATA);
  42                 break;
  43         }
  44         return PCIBIOS_SUCCESSFUL;
  45 }
  46
  47 static int
  48 puv3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  49                         int size, u32 value)
  50 {
  51         writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR);
  52         switch (size) {
  53         case 1:
  54                 writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8))
  55                         | FIELD(value, 8, (where&3)*8), PCICFG_DATA);
  56                 break;
  57         case 2:
  58                 writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8))
  59                         | FIELD(value, 16, (where&2)*8), PCICFG_DATA);
  60                 break;
  61         case 4:
  62                 writel(value, PCICFG_DATA);
  63                 break;
  64         }
  65         return PCIBIOS_SUCCESSFUL;
  66 }
  67
  68 struct pci_ops pci_puv3_ops = {
  69         .read  = puv3_read_config,
  70         .write = puv3_write_config,
  71 };
  72
  73 void pci_puv3_preinit(void)
  74 {
  75         printk(KERN_DEBUG "PCI: PKUnity PCI Controller Initializing ...\n");
  76         /* config PCI bridge base */
  77         writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE);
  78
  79         writel(0, PCIBRI_AHBCTL0);
  80         writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0);
  81         writel(0xFFFF0000, PCIBRI_AHBAMR0);
  82         writel(0, PCIBRI_AHBTAR0);
  83
  84         writel(PCIBRI_CTLx_AT, PCIBRI_AHBCTL1);
  85         writel(io_v2p(PKUNITY_PCILIO_BASE) | PCIBRI_BARx_IO, PCIBRI_AHBBAR1);
  86         writel(0xFFFF0000, PCIBRI_AHBAMR1);
  87         writel(0x00000000, PCIBRI_AHBTAR1);
  88
  89         writel(PCIBRI_CTLx_PREF, PCIBRI_AHBCTL2);
  90         writel(io_v2p(PKUNITY_PCIMEM_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR2);
  91         writel(0xF8000000, PCIBRI_AHBAMR2);
  92         writel(0, PCIBRI_AHBTAR2);
  93
  94         writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_BAR1);
  95
  96         writel(PCIBRI_CTLx_AT | PCIBRI_CTLx_PREF, PCIBRI_PCICTL0);
  97         writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_PCIBAR0);
  98         writel(0xF8000000, PCIBRI_PCIAMR0);
  99         writel(PKUNITY_SDRAM_BASE, PCIBRI_PCITAR0);
 100
 101         writel(readl(PCIBRI_CMD) | PCIBRI_CMD_IO | PCIBRI_CMD_MEM, PCIBRI_CMD);
 102 }
 103
 104 static int pci_puv3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 105 {
 106         if (dev->bus->number == 0) {
 107 #ifdef CONFIG_ARCH_FPGA /* 4 pci slots */
 108                 if      (dev->devfn == 0x00)
 109                         return IRQ_PCIINTA;
 110                 else if (dev->devfn == 0x08)
 111                         return IRQ_PCIINTB;
 112                 else if (dev->devfn == 0x10)
 113                         return IRQ_PCIINTC;
 114                 else if (dev->devfn == 0x18)
 115                         return IRQ_PCIINTD;
 116 #endif
 117 #ifdef CONFIG_PUV3_DB0913 /* 3 pci slots */
 118                 if      (dev->devfn == 0x30)
 119                         return IRQ_PCIINTB;
 120                 else if (dev->devfn == 0x60)
 121                         return IRQ_PCIINTC;
 122                 else if (dev->devfn == 0x58)
 123                         return IRQ_PCIINTD;
 124 #endif
 125 #if     defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919)
 126                 /* only support 2 pci devices */
 127                 if      (dev->devfn == 0x00)
 128                         return IRQ_PCIINTC; /* sata */
 129 #endif
 130         }
 131         return -1;
 132 }
 133
 134 /*
 135  * Only first 128MB of memory can be accessed via PCI.
 136  * We use GFP_DMA to allocate safe buffers to do map/unmap.
 137  * This is really ugly and we need a better way of specifying
 138  * DMA-capable regions of memory.
 139  */
 140 void __init puv3_pci_adjust_zones(unsigned long *zone_size,
 141         unsigned long *zhole_size)
 142 {
 143         unsigned int sz = SZ_128M >> PAGE_SHIFT;
 144
 145         /*
 146          * Only adjust if > 128M on current system
 147          */
 148         if (zone_size[0] <= sz)
 149                 return;
 150
 151         zone_size[1] = zone_size[0] - sz;
 152         zone_size[0] = sz;
 153         zhole_size[1] = zhole_size[0];
 154         zhole_size[0] = 0;
 155 }
 156
 157 /*
 158  * If the bus contains any of these devices, then we must not turn on
 159  * parity checking of any kind.
 160  */
 161 static inline int pdev_bad_for_parity(struct pci_dev *dev)
 162 {
 163         return 0;
 164 }
 165
 166 /*
 167  * pcibios_fixup_bus - Called after each bus is probed,
 168  * but before its children are examined.
 169  */
 170 void pcibios_fixup_bus(struct pci_bus *bus)
 171 {
 172         struct pci_dev *dev;
 173         u16 features = PCI_COMMAND_SERR
 174                 | PCI_COMMAND_PARITY
 175                 | PCI_COMMAND_FAST_BACK;
 176
 177         bus->resource[0] = &ioport_resource;
 178         bus->resource[1] = &iomem_resource;
 179
 180         /*
 181          * Walk the devices on this bus, working out what we can
 182          * and can't support.
 183          */
 184         list_for_each_entry(dev, &bus->devices, bus_list) {
 185                 u16 status;
 186
 187                 pci_read_config_word(dev, PCI_STATUS, &status);
 188
 189                 /*
 190                  * If any device on this bus does not support fast back
 191                  * to back transfers, then the bus as a whole is not able
 192                  * to support them.  Having fast back to back transfers
 193                  * on saves us one PCI cycle per transaction.
 194                  */
 195                 if (!(status & PCI_STATUS_FAST_BACK))
 196                         features &= ~PCI_COMMAND_FAST_BACK;
 197
 198                 if (pdev_bad_for_parity(dev))
 199                         features &= ~(PCI_COMMAND_SERR
 200                                         | PCI_COMMAND_PARITY);
 201
 202                 switch (dev->class >> 8) {
 203                 case PCI_CLASS_BRIDGE_PCI:
 204                         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
 205                         status |= PCI_BRIDGE_CTL_PARITY
 206                                 | PCI_BRIDGE_CTL_MASTER_ABORT;
 207                         status &= ~(PCI_BRIDGE_CTL_BUS_RESET
 208                                 | PCI_BRIDGE_CTL_FAST_BACK);
 209                         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
 210                         break;
 211
 212                 case PCI_CLASS_BRIDGE_CARDBUS:
 213                         pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL,
 214                                         &status);
 215                         status |= PCI_CB_BRIDGE_CTL_PARITY
 216                                 | PCI_CB_BRIDGE_CTL_MASTER_ABORT;
 217                         pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL,
 218                                         status);
 219                         break;
 220                 }
 221         }
 222
 223         /*
 224          * Now walk the devices again, this time setting them up.
 225          */
 226         list_for_each_entry(dev, &bus->devices, bus_list) {
 227                 u16 cmd;
 228
 229                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
 230                 cmd |= features;
 231                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 232
 233                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
 234                                       L1_CACHE_BYTES >> 2);
 235         }
 236
 237         /*
 238          * Propagate the flags to the PCI bridge.
 239          */
 240         if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
 241                 if (features & PCI_COMMAND_FAST_BACK)
 242                         bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
 243                 if (features & PCI_COMMAND_PARITY)
 244                         bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
 245         }
 246
 247         /*
 248          * Report what we did for this bus
 249          */
 250         printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
 251                 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
 252 }
 253 EXPORT_SYMBOL(pcibios_fixup_bus);
 254
 255 static struct resource busn_resource = {
 256         .name   = "PCI busn",
 257         .start  = 0,
 258         .end    = 255,
 259         .flags  = IORESOURCE_BUS,
 260 };
 261
 262 static int __init pci_common_init(void)
 263 {
 264         struct pci_bus *puv3_bus;
 265         struct pci_host_bridge *bridge;
 266         int ret;
 267
 268         bridge = pci_alloc_host_bridge(0);
 269         if (!bridge)
 270                 return -ENOMEM;
 271
 272         pci_puv3_preinit();
 273
 274         pci_add_resource(&bridge->windows, &ioport_resource);
 275         pci_add_resource(&bridge->windows, &iomem_resource);
 276         pci_add_resource(&bridge->windows, &busn_resource);
 277         bridge->sysdata = NULL;
 278         bridge->busnr = 0;
 279         bridge->ops = &pci_puv3_ops;
 280         bridge->swizzle_irq = pci_common_swizzle;
 281         bridge->map_irq = pci_puv3_map_irq;
 282
 283         /* Scan our single hose.  */
 284         ret = pci_scan_root_bus_bridge(bridge);
 285         if (ret) {
 286                 pci_free_host_bridge(bridge);
 287                 return;
 288         }
 289
 290         puv3_bus = bridge->bus;
 291
 292         if (!puv3_bus)
 293                 panic("PCI: unable to scan bus!");
 294
 295         pci_bus_size_bridges(puv3_bus);
 296         pci_bus_assign_resources(puv3_bus);
 297         pci_bus_add_devices(puv3_bus);
 298         return 0;
 299 }
 300 subsys_initcall(pci_common_init);
 301
 302 char * __init pcibios_setup(char *str)
 303 {
 304         if (!strcmp(str, "debug")) {
 305                 debug_pci = 1;
 306                 return NULL;
 307         }
 308         return str;
 309 }
 310
 311 void pcibios_set_master(struct pci_dev *dev)
 312 {
 313         /* No special bus mastering setup handling */
 314 }
 315
 316 /*
 317  * From arch/i386/kernel/pci-i386.c:
 318  *
 319  * We need to avoid collisions with `mirrored' VGA ports
 320  * and other strange ISA hardware, so we always want the
 321  * addresses to be allocated in the 0x000-0x0ff region
 322  * modulo 0x400.
 323  *
 324  * Why? Because some silly external IO cards only decode
 325  * the low 10 bits of the IO address. The 0x00-0xff region
 326  * is reserved for motherboard devices that decode all 16
 327  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 328  * but we want to try to avoid allocating at 0x2900-0x2bff
 329  * which might be mirrored at 0x0100-0x03ff..
 330  */
 331 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 332                                 resource_size_t size, resource_size_t align)
 333 {
 334         resource_size_t start = res->start;
 335
 336         if (res->flags & IORESOURCE_IO && start & 0x300)
 337                 start = (start + 0x3ff) & ~0x3ff;
 338
 339         start = (start + align - 1) & ~(align - 1);
 340
 341         return start;
 342 }
 343
 344 /**
 345  * pcibios_enable_device - Enable I/O and memory.
 346  * @dev: PCI device to be enabled
 347  */
 348 int pcibios_enable_device(struct pci_dev *dev, int mask)
 349 {
 350         u16 cmd, old_cmd;
 351         int idx;
 352         struct resource *r;
 353
 354         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 355         old_cmd = cmd;
 356         for (idx = 0; idx < 6; idx++) {
 357                 /* Only set up the requested stuff */
 358                 if (!(mask & (1 << idx)))
 359                         continue;
 360
 361                 r = dev->resource + idx;
 362                 if (!r->start && r->end) {
 363                         printk(KERN_ERR "PCI: Device %s not available because"
 364                                " of resource collisions\n", pci_name(dev));
 365                         return -EINVAL;
 366                 }
 367                 if (r->flags & IORESOURCE_IO)
 368                         cmd |= PCI_COMMAND_IO;
 369                 if (r->flags & IORESOURCE_MEM)
 370                         cmd |= PCI_COMMAND_MEMORY;
 371         }
 372
 373         /*
 374          * Bridges (eg, cardbus bridges) need to be fully enabled
 375          */
 376         if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
 377                 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 378
 379         if (cmd != old_cmd) {
 380                 printk("PCI: enabling device %s (%04x -> %04x)\n",
 381                        pci_name(dev), old_cmd, cmd);
 382                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 383         }
 384         return 0;
 385 }