| blob | 805f52703ee3377f88180eb3467a34bf2bc40e87 |
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * linux/arch/x86_64/entry.S
4 *
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
8 *
9 * entry.S contains the system-call and fault low-level handling routines.
10 *
11 * Some of this is documented in Documentation/x86/entry_64.txt
12 *
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
16 *
17 * Some macro usage:
18 * - ENTRY/END: Define functions in the symbol table.
19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging.
20 * - idtentry: Define exception entry points.
21 */
22 #include <linux/linkage.h>
23 #include <asm/segment.h>
24 #include <asm/cache.h>
25 #include <asm/errno.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/msr.h>
28 #include <asm/unistd.h>
29 #include <asm/thread_info.h>
30 #include <asm/hw_irq.h>
31 #include <asm/page_types.h>
32 #include <asm/irqflags.h>
33 #include <asm/paravirt.h>
34 #include <asm/percpu.h>
35 #include <asm/asm.h>
36 #include <asm/smap.h>
37 #include <asm/pgtable_types.h>
38 #include <asm/export.h>
39 #include <asm/frame.h>
40 #include <asm/nospec-branch.h>
41 #include <linux/err.h>
43 #include "calling.h"
45 .code64
46 .section .entry.text, "ax"
48 #ifdef CONFIG_PARAVIRT
49 ENTRY(native_usergs_sysret64)
50 UNWIND_HINT_EMPTY
51 swapgs
52 sysretq
53 END(native_usergs_sysret64)
54 #endif /* CONFIG_PARAVIRT */
56 .macro TRACE_IRQS_FLAGS flags:req
57 #ifdef CONFIG_TRACE_IRQFLAGS
58 btl $9, \flags /* interrupts off? */
59 jnc 1f
60 TRACE_IRQS_ON
61 1:
62 #endif
63 .endm
65 .macro TRACE_IRQS_IRETQ
66 TRACE_IRQS_FLAGS EFLAGS(%rsp)
67 .endm
69 /*
70 * When dynamic function tracer is enabled it will add a breakpoint
71 * to all locations that it is about to modify, sync CPUs, update
72 * all the code, sync CPUs, then remove the breakpoints. In this time
73 * if lockdep is enabled, it might jump back into the debug handler
74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
75 *
76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
77 * make sure the stack pointer does not get reset back to the top
78 * of the debug stack, and instead just reuses the current stack.
79 */
80 #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
82 .macro TRACE_IRQS_OFF_DEBUG
83 call debug_stack_set_zero
84 TRACE_IRQS_OFF
85 call debug_stack_reset
86 .endm
88 .macro TRACE_IRQS_ON_DEBUG
89 call debug_stack_set_zero
90 TRACE_IRQS_ON
91 call debug_stack_reset
92 .endm
94 .macro TRACE_IRQS_IRETQ_DEBUG
95 bt $9, EFLAGS(%rsp) /* interrupts off? */
96 jnc 1f
97 TRACE_IRQS_ON_DEBUG
98 1:
99 .endm
101 #else
102 # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
103 # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
104 # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
105 #endif
107 /*
108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
109 *
110 * This is the only entry point used for 64-bit system calls. The
111 * hardware interface is reasonably well designed and the register to
112 * argument mapping Linux uses fits well with the registers that are
113 * available when SYSCALL is used.
114 *
115 * SYSCALL instructions can be found inlined in libc implementations as
116 * well as some other programs and libraries. There are also a handful
117 * of SYSCALL instructions in the vDSO used, for example, as a
118 * clock_gettimeofday fallback.
119 *
120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
121 * then loads new ss, cs, and rip from previously programmed MSRs.
122 * rflags gets masked by a value from another MSR (so CLD and CLAC
123 * are not needed). SYSCALL does not save anything on the stack
124 * and does not change rsp.
125 *
126 * Registers on entry:
127 * rax system call number
128 * rcx return address
129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
130 * rdi arg0
131 * rsi arg1
132 * rdx arg2
133 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
134 * r8 arg4
135 * r9 arg5
136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
137 *
138 * Only called from user space.
139 *
140 * When user can change pt_regs->foo always force IRET. That is because
141 * it deals with uncanonical addresses better. SYSRET has trouble
142 * with them due to bugs in both AMD and Intel CPUs.
143 */
145 .pushsection .entry_trampoline, "ax"
147 /*
148 * The code in here gets remapped into cpu_entry_area's trampoline. This means
149 * that the assembler and linker have the wrong idea as to where this code
150 * lives (and, in fact, it's mapped more than once, so it's not even at a
151 * fixed address). So we can't reference any symbols outside the entry
152 * trampoline and expect it to work.
153 *
154 * Instead, we carefully abuse %rip-relative addressing.
155 * _entry_trampoline(%rip) refers to the start of the remapped) entry
156 * trampoline. We can thus find cpu_entry_area with this macro:
157 */
159 #define CPU_ENTRY_AREA \
160 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip)
162 /* The top word of the SYSENTER stack is hot and is usable as scratch space. */
163 #define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \
164 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA
166 ENTRY(entry_SYSCALL_64_trampoline)
167 UNWIND_HINT_EMPTY
168 swapgs
170 /* Stash the user RSP. */
171 movq %rsp, RSP_SCRATCH
173 /* Note: using %rsp as a scratch reg. */
174 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
176 /* Load the top of the task stack into RSP */
177 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp
179 /* Start building the simulated IRET frame. */
180 pushq $__USER_DS /* pt_regs->ss */
181 pushq RSP_SCRATCH /* pt_regs->sp */
182 pushq %r11 /* pt_regs->flags */
183 pushq $__USER_CS /* pt_regs->cs */
184 pushq %rcx /* pt_regs->ip */
186 /*
187 * x86 lacks a near absolute jump, and we can't jump to the real
188 * entry text with a relative jump. We could push the target
189 * address and then use retq, but this destroys the pipeline on
190 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead,
191 * spill RDI and restore it in a second-stage trampoline.
192 */
193 pushq %rdi
194 movq $entry_SYSCALL_64_stage2, %rdi
195 JMP_NOSPEC %rdi
196 END(entry_SYSCALL_64_trampoline)
198 .popsection
200 ENTRY(entry_SYSCALL_64_stage2)
201 UNWIND_HINT_EMPTY
202 popq %rdi
203 jmp entry_SYSCALL_64_after_hwframe
204 END(entry_SYSCALL_64_stage2)
206 ENTRY(entry_SYSCALL_64)
207 UNWIND_HINT_EMPTY
208 /*
209 * Interrupts are off on entry.
210 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
211 * it is too small to ever cause noticeable irq latency.
212 */
214 swapgs
215 /*
216 * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it
217 * is not required to switch CR3.
218 */
219 movq %rsp, PER_CPU_VAR(rsp_scratch)
220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
222 /* Construct struct pt_regs on stack */
223 pushq $__USER_DS /* pt_regs->ss */
224 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */
225 pushq %r11 /* pt_regs->flags */
226 pushq $__USER_CS /* pt_regs->cs */
227 pushq %rcx /* pt_regs->ip */
228 GLOBAL(entry_SYSCALL_64_after_hwframe)
229 pushq %rax /* pt_regs->orig_ax */
231 PUSH_AND_CLEAR_REGS rax=$-ENOSYS
233 TRACE_IRQS_OFF
235 /* IRQs are off. */
236 movq %rsp, %rdi
237 call do_syscall_64 /* returns with IRQs disabled */
239 TRACE_IRQS_IRETQ /* we're about to change IF */
241 /*
242 * Try to use SYSRET instead of IRET if we're returning to
243 * a completely clean 64-bit userspace context. If we're not,
244 * go to the slow exit path.
245 */
246 movq RCX(%rsp), %rcx
247 movq RIP(%rsp), %r11
249 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
250 jne swapgs_restore_regs_and_return_to_usermode
252 /*
253 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
254 * in kernel space. This essentially lets the user take over
255 * the kernel, since userspace controls RSP.
256 *
257 * If width of "canonical tail" ever becomes variable, this will need
258 * to be updated to remain correct on both old and new CPUs.
259 *
260 * Change top bits to match most significant bit (47th or 56th bit
261 * depending on paging mode) in the address.
262 */
263 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
264 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
266 /* If this changed %rcx, it was not canonical */
267 cmpq %rcx, %r11
268 jne swapgs_restore_regs_and_return_to_usermode
270 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
271 jne swapgs_restore_regs_and_return_to_usermode
273 movq R11(%rsp), %r11
274 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
275 jne swapgs_restore_regs_and_return_to_usermode
277 /*
278 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
279 * restore RF properly. If the slowpath sets it for whatever reason, we
280 * need to restore it correctly.
281 *
282 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
283 * trap from userspace immediately after SYSRET. This would cause an
284 * infinite loop whenever #DB happens with register state that satisfies
285 * the opportunistic SYSRET conditions. For example, single-stepping
286 * this user code:
287 *
288 * movq $stuck_here, %rcx
289 * pushfq
290 * popq %r11
291 * stuck_here:
292 *
293 * would never get past 'stuck_here'.
294 */
295 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
296 jnz swapgs_restore_regs_and_return_to_usermode
298 /* nothing to check for RSP */
300 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
301 jne swapgs_restore_regs_and_return_to_usermode
303 /*
304 * We win! This label is here just for ease of understanding
305 * perf profiles. Nothing jumps here.
306 */
307 syscall_return_via_sysret:
308 /* rcx and r11 are already restored (see code above) */
309 UNWIND_HINT_EMPTY
310 POP_REGS pop_rdi=0 skip_r11rcx=1
312 /*
313 * Now all regs are restored except RSP and RDI.
314 * Save old stack pointer and switch to trampoline stack.
315 */
316 movq %rsp, %rdi
317 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
319 pushq RSP-RDI(%rdi) /* RSP */
320 pushq (%rdi) /* RDI */
322 /*
323 * We are on the trampoline stack. All regs except RDI are live.
324 * We can do future final exit work right here.
325 */
326 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
328 popq %rdi
329 popq %rsp
330 USERGS_SYSRET64
331 END(entry_SYSCALL_64)
333 /*
334 * %rdi: prev task
335 * %rsi: next task
336 */
337 ENTRY(__switch_to_asm)
338 UNWIND_HINT_FUNC
339 /*
340 * Save callee-saved registers
341 * This must match the order in inactive_task_frame
342 */
343 pushq %rbp
344 pushq %rbx
345 pushq %r12
346 pushq %r13
347 pushq %r14
348 pushq %r15
350 /* switch stack */
351 movq %rsp, TASK_threadsp(%rdi)
352 movq TASK_threadsp(%rsi), %rsp
354 #ifdef CONFIG_CC_STACKPROTECTOR
355 movq TASK_stack_canary(%rsi), %rbx
356 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
357 #endif
359 #ifdef CONFIG_RETPOLINE
360 /*
361 * When switching from a shallower to a deeper call stack
362 * the RSB may either underflow or use entries populated
363 * with userspace addresses. On CPUs where those concerns
364 * exist, overwrite the RSB with entries which capture
365 * speculative execution to prevent attack.
366 */
367 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
368 #endif
370 /* restore callee-saved registers */
371 popq %r15
372 popq %r14
373 popq %r13
374 popq %r12
375 popq %rbx
376 popq %rbp
378 jmp __switch_to
379 END(__switch_to_asm)
381 /*
382 * A newly forked process directly context switches into this address.
383 *
384 * rax: prev task we switched from
385 * rbx: kernel thread func (NULL for user thread)
386 * r12: kernel thread arg
387 */
388 ENTRY(ret_from_fork)
389 UNWIND_HINT_EMPTY
390 movq %rax, %rdi
391 call schedule_tail /* rdi: 'prev' task parameter */
393 testq %rbx, %rbx /* from kernel_thread? */
394 jnz 1f /* kernel threads are uncommon */
396 2:
397 UNWIND_HINT_REGS
398 movq %rsp, %rdi
399 call syscall_return_slowpath /* returns with IRQs disabled */
400 TRACE_IRQS_ON /* user mode is traced as IRQS on */
401 jmp swapgs_restore_regs_and_return_to_usermode
403 1:
404 /* kernel thread */
405 movq %r12, %rdi
406 CALL_NOSPEC %rbx
407 /*
408 * A kernel thread is allowed to return here after successfully
409 * calling do_execve(). Exit to userspace to complete the execve()
410 * syscall.
411 */
412 movq $0, RAX(%rsp)
413 jmp 2b
414 END(ret_from_fork)
416 /*
417 * Build the entry stubs with some assembler magic.
418 * We pack 1 stub into every 8-byte block.
419 */
420 .align 8
421 ENTRY(irq_entries_start)
422 vector=FIRST_EXTERNAL_VECTOR
423 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
424 UNWIND_HINT_IRET_REGS
425 pushq $(~vector+0x80) /* Note: always in signed byte range */
426 jmp common_interrupt
427 .align 8
428 vector=vector+1
429 .endr
430 END(irq_entries_start)
432 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
433 #ifdef CONFIG_DEBUG_ENTRY
434 pushq %rax
435 SAVE_FLAGS(CLBR_RAX)
436 testl $X86_EFLAGS_IF, %eax
437 jz .Lokay_\@
438 ud2
439 .Lokay_\@:
440 popq %rax
441 #endif
442 .endm
444 /*
445 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers
446 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone.
447 * Requires kernel GSBASE.
448 *
449 * The invariant is that, if irq_count != -1, then the IRQ stack is in use.
450 */
451 .macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0
452 DEBUG_ENTRY_ASSERT_IRQS_OFF
454 .if \save_ret
455 /*
456 * If save_ret is set, the original stack contains one additional
457 * entry -- the return address. Therefore, move the address one
458 * entry below %rsp to \old_rsp.
459 */
460 leaq 8(%rsp), \old_rsp
461 .else
462 movq %rsp, \old_rsp
463 .endif
465 .if \regs
466 UNWIND_HINT_REGS base=\old_rsp
467 .endif
469 incl PER_CPU_VAR(irq_count)
470 jnz .Lirq_stack_push_old_rsp_\@
472 /*
473 * Right now, if we just incremented irq_count to zero, we've
474 * claimed the IRQ stack but we haven't switched to it yet.
475 *
476 * If anything is added that can interrupt us here without using IST,
477 * it must be *extremely* careful to limit its stack usage. This
478 * could include kprobes and a hypothetical future IST-less #DB
479 * handler.
480 *
481 * The OOPS unwinder relies on the word at the top of the IRQ
482 * stack linking back to the previous RSP for the entire time we're
483 * on the IRQ stack. For this to work reliably, we need to write
484 * it before we actually move ourselves to the IRQ stack.
485 */
487 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8)
488 movq PER_CPU_VAR(irq_stack_ptr), %rsp
490 #ifdef CONFIG_DEBUG_ENTRY
491 /*
492 * If the first movq above becomes wrong due to IRQ stack layout
493 * changes, the only way we'll notice is if we try to unwind right
494 * here. Assert that we set up the stack right to catch this type
495 * of bug quickly.
496 */
497 cmpq -8(%rsp), \old_rsp
498 je .Lirq_stack_okay\@
499 ud2
500 .Lirq_stack_okay\@:
501 #endif
503 .Lirq_stack_push_old_rsp_\@:
504 pushq \old_rsp
506 .if \regs
507 UNWIND_HINT_REGS indirect=1
508 .endif
510 .if \save_ret
511 /*
512 * Push the return address to the stack. This return address can
513 * be found at the "real" original RSP, which was offset by 8 at
514 * the beginning of this macro.
515 */
516 pushq -8(\old_rsp)
517 .endif
518 .endm
520 /*
521 * Undoes ENTER_IRQ_STACK.
522 */
523 .macro LEAVE_IRQ_STACK regs=1
524 DEBUG_ENTRY_ASSERT_IRQS_OFF
525 /* We need to be off the IRQ stack before decrementing irq_count. */
526 popq %rsp
528 .if \regs
529 UNWIND_HINT_REGS
530 .endif
532 /*
533 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming
534 * the irq stack but we're not on it.
535 */
537 decl PER_CPU_VAR(irq_count)
538 .endm
540 /*
541 * Interrupt entry helper function.
542 *
543 * Entry runs with interrupts off. Stack layout at entry:
544 * +----------------------------------------------------+
545 * | regs->ss |
546 * | regs->rsp |
547 * | regs->eflags |
548 * | regs->cs |
549 * | regs->ip |
550 * +----------------------------------------------------+
551 * | regs->orig_ax = ~(interrupt number) |
552 * +----------------------------------------------------+
553 * | return address |
554 * +----------------------------------------------------+
555 */
556 ENTRY(interrupt_entry)
557 UNWIND_HINT_FUNC
558 ASM_CLAC
559 cld
561 testb $3, CS-ORIG_RAX+8(%rsp)
562 jz 1f
563 SWAPGS
565 /*
566 * Switch to the thread stack. The IRET frame and orig_ax are
567 * on the stack, as well as the return address. RDI..R12 are
568 * not (yet) on the stack and space has not (yet) been
569 * allocated for them.
570 */
571 pushq %rdi
573 /* Need to switch before accessing the thread stack. */
574 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
575 movq %rsp, %rdi
576 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
578 /*
579 * We have RDI, return address, and orig_ax on the stack on
580 * top of the IRET frame. That means offset=24
581 */
582 UNWIND_HINT_IRET_REGS base=%rdi offset=24
584 pushq 7*8(%rdi) /* regs->ss */
585 pushq 6*8(%rdi) /* regs->rsp */
586 pushq 5*8(%rdi) /* regs->eflags */
587 pushq 4*8(%rdi) /* regs->cs */
588 pushq 3*8(%rdi) /* regs->ip */
589 pushq 2*8(%rdi) /* regs->orig_ax */
590 pushq 8(%rdi) /* return address */
591 UNWIND_HINT_FUNC
593 movq (%rdi), %rdi
594 1:
596 PUSH_AND_CLEAR_REGS save_ret=1
597 ENCODE_FRAME_POINTER 8
599 testb $3, CS+8(%rsp)
600 jz 1f
602 /*
603 * IRQ from user mode.
604 *
605 * We need to tell lockdep that IRQs are off. We can't do this until
606 * we fix gsbase, and we should do it before enter_from_user_mode
607 * (which can take locks). Since TRACE_IRQS_OFF is idempotent,
608 * the simplest way to handle it is to just call it twice if
609 * we enter from user mode. There's no reason to optimize this since
610 * TRACE_IRQS_OFF is a no-op if lockdep is off.
611 */
612 TRACE_IRQS_OFF
614 CALL_enter_from_user_mode
616 1:
617 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1
618 /* We entered an interrupt context - irqs are off: */
619 TRACE_IRQS_OFF
621 ret
622 END(interrupt_entry)
625 /* Interrupt entry/exit. */
627 /*
628 * The interrupt stubs push (~vector+0x80) onto the stack and
629 * then jump to common_interrupt.
630 */
631 .p2align CONFIG_X86_L1_CACHE_SHIFT
632 common_interrupt:
633 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
634 call interrupt_entry
635 UNWIND_HINT_REGS indirect=1
636 call do_IRQ /* rdi points to pt_regs */
637 /* 0(%rsp): old RSP */
638 ret_from_intr:
639 DISABLE_INTERRUPTS(CLBR_ANY)
640 TRACE_IRQS_OFF
642 LEAVE_IRQ_STACK
644 testb $3, CS(%rsp)
645 jz retint_kernel
647 /* Interrupt came from user space */
648 GLOBAL(retint_user)
649 mov %rsp,%rdi
650 call prepare_exit_to_usermode
651 TRACE_IRQS_IRETQ
653 GLOBAL(swapgs_restore_regs_and_return_to_usermode)
654 #ifdef CONFIG_DEBUG_ENTRY
655 /* Assert that pt_regs indicates user mode. */
656 testb $3, CS(%rsp)
657 jnz 1f
658 ud2
659 1:
660 #endif
661 POP_REGS pop_rdi=0
663 /*
664 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
665 * Save old stack pointer and switch to trampoline stack.
666 */
667 movq %rsp, %rdi
668 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
670 /* Copy the IRET frame to the trampoline stack. */
671 pushq 6*8(%rdi) /* SS */
672 pushq 5*8(%rdi) /* RSP */
673 pushq 4*8(%rdi) /* EFLAGS */
674 pushq 3*8(%rdi) /* CS */
675 pushq 2*8(%rdi) /* RIP */
677 /* Push user RDI on the trampoline stack. */
678 pushq (%rdi)
680 /*
681 * We are on the trampoline stack. All regs except RDI are live.
682 * We can do future final exit work right here.
683 */
685 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
687 /* Restore RDI. */
688 popq %rdi
689 SWAPGS
690 INTERRUPT_RETURN
693 /* Returning to kernel space */
694 retint_kernel:
695 #ifdef CONFIG_PREEMPT
696 /* Interrupts are off */
697 /* Check if we need preemption */
698 bt $9, EFLAGS(%rsp) /* were interrupts off? */
699 jnc 1f
700 0: cmpl $0, PER_CPU_VAR(__preempt_count)
701 jnz 1f
702 call preempt_schedule_irq
703 jmp 0b
704 1:
705 #endif
706 /*
707 * The iretq could re-enable interrupts:
708 */
709 TRACE_IRQS_IRETQ
711 GLOBAL(restore_regs_and_return_to_kernel)
712 #ifdef CONFIG_DEBUG_ENTRY
713 /* Assert that pt_regs indicates kernel mode. */
714 testb $3, CS(%rsp)
715 jz 1f
716 ud2
717 1:
718 #endif
719 POP_REGS
720 addq $8, %rsp /* skip regs->orig_ax */
721 /*
722 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
723 * when returning from IPI handler.
724 */
725 INTERRUPT_RETURN
727 ENTRY(native_iret)
728 UNWIND_HINT_IRET_REGS
729 /*
730 * Are we returning to a stack segment from the LDT? Note: in
731 * 64-bit mode SS:RSP on the exception stack is always valid.
732 */
733 #ifdef CONFIG_X86_ESPFIX64
734 testb $4, (SS-RIP)(%rsp)
735 jnz native_irq_return_ldt
736 #endif
738 .global native_irq_return_iret
739 native_irq_return_iret:
740 /*
741 * This may fault. Non-paranoid faults on return to userspace are
742 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
743 * Double-faults due to espfix64 are handled in do_double_fault.
744 * Other faults here are fatal.
745 */
746 iretq
748 #ifdef CONFIG_X86_ESPFIX64
749 native_irq_return_ldt:
750 /*
751 * We are running with user GSBASE. All GPRs contain their user
752 * values. We have a percpu ESPFIX stack that is eight slots
753 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
754 * of the ESPFIX stack.
755 *
756 * We clobber RAX and RDI in this code. We stash RDI on the
757 * normal stack and RAX on the ESPFIX stack.
758 *
759 * The ESPFIX stack layout we set up looks like this:
760 *
761 * --- top of ESPFIX stack ---
762 * SS
763 * RSP
764 * RFLAGS
765 * CS
766 * RIP <-- RSP points here when we're done
767 * RAX <-- espfix_waddr points here
768 * --- bottom of ESPFIX stack ---
769 */
771 pushq %rdi /* Stash user RDI */
772 SWAPGS /* to kernel GS */
773 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
775 movq PER_CPU_VAR(espfix_waddr), %rdi
776 movq %rax, (0*8)(%rdi) /* user RAX */
777 movq (1*8)(%rsp), %rax /* user RIP */
778 movq %rax, (1*8)(%rdi)
779 movq (2*8)(%rsp), %rax /* user CS */
780 movq %rax, (2*8)(%rdi)
781 movq (3*8)(%rsp), %rax /* user RFLAGS */
782 movq %rax, (3*8)(%rdi)
783 movq (5*8)(%rsp), %rax /* user SS */
784 movq %rax, (5*8)(%rdi)
785 movq (4*8)(%rsp), %rax /* user RSP */
786 movq %rax, (4*8)(%rdi)
787 /* Now RAX == RSP. */
789 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
791 /*
792 * espfix_stack[31:16] == 0. The page tables are set up such that
793 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
794 * espfix_waddr for any X. That is, there are 65536 RO aliases of
795 * the same page. Set up RSP so that RSP[31:16] contains the
796 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
797 * still points to an RO alias of the ESPFIX stack.
798 */
799 orq PER_CPU_VAR(espfix_stack), %rax
801 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
802 SWAPGS /* to user GS */
803 popq %rdi /* Restore user RDI */
805 movq %rax, %rsp
806 UNWIND_HINT_IRET_REGS offset=8
808 /*
809 * At this point, we cannot write to the stack any more, but we can
810 * still read.
811 */
812 popq %rax /* Restore user RAX */
814 /*
815 * RSP now points to an ordinary IRET frame, except that the page
816 * is read-only and RSP[31:16] are preloaded with the userspace
817 * values. We can now IRET back to userspace.
818 */
819 jmp native_irq_return_iret
820 #endif
821 END(common_interrupt)
823 /*
824 * APIC interrupts.
825 */
826 .macro apicinterrupt3 num sym do_sym
827 ENTRY(\sym)
828 UNWIND_HINT_IRET_REGS
829 pushq $~(\num)
830 .Lcommon_\sym:
831 call interrupt_entry
832 UNWIND_HINT_REGS indirect=1
833 call \do_sym /* rdi points to pt_regs */
834 jmp ret_from_intr
835 END(\sym)
836 .endm
838 /* Make sure APIC interrupt handlers end up in the irqentry section: */
839 #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
840 #define POP_SECTION_IRQENTRY .popsection
842 .macro apicinterrupt num sym do_sym
843 PUSH_SECTION_IRQENTRY
844 apicinterrupt3 \num \sym \do_sym
845 POP_SECTION_IRQENTRY
846 .endm
848 #ifdef CONFIG_SMP
849 apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
850 apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
851 #endif
853 #ifdef CONFIG_X86_UV
854 apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
855 #endif
857 apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
858 apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
860 #ifdef CONFIG_HAVE_KVM
861 apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
862 apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
863 apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi
864 #endif
866 #ifdef CONFIG_X86_MCE_THRESHOLD
867 apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
868 #endif
870 #ifdef CONFIG_X86_MCE_AMD
871 apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
872 #endif
874 #ifdef CONFIG_X86_THERMAL_VECTOR
875 apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
876 #endif
878 #ifdef CONFIG_SMP
879 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
880 apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
881 apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
882 #endif
884 apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
885 apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
887 #ifdef CONFIG_IRQ_WORK
888 apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
889 #endif
891 /*
892 * Exception entry points.
893 */
894 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8)
896 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1
897 ENTRY(\sym)
898 UNWIND_HINT_IRET_REGS offset=\has_error_code*8
900 /* Sanity check */
901 .if \shift_ist != -1 && \paranoid == 0
902 .error "using shift_ist requires paranoid=1"
903 .endif
905 ASM_CLAC
907 .if \has_error_code == 0
908 pushq $-1 /* ORIG_RAX: no syscall to restart */
909 .endif
911 .if \paranoid < 2
912 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */
913 jnz .Lfrom_usermode_switch_stack_\@
914 .endif
916 .if \paranoid
917 call paranoid_entry
918 .else
919 call error_entry
920 .endif
921 UNWIND_HINT_REGS
922 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
924 .if \paranoid
925 .if \shift_ist != -1
926 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
927 .else
928 TRACE_IRQS_OFF
929 .endif
930 .endif
932 movq %rsp, %rdi /* pt_regs pointer */
934 .if \has_error_code
935 movq ORIG_RAX(%rsp), %rsi /* get error code */
936 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
937 .else
938 xorl %esi, %esi /* no error code */
939 .endif
941 .if \shift_ist != -1
942 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
943 .endif
945 call \do_sym
947 .if \shift_ist != -1
948 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
949 .endif
951 /* these procedures expect "no swapgs" flag in ebx */
952 .if \paranoid
953 jmp paranoid_exit
954 .else
955 jmp error_exit
956 .endif
958 .if \paranoid < 2
959 /*
960 * Entry from userspace. Switch stacks and treat it
961 * as a normal entry. This means that paranoid handlers
962 * run in real process context if user_mode(regs).
963 */
964 .Lfrom_usermode_switch_stack_\@:
965 call error_entry
967 movq %rsp, %rdi /* pt_regs pointer */
969 .if \has_error_code
970 movq ORIG_RAX(%rsp), %rsi /* get error code */
971 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
972 .else
973 xorl %esi, %esi /* no error code */
974 .endif
976 call \do_sym
978 jmp error_exit /* %ebx: no swapgs flag */
979 .endif
980 END(\sym)
981 .endm
983 idtentry divide_error do_divide_error has_error_code=0
984 idtentry overflow do_overflow has_error_code=0
985 idtentry bounds do_bounds has_error_code=0
986 idtentry invalid_op do_invalid_op has_error_code=0
987 idtentry device_not_available do_device_not_available has_error_code=0
988 idtentry double_fault do_double_fault has_error_code=1 paranoid=2
989 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
990 idtentry invalid_TSS do_invalid_TSS has_error_code=1
991 idtentry segment_not_present do_segment_not_present has_error_code=1
992 idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
993 idtentry coprocessor_error do_coprocessor_error has_error_code=0
994 idtentry alignment_check do_alignment_check has_error_code=1
995 idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
998 /*
999 * Reload gs selector with exception handling
1000 * edi: new selector
1001 */
1002 ENTRY(native_load_gs_index)
1003 FRAME_BEGIN
1004 pushfq
1005 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
1006 TRACE_IRQS_OFF
1007 SWAPGS
1008 .Lgs_change:
1009 movl %edi, %gs
1010 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
1011 SWAPGS
1012 TRACE_IRQS_FLAGS (%rsp)
1013 popfq
1014 FRAME_END
1015 ret
1016 ENDPROC(native_load_gs_index)
1017 EXPORT_SYMBOL(native_load_gs_index)
1019 _ASM_EXTABLE(.Lgs_change, bad_gs)
1020 .section .fixup, "ax"
1021 /* running with kernelgs */
1022 bad_gs:
1023 SWAPGS /* switch back to user gs */
1024 .macro ZAP_GS
1025 /* This can't be a string because the preprocessor needs to see it. */
1026 movl $__USER_DS, %eax
1027 movl %eax, %gs
1028 .endm
1029 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
1030 xorl %eax, %eax
1031 movl %eax, %gs
1032 jmp 2b
1033 .previous
1035 /* Call softirq on interrupt stack. Interrupts are off. */
1036 ENTRY(do_softirq_own_stack)
1037 pushq %rbp
1038 mov %rsp, %rbp
1039 ENTER_IRQ_STACK regs=0 old_rsp=%r11
1040 call __do_softirq
1041 LEAVE_IRQ_STACK regs=0
1042 leaveq
1043 ret
1044 ENDPROC(do_softirq_own_stack)
1046 #ifdef CONFIG_XEN
1047 idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0
1049 /*
1050 * A note on the "critical region" in our callback handler.
1051 * We want to avoid stacking callback handlers due to events occurring
1052 * during handling of the last event. To do this, we keep events disabled
1053 * until we've done all processing. HOWEVER, we must enable events before
1054 * popping the stack frame (can't be done atomically) and so it would still
1055 * be possible to get enough handler activations to overflow the stack.
1056 * Although unlikely, bugs of that kind are hard to track down, so we'd
1057 * like to avoid the possibility.
1058 * So, on entry to the handler we detect whether we interrupted an
1059 * existing activation in its critical region -- if so, we pop the current
1060 * activation and restart the handler using the previous one.
1061 */
1062 ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */
1064 /*
1065 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
1066 * see the correct pointer to the pt_regs
1067 */
1068 UNWIND_HINT_FUNC
1069 movq %rdi, %rsp /* we don't return, adjust the stack frame */
1070 UNWIND_HINT_REGS
1072 ENTER_IRQ_STACK old_rsp=%r10
1073 call xen_evtchn_do_upcall
1074 LEAVE_IRQ_STACK
1076 #ifndef CONFIG_PREEMPT
1077 call xen_maybe_preempt_hcall
1078 #endif
1079 jmp error_exit
1080 END(xen_do_hypervisor_callback)
1082 /*
1083 * Hypervisor uses this for application faults while it executes.
1084 * We get here for two reasons:
1085 * 1. Fault while reloading DS, ES, FS or GS
1086 * 2. Fault while executing IRET
1087 * Category 1 we do not need to fix up as Xen has already reloaded all segment
1088 * registers that could be reloaded and zeroed the others.
1089 * Category 2 we fix up by killing the current process. We cannot use the
1090 * normal Linux return path in this case because if we use the IRET hypercall
1091 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1092 * We distinguish between categories by comparing each saved segment register
1093 * with its current contents: any discrepancy means we in category 1.
1094 */
1095 ENTRY(xen_failsafe_callback)
1096 UNWIND_HINT_EMPTY
1097 movl %ds, %ecx
1098 cmpw %cx, 0x10(%rsp)
1099 jne 1f
1100 movl %es, %ecx
1101 cmpw %cx, 0x18(%rsp)
1102 jne 1f
1103 movl %fs, %ecx
1104 cmpw %cx, 0x20(%rsp)
1105 jne 1f
1106 movl %gs, %ecx
1107 cmpw %cx, 0x28(%rsp)
1108 jne 1f
1109 /* All segments match their saved values => Category 2 (Bad IRET). */
1110 movq (%rsp), %rcx
1111 movq 8(%rsp), %r11
1112 addq $0x30, %rsp
1113 pushq $0 /* RIP */
1114 UNWIND_HINT_IRET_REGS offset=8
1115 jmp general_protection
1116 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
1117 movq (%rsp), %rcx
1118 movq 8(%rsp), %r11
1119 addq $0x30, %rsp
1120 UNWIND_HINT_IRET_REGS
1121 pushq $-1 /* orig_ax = -1 => not a system call */
1122 PUSH_AND_CLEAR_REGS
1123 ENCODE_FRAME_POINTER
1124 jmp error_exit
1125 END(xen_failsafe_callback)
1127 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1128 xen_hvm_callback_vector xen_evtchn_do_upcall
1130 #endif /* CONFIG_XEN */
1132 #if IS_ENABLED(CONFIG_HYPERV)
1133 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1134 hyperv_callback_vector hyperv_vector_handler
1136 apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \
1137 hyperv_reenlightenment_vector hyperv_reenlightenment_intr
1138 #endif /* CONFIG_HYPERV */
1140 idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
1141 idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
1142 idtentry stack_segment do_stack_segment has_error_code=1
1144 #ifdef CONFIG_XEN
1145 idtentry xennmi do_nmi has_error_code=0
1146 idtentry xendebug do_debug has_error_code=0
1147 idtentry xenint3 do_int3 has_error_code=0
1148 #endif
1150 idtentry general_protection do_general_protection has_error_code=1
1151 idtentry page_fault do_page_fault has_error_code=1
1153 #ifdef CONFIG_KVM_GUEST
1154 idtentry async_page_fault do_async_page_fault has_error_code=1
1155 #endif
1157 #ifdef CONFIG_X86_MCE
1158 idtentry machine_check do_mce has_error_code=0 paranoid=1
1159 #endif
1161 /*
1162 * Save all registers in pt_regs, and switch gs if needed.
1163 * Use slow, but surefire "are we in kernel?" check.
1164 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise
1165 */
1166 ENTRY(paranoid_entry)
1167 UNWIND_HINT_FUNC
1168 cld
1169 PUSH_AND_CLEAR_REGS save_ret=1
1170 ENCODE_FRAME_POINTER 8
1171 movl $1, %ebx
1172 movl $MSR_GS_BASE, %ecx
1173 rdmsr
1174 testl %edx, %edx
1175 js 1f /* negative -> in kernel */
1176 SWAPGS
1177 xorl %ebx, %ebx
1179 1:
1180 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
1182 ret
1183 END(paranoid_entry)
1185 /*
1186 * "Paranoid" exit path from exception stack. This is invoked
1187 * only on return from non-NMI IST interrupts that came
1188 * from kernel space.
1189 *
1190 * We may be returning to very strange contexts (e.g. very early
1191 * in syscall entry), so checking for preemption here would
1192 * be complicated. Fortunately, we there's no good reason
1193 * to try to handle preemption here.
1194 *
1195 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it)
1196 */
1197 ENTRY(paranoid_exit)
1198 UNWIND_HINT_REGS
1199 DISABLE_INTERRUPTS(CLBR_ANY)
1200 TRACE_IRQS_OFF_DEBUG
1201 testl %ebx, %ebx /* swapgs needed? */
1202 jnz .Lparanoid_exit_no_swapgs
1203 TRACE_IRQS_IRETQ
1204 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1205 SWAPGS_UNSAFE_STACK
1206 jmp .Lparanoid_exit_restore
1207 .Lparanoid_exit_no_swapgs:
1208 TRACE_IRQS_IRETQ_DEBUG
1209 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1210 .Lparanoid_exit_restore:
1211 jmp restore_regs_and_return_to_kernel
1212 END(paranoid_exit)
1214 /*
1215 * Save all registers in pt_regs, and switch GS if needed.
1216 * Return: EBX=0: came from user mode; EBX=1: otherwise
1217 */
1218 ENTRY(error_entry)
1219 UNWIND_HINT_FUNC
1220 cld
1221 PUSH_AND_CLEAR_REGS save_ret=1
1222 ENCODE_FRAME_POINTER 8
1223 testb $3, CS+8(%rsp)
1224 jz .Lerror_kernelspace
1226 /*
1227 * We entered from user mode or we're pretending to have entered
1228 * from user mode due to an IRET fault.
1229 */
1230 SWAPGS
1231 /* We have user CR3. Change to kernel CR3. */
1232 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1234 .Lerror_entry_from_usermode_after_swapgs:
1235 /* Put us onto the real thread stack. */
1236 popq %r12 /* save return addr in %12 */
1237 movq %rsp, %rdi /* arg0 = pt_regs pointer */
1238 call sync_regs
1239 movq %rax, %rsp /* switch stack */
1240 ENCODE_FRAME_POINTER
1241 pushq %r12
1243 /*
1244 * We need to tell lockdep that IRQs are off. We can't do this until
1245 * we fix gsbase, and we should do it before enter_from_user_mode
1246 * (which can take locks).
1247 */
1248 TRACE_IRQS_OFF
1249 CALL_enter_from_user_mode
1250 ret
1252 .Lerror_entry_done:
1253 TRACE_IRQS_OFF
1254 ret
1256 /*
1257 * There are two places in the kernel that can potentially fault with
1258 * usergs. Handle them here. B stepping K8s sometimes report a
1259 * truncated RIP for IRET exceptions returning to compat mode. Check
1260 * for these here too.
1261 */
1262 .Lerror_kernelspace:
1263 incl %ebx
1264 leaq native_irq_return_iret(%rip), %rcx
1265 cmpq %rcx, RIP+8(%rsp)
1266 je .Lerror_bad_iret
1267 movl %ecx, %eax /* zero extend */
1268 cmpq %rax, RIP+8(%rsp)
1269 je .Lbstep_iret
1270 cmpq $.Lgs_change, RIP+8(%rsp)
1271 jne .Lerror_entry_done
1273 /*
1274 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1275 * gsbase and proceed. We'll fix up the exception and land in
1276 * .Lgs_change's error handler with kernel gsbase.
1277 */
1278 SWAPGS
1279 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1280 jmp .Lerror_entry_done
1282 .Lbstep_iret:
1283 /* Fix truncated RIP */
1284 movq %rcx, RIP+8(%rsp)
1285 /* fall through */
1287 .Lerror_bad_iret:
1288 /*
1289 * We came from an IRET to user mode, so we have user
1290 * gsbase and CR3. Switch to kernel gsbase and CR3:
1291 */
1292 SWAPGS
1293 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1295 /*
1296 * Pretend that the exception came from user mode: set up pt_regs
1297 * as if we faulted immediately after IRET and clear EBX so that
1298 * error_exit knows that we will be returning to user mode.
1299 */
1300 mov %rsp, %rdi
1301 call fixup_bad_iret
1302 mov %rax, %rsp
1303 decl %ebx
1304 jmp .Lerror_entry_from_usermode_after_swapgs
1305 END(error_entry)
1308 /*
1309 * On entry, EBX is a "return to kernel mode" flag:
1310 * 1: already in kernel mode, don't need SWAPGS
1311 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode
1312 */
1313 ENTRY(error_exit)
1314 UNWIND_HINT_REGS
1315 DISABLE_INTERRUPTS(CLBR_ANY)
1316 TRACE_IRQS_OFF
1317 testl %ebx, %ebx
1318 jnz retint_kernel
1319 jmp retint_user
1320 END(error_exit)
1322 /*
1323 * Runs on exception stack. Xen PV does not go through this path at all,
1324 * so we can use real assembly here.
1325 *
1326 * Registers:
1327 * %r14: Used to save/restore the CR3 of the interrupted context
1328 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1329 */
1330 ENTRY(nmi)
1331 UNWIND_HINT_IRET_REGS
1333 /*
1334 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1335 * the iretq it performs will take us out of NMI context.
1336 * This means that we can have nested NMIs where the next
1337 * NMI is using the top of the stack of the previous NMI. We
1338 * can't let it execute because the nested NMI will corrupt the
1339 * stack of the previous NMI. NMI handlers are not re-entrant
1340 * anyway.
1341 *
1342 * To handle this case we do the following:
1343 * Check the a special location on the stack that contains
1344 * a variable that is set when NMIs are executing.
1345 * The interrupted task's stack is also checked to see if it
1346 * is an NMI stack.
1347 * If the variable is not set and the stack is not the NMI
1348 * stack then:
1349 * o Set the special variable on the stack
1350 * o Copy the interrupt frame into an "outermost" location on the
1351 * stack
1352 * o Copy the interrupt frame into an "iret" location on the stack
1353 * o Continue processing the NMI
1354 * If the variable is set or the previous stack is the NMI stack:
1355 * o Modify the "iret" location to jump to the repeat_nmi
1356 * o return back to the first NMI
1357 *
1358 * Now on exit of the first NMI, we first clear the stack variable
1359 * The NMI stack will tell any nested NMIs at that point that it is
1360 * nested. Then we pop the stack normally with iret, and if there was
1361 * a nested NMI that updated the copy interrupt stack frame, a
1362 * jump will be made to the repeat_nmi code that will handle the second
1363 * NMI.
1364 *
1365 * However, espfix prevents us from directly returning to userspace
1366 * with a single IRET instruction. Similarly, IRET to user mode
1367 * can fault. We therefore handle NMIs from user space like
1368 * other IST entries.
1369 */
1371 ASM_CLAC
1373 /* Use %rdx as our temp variable throughout */
1374 pushq %rdx
1376 testb $3, CS-RIP+8(%rsp)
1377 jz .Lnmi_from_kernel
1379 /*
1380 * NMI from user mode. We need to run on the thread stack, but we
1381 * can't go through the normal entry paths: NMIs are masked, and
1382 * we don't want to enable interrupts, because then we'll end
1383 * up in an awkward situation in which IRQs are on but NMIs
1384 * are off.
1385 *
1386 * We also must not push anything to the stack before switching
1387 * stacks lest we corrupt the "NMI executing" variable.
1388 */
1390 swapgs
1391 cld
1392 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1393 movq %rsp, %rdx
1394 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
1395 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1396 pushq 5*8(%rdx) /* pt_regs->ss */
1397 pushq 4*8(%rdx) /* pt_regs->rsp */
1398 pushq 3*8(%rdx) /* pt_regs->flags */
1399 pushq 2*8(%rdx) /* pt_regs->cs */
1400 pushq 1*8(%rdx) /* pt_regs->rip */
1401 UNWIND_HINT_IRET_REGS
1402 pushq $-1 /* pt_regs->orig_ax */
1403 PUSH_AND_CLEAR_REGS rdx=(%rdx)
1404 ENCODE_FRAME_POINTER
1406 /*
1407 * At this point we no longer need to worry about stack damage
1408 * due to nesting -- we're on the normal thread stack and we're
1409 * done with the NMI stack.
1410 */
1412 movq %rsp, %rdi
1413 movq $-1, %rsi
1414 call do_nmi
1416 /*
1417 * Return back to user mode. We must *not* do the normal exit
1418 * work, because we don't want to enable interrupts.
1419 */
1420 jmp swapgs_restore_regs_and_return_to_usermode
1422 .Lnmi_from_kernel:
1423 /*
1424 * Here's what our stack frame will look like:
1425 * +---------------------------------------------------------+
1426 * | original SS |
1427 * | original Return RSP |
1428 * | original RFLAGS |
1429 * | original CS |
1430 * | original RIP |
1431 * +---------------------------------------------------------+
1432 * | temp storage for rdx |
1433 * +---------------------------------------------------------+
1434 * | "NMI executing" variable |
1435 * +---------------------------------------------------------+
1436 * | iret SS } Copied from "outermost" frame |
1437 * | iret Return RSP } on each loop iteration; overwritten |
1438 * | iret RFLAGS } by a nested NMI to force another |
1439 * | iret CS } iteration if needed. |
1440 * | iret RIP } |
1441 * +---------------------------------------------------------+
1442 * | outermost SS } initialized in first_nmi; |
1443 * | outermost Return RSP } will not be changed before |
1444 * | outermost RFLAGS } NMI processing is done. |
1445 * | outermost CS } Copied to "iret" frame on each |
1446 * | outermost RIP } iteration. |
1447 * +---------------------------------------------------------+
1448 * | pt_regs |
1449 * +---------------------------------------------------------+
1450 *
1451 * The "original" frame is used by hardware. Before re-enabling
1452 * NMIs, we need to be done with it, and we need to leave enough
1453 * space for the asm code here.
1454 *
1455 * We return by executing IRET while RSP points to the "iret" frame.
1456 * That will either return for real or it will loop back into NMI
1457 * processing.
1458 *
1459 * The "outermost" frame is copied to the "iret" frame on each
1460 * iteration of the loop, so each iteration starts with the "iret"
1461 * frame pointing to the final return target.
1462 */
1464 /*
1465 * Determine whether we're a nested NMI.
1466 *
1467 * If we interrupted kernel code between repeat_nmi and
1468 * end_repeat_nmi, then we are a nested NMI. We must not
1469 * modify the "iret" frame because it's being written by
1470 * the outer NMI. That's okay; the outer NMI handler is
1471 * about to about to call do_nmi anyway, so we can just
1472 * resume the outer NMI.
1473 */
1475 movq $repeat_nmi, %rdx
1476 cmpq 8(%rsp), %rdx
1477 ja 1f
1478 movq $end_repeat_nmi, %rdx
1479 cmpq 8(%rsp), %rdx
1480 ja nested_nmi_out
1481 1:
1483 /*
1484 * Now check "NMI executing". If it's set, then we're nested.
1485 * This will not detect if we interrupted an outer NMI just
1486 * before IRET.
1487 */
1488 cmpl $1, -8(%rsp)
1489 je nested_nmi
1491 /*
1492 * Now test if the previous stack was an NMI stack. This covers
1493 * the case where we interrupt an outer NMI after it clears
1494 * "NMI executing" but before IRET. We need to be careful, though:
1495 * there is one case in which RSP could point to the NMI stack
1496 * despite there being no NMI active: naughty userspace controls
1497 * RSP at the very beginning of the SYSCALL targets. We can
1498 * pull a fast one on naughty userspace, though: we program
1499 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1500 * if it controls the kernel's RSP. We set DF before we clear
1501 * "NMI executing".
1502 */
1503 lea 6*8(%rsp), %rdx
1504 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1505 cmpq %rdx, 4*8(%rsp)
1506 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1507 ja first_nmi
1509 subq $EXCEPTION_STKSZ, %rdx
1510 cmpq %rdx, 4*8(%rsp)
1511 /* If it is below the NMI stack, it is a normal NMI */
1512 jb first_nmi
1514 /* Ah, it is within the NMI stack. */
1516 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1517 jz first_nmi /* RSP was user controlled. */
1519 /* This is a nested NMI. */
1521 nested_nmi:
1522 /*
1523 * Modify the "iret" frame to point to repeat_nmi, forcing another
1524 * iteration of NMI handling.
1525 */
1526 subq $8, %rsp
1527 leaq -10*8(%rsp), %rdx
1528 pushq $__KERNEL_DS
1529 pushq %rdx
1530 pushfq
1531 pushq $__KERNEL_CS
1532 pushq $repeat_nmi
1534 /* Put stack back */
1535 addq $(6*8), %rsp
1537 nested_nmi_out:
1538 popq %rdx
1540 /* We are returning to kernel mode, so this cannot result in a fault. */
1541 iretq
1543 first_nmi:
1544 /* Restore rdx. */
1545 movq (%rsp), %rdx
1547 /* Make room for "NMI executing". */
1548 pushq $0
1550 /* Leave room for the "iret" frame */
1551 subq $(5*8), %rsp
1553 /* Copy the "original" frame to the "outermost" frame */
1554 .rept 5
1555 pushq 11*8(%rsp)
1556 .endr
1557 UNWIND_HINT_IRET_REGS
1559 /* Everything up to here is safe from nested NMIs */
1561 #ifdef CONFIG_DEBUG_ENTRY
1562 /*
1563 * For ease of testing, unmask NMIs right away. Disabled by
1564 * default because IRET is very expensive.
1565 */
1566 pushq $0 /* SS */
1567 pushq %rsp /* RSP (minus 8 because of the previous push) */
1568 addq $8, (%rsp) /* Fix up RSP */
1569 pushfq /* RFLAGS */
1570 pushq $__KERNEL_CS /* CS */
1571 pushq $1f /* RIP */
1572 iretq /* continues at repeat_nmi below */
1573 UNWIND_HINT_IRET_REGS
1574 1:
1575 #endif
1577 repeat_nmi:
1578 /*
1579 * If there was a nested NMI, the first NMI's iret will return
1580 * here. But NMIs are still enabled and we can take another
1581 * nested NMI. The nested NMI checks the interrupted RIP to see
1582 * if it is between repeat_nmi and end_repeat_nmi, and if so
1583 * it will just return, as we are about to repeat an NMI anyway.
1584 * This makes it safe to copy to the stack frame that a nested
1585 * NMI will update.
1586 *
1587 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1588 * we're repeating an NMI, gsbase has the same value that it had on
1589 * the first iteration. paranoid_entry will load the kernel
1590 * gsbase if needed before we call do_nmi. "NMI executing"
1591 * is zero.
1592 */
1593 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1595 /*
1596 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1597 * here must not modify the "iret" frame while we're writing to
1598 * it or it will end up containing garbage.
1599 */
1600 addq $(10*8), %rsp
1601 .rept 5
1602 pushq -6*8(%rsp)
1603 .endr
1604 subq $(5*8), %rsp
1605 end_repeat_nmi:
1607 /*
1608 * Everything below this point can be preempted by a nested NMI.
1609 * If this happens, then the inner NMI will change the "iret"
1610 * frame to point back to repeat_nmi.
1611 */
1612 pushq $-1 /* ORIG_RAX: no syscall to restart */
1614 /*
1615 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1616 * as we should not be calling schedule in NMI context.
1617 * Even with normal interrupts enabled. An NMI should not be
1618 * setting NEED_RESCHED or anything that normal interrupts and
1619 * exceptions might do.
1620 */
1621 call paranoid_entry
1622 UNWIND_HINT_REGS
1624 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
1625 movq %rsp, %rdi
1626 movq $-1, %rsi
1627 call do_nmi
1629 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1631 testl %ebx, %ebx /* swapgs needed? */
1632 jnz nmi_restore
1633 nmi_swapgs:
1634 SWAPGS_UNSAFE_STACK
1635 nmi_restore:
1636 POP_REGS
1638 /*
1639 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1640 * at the "iret" frame.
1641 */
1642 addq $6*8, %rsp
1644 /*
1645 * Clear "NMI executing". Set DF first so that we can easily
1646 * distinguish the remaining code between here and IRET from
1647 * the SYSCALL entry and exit paths.
1648 *
1649 * We arguably should just inspect RIP instead, but I (Andy) wrote
1650 * this code when I had the misapprehension that Xen PV supported
1651 * NMIs, and Xen PV would break that approach.
1652 */
1653 std
1654 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1656 /*
1657 * iretq reads the "iret" frame and exits the NMI stack in a
1658 * single instruction. We are returning to kernel mode, so this
1659 * cannot result in a fault. Similarly, we don't need to worry
1660 * about espfix64 on the way back to kernel mode.
1661 */
1662 iretq
1663 END(nmi)
1665 ENTRY(ignore_sysret)
1666 UNWIND_HINT_EMPTY
1667 mov $-ENOSYS, %eax
1668 sysret
1669 END(ignore_sysret)
1671 ENTRY(rewind_stack_do_exit)
1672 UNWIND_HINT_FUNC
1673 /* Prevent any naive code from trying to unwind to our caller. */
1674 xorl %ebp, %ebp
1676 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
1677 leaq -PTREGS_SIZE(%rax), %rsp
1678 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE
1680 call do_exit
1681 END(rewind_stack_do_exit)