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[cris-mirror.git] / arch / x86 / include / asm / io_apic.h
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1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_IO_APIC_H
3 #define _ASM_X86_IO_APIC_H
5 #include <linux/types.h>
6 #include <asm/mpspec.h>
7 #include <asm/apicdef.h>
8 #include <asm/irq_vectors.h>
9 #include <asm/x86_init.h>
11 * Intel IO-APIC support for SMP and UP systems.
13 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
16 /* I/O Unit Redirection Table */
17 #define IO_APIC_REDIR_VECTOR_MASK 0x000FF
18 #define IO_APIC_REDIR_DEST_LOGICAL 0x00800
19 #define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
20 #define IO_APIC_REDIR_SEND_PENDING (1 << 12)
21 #define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
22 #define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
23 #define IO_APIC_REDIR_MASKED (1 << 16)
26 * The structure of the IO-APIC:
28 union IO_APIC_reg_00 {
29 u32 raw;
30 struct {
31 u32 __reserved_2 : 14,
32 LTS : 1,
33 delivery_type : 1,
34 __reserved_1 : 8,
35 ID : 8;
36 } __attribute__ ((packed)) bits;
39 union IO_APIC_reg_01 {
40 u32 raw;
41 struct {
42 u32 version : 8,
43 __reserved_2 : 7,
44 PRQ : 1,
45 entries : 8,
46 __reserved_1 : 8;
47 } __attribute__ ((packed)) bits;
50 union IO_APIC_reg_02 {
51 u32 raw;
52 struct {
53 u32 __reserved_2 : 24,
54 arbitration : 4,
55 __reserved_1 : 4;
56 } __attribute__ ((packed)) bits;
59 union IO_APIC_reg_03 {
60 u32 raw;
61 struct {
62 u32 boot_DT : 1,
63 __reserved_1 : 31;
64 } __attribute__ ((packed)) bits;
67 struct IO_APIC_route_entry {
68 __u32 vector : 8,
69 delivery_mode : 3, /* 000: FIXED
70 * 001: lowest prio
71 * 111: ExtINT
73 dest_mode : 1, /* 0: physical, 1: logical */
74 delivery_status : 1,
75 polarity : 1,
76 irr : 1,
77 trigger : 1, /* 0: edge, 1: level */
78 mask : 1, /* 0: enabled, 1: disabled */
79 __reserved_2 : 15;
81 __u32 __reserved_3 : 24,
82 dest : 8;
83 } __attribute__ ((packed));
85 struct IR_IO_APIC_route_entry {
86 __u64 vector : 8,
87 zero : 3,
88 index2 : 1,
89 delivery_status : 1,
90 polarity : 1,
91 irr : 1,
92 trigger : 1,
93 mask : 1,
94 reserved : 31,
95 format : 1,
96 index : 15;
97 } __attribute__ ((packed));
99 struct irq_alloc_info;
100 struct ioapic_domain_cfg;
102 #define IOAPIC_AUTO -1
103 #define IOAPIC_EDGE 0
104 #define IOAPIC_LEVEL 1
106 #define IOAPIC_MASKED 1
107 #define IOAPIC_UNMASKED 0
109 #define IOAPIC_POL_HIGH 0
110 #define IOAPIC_POL_LOW 1
112 #define IOAPIC_DEST_MODE_PHYSICAL 0
113 #define IOAPIC_DEST_MODE_LOGICAL 1
115 #define IOAPIC_MAP_ALLOC 0x1
116 #define IOAPIC_MAP_CHECK 0x2
118 #ifdef CONFIG_X86_IO_APIC
121 * # of IO-APICs and # of IRQ routing registers
123 extern int nr_ioapics;
125 extern int mpc_ioapic_id(int ioapic);
126 extern unsigned int mpc_ioapic_addr(int ioapic);
128 /* # of MP IRQ source entries */
129 extern int mp_irq_entries;
131 /* MP IRQ source entries */
132 extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
134 /* 1 if "noapic" boot option passed */
135 extern int skip_ioapic_setup;
137 /* 1 if "noapic" boot option passed */
138 extern int noioapicquirk;
140 /* -1 if "noapic" boot option passed */
141 extern int noioapicreroute;
143 extern u32 gsi_top;
145 extern unsigned long io_apic_irqs;
147 #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))
150 * If we use the IO-APIC for IRQ routing, disable automatic
151 * assignment of PCI IRQ's.
153 #define io_apic_assign_pci_irqs \
154 (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
156 struct irq_cfg;
157 extern void ioapic_insert_resources(void);
158 extern int arch_early_ioapic_init(void);
160 extern int save_ioapic_entries(void);
161 extern void mask_ioapic_entries(void);
162 extern int restore_ioapic_entries(void);
164 extern void setup_ioapic_ids_from_mpc(void);
165 extern void setup_ioapic_ids_from_mpc_nocheck(void);
167 extern int mp_find_ioapic(u32 gsi);
168 extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
169 extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
170 struct irq_alloc_info *info);
171 extern void mp_unmap_irq(int irq);
172 extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
173 struct ioapic_domain_cfg *cfg);
174 extern int mp_unregister_ioapic(u32 gsi_base);
175 extern int mp_ioapic_registered(u32 gsi_base);
177 extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
178 int node, int trigger, int polarity);
180 extern void mp_save_irq(struct mpc_intsrc *m);
182 extern void disable_ioapic_support(void);
184 extern void __init io_apic_init_mappings(void);
185 extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
186 extern void native_disable_io_apic(void);
188 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
190 return x86_io_apic_ops.read(apic, reg);
193 extern void setup_IO_APIC(void);
194 extern void enable_IO_APIC(void);
195 extern void disable_IO_APIC(void);
196 extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
197 extern void print_IO_APICs(void);
198 #else /* !CONFIG_X86_IO_APIC */
200 #define IO_APIC_IRQ(x) 0
201 #define io_apic_assign_pci_irqs 0
202 #define setup_ioapic_ids_from_mpc x86_init_noop
203 static inline void ioapic_insert_resources(void) { }
204 static inline int arch_early_ioapic_init(void) { return 0; }
205 static inline void print_IO_APICs(void) {}
206 #define gsi_top (NR_IRQS_LEGACY)
207 static inline int mp_find_ioapic(u32 gsi) { return 0; }
208 static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
209 struct irq_alloc_info *info)
211 return gsi;
214 static inline void mp_unmap_irq(int irq) { }
216 static inline int save_ioapic_entries(void)
218 return -ENOMEM;
221 static inline void mask_ioapic_entries(void) { }
222 static inline int restore_ioapic_entries(void)
224 return -ENOMEM;
227 static inline void mp_save_irq(struct mpc_intsrc *m) { }
228 static inline void disable_ioapic_support(void) { }
229 static inline void io_apic_init_mappings(void) { }
230 #define native_io_apic_read NULL
231 #define native_disable_io_apic NULL
233 static inline void setup_IO_APIC(void) { }
234 static inline void enable_IO_APIC(void) { }
236 #endif
238 #endif /* _ASM_X86_IO_APIC_H */