1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PARAVIRT_H
3 #define _ASM_X86_PARAVIRT_H
4 /* Various instructions on x86 need to be replaced for
5 * para-virtualization: those hooks are defined here. */
8 #include <asm/pgtable_types.h>
10 #include <asm/nospec-branch.h>
12 #include <asm/paravirt_types.h>
15 #include <linux/bug.h>
16 #include <linux/types.h>
17 #include <linux/cpumask.h>
18 #include <asm/frame.h>
20 static inline void load_sp0(unsigned long sp0
)
22 PVOP_VCALL1(pv_cpu_ops
.load_sp0
, sp0
);
25 /* The paravirtualized CPUID instruction. */
26 static inline void __cpuid(unsigned int *eax
, unsigned int *ebx
,
27 unsigned int *ecx
, unsigned int *edx
)
29 PVOP_VCALL4(pv_cpu_ops
.cpuid
, eax
, ebx
, ecx
, edx
);
33 * These special macros can be used to get or set a debugging register
35 static inline unsigned long paravirt_get_debugreg(int reg
)
37 return PVOP_CALL1(unsigned long, pv_cpu_ops
.get_debugreg
, reg
);
39 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
40 static inline void set_debugreg(unsigned long val
, int reg
)
42 PVOP_VCALL2(pv_cpu_ops
.set_debugreg
, reg
, val
);
45 static inline unsigned long read_cr0(void)
47 return PVOP_CALL0(unsigned long, pv_cpu_ops
.read_cr0
);
50 static inline void write_cr0(unsigned long x
)
52 PVOP_VCALL1(pv_cpu_ops
.write_cr0
, x
);
55 static inline unsigned long read_cr2(void)
57 return PVOP_CALL0(unsigned long, pv_mmu_ops
.read_cr2
);
60 static inline void write_cr2(unsigned long x
)
62 PVOP_VCALL1(pv_mmu_ops
.write_cr2
, x
);
65 static inline unsigned long __read_cr3(void)
67 return PVOP_CALL0(unsigned long, pv_mmu_ops
.read_cr3
);
70 static inline void write_cr3(unsigned long x
)
72 PVOP_VCALL1(pv_mmu_ops
.write_cr3
, x
);
75 static inline void __write_cr4(unsigned long x
)
77 PVOP_VCALL1(pv_cpu_ops
.write_cr4
, x
);
81 static inline unsigned long read_cr8(void)
83 return PVOP_CALL0(unsigned long, pv_cpu_ops
.read_cr8
);
86 static inline void write_cr8(unsigned long x
)
88 PVOP_VCALL1(pv_cpu_ops
.write_cr8
, x
);
92 static inline void arch_safe_halt(void)
94 PVOP_VCALL0(pv_irq_ops
.safe_halt
);
97 static inline void halt(void)
99 PVOP_VCALL0(pv_irq_ops
.halt
);
102 static inline void wbinvd(void)
104 PVOP_VCALL0(pv_cpu_ops
.wbinvd
);
107 #define get_kernel_rpl() (pv_info.kernel_rpl)
109 static inline u64
paravirt_read_msr(unsigned msr
)
111 return PVOP_CALL1(u64
, pv_cpu_ops
.read_msr
, msr
);
114 static inline void paravirt_write_msr(unsigned msr
,
115 unsigned low
, unsigned high
)
117 PVOP_VCALL3(pv_cpu_ops
.write_msr
, msr
, low
, high
);
120 static inline u64
paravirt_read_msr_safe(unsigned msr
, int *err
)
122 return PVOP_CALL2(u64
, pv_cpu_ops
.read_msr_safe
, msr
, err
);
125 static inline int paravirt_write_msr_safe(unsigned msr
,
126 unsigned low
, unsigned high
)
128 return PVOP_CALL3(int, pv_cpu_ops
.write_msr_safe
, msr
, low
, high
);
131 #define rdmsr(msr, val1, val2) \
133 u64 _l = paravirt_read_msr(msr); \
138 #define wrmsr(msr, val1, val2) \
140 paravirt_write_msr(msr, val1, val2); \
143 #define rdmsrl(msr, val) \
145 val = paravirt_read_msr(msr); \
148 static inline void wrmsrl(unsigned msr
, u64 val
)
150 wrmsr(msr
, (u32
)val
, (u32
)(val
>>32));
153 #define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b)
155 /* rdmsr with exception handling */
156 #define rdmsr_safe(msr, a, b) \
159 u64 _l = paravirt_read_msr_safe(msr, &_err); \
165 static inline int rdmsrl_safe(unsigned msr
, unsigned long long *p
)
169 *p
= paravirt_read_msr_safe(msr
, &err
);
173 static inline unsigned long long paravirt_sched_clock(void)
175 return PVOP_CALL0(unsigned long long, pv_time_ops
.sched_clock
);
179 extern struct static_key paravirt_steal_enabled
;
180 extern struct static_key paravirt_steal_rq_enabled
;
182 static inline u64
paravirt_steal_clock(int cpu
)
184 return PVOP_CALL1(u64
, pv_time_ops
.steal_clock
, cpu
);
187 static inline unsigned long long paravirt_read_pmc(int counter
)
189 return PVOP_CALL1(u64
, pv_cpu_ops
.read_pmc
, counter
);
192 #define rdpmc(counter, low, high) \
194 u64 _l = paravirt_read_pmc(counter); \
199 #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
201 static inline void paravirt_alloc_ldt(struct desc_struct
*ldt
, unsigned entries
)
203 PVOP_VCALL2(pv_cpu_ops
.alloc_ldt
, ldt
, entries
);
206 static inline void paravirt_free_ldt(struct desc_struct
*ldt
, unsigned entries
)
208 PVOP_VCALL2(pv_cpu_ops
.free_ldt
, ldt
, entries
);
211 static inline void load_TR_desc(void)
213 PVOP_VCALL0(pv_cpu_ops
.load_tr_desc
);
215 static inline void load_gdt(const struct desc_ptr
*dtr
)
217 PVOP_VCALL1(pv_cpu_ops
.load_gdt
, dtr
);
219 static inline void load_idt(const struct desc_ptr
*dtr
)
221 PVOP_VCALL1(pv_cpu_ops
.load_idt
, dtr
);
223 static inline void set_ldt(const void *addr
, unsigned entries
)
225 PVOP_VCALL2(pv_cpu_ops
.set_ldt
, addr
, entries
);
227 static inline unsigned long paravirt_store_tr(void)
229 return PVOP_CALL0(unsigned long, pv_cpu_ops
.store_tr
);
231 #define store_tr(tr) ((tr) = paravirt_store_tr())
232 static inline void load_TLS(struct thread_struct
*t
, unsigned cpu
)
234 PVOP_VCALL2(pv_cpu_ops
.load_tls
, t
, cpu
);
238 static inline void load_gs_index(unsigned int gs
)
240 PVOP_VCALL1(pv_cpu_ops
.load_gs_index
, gs
);
244 static inline void write_ldt_entry(struct desc_struct
*dt
, int entry
,
247 PVOP_VCALL3(pv_cpu_ops
.write_ldt_entry
, dt
, entry
, desc
);
250 static inline void write_gdt_entry(struct desc_struct
*dt
, int entry
,
251 void *desc
, int type
)
253 PVOP_VCALL4(pv_cpu_ops
.write_gdt_entry
, dt
, entry
, desc
, type
);
256 static inline void write_idt_entry(gate_desc
*dt
, int entry
, const gate_desc
*g
)
258 PVOP_VCALL3(pv_cpu_ops
.write_idt_entry
, dt
, entry
, g
);
260 static inline void set_iopl_mask(unsigned mask
)
262 PVOP_VCALL1(pv_cpu_ops
.set_iopl_mask
, mask
);
265 /* The paravirtualized I/O functions */
266 static inline void slow_down_io(void)
268 pv_cpu_ops
.io_delay();
269 #ifdef REALLY_SLOW_IO
270 pv_cpu_ops
.io_delay();
271 pv_cpu_ops
.io_delay();
272 pv_cpu_ops
.io_delay();
276 static inline void paravirt_activate_mm(struct mm_struct
*prev
,
277 struct mm_struct
*next
)
279 PVOP_VCALL2(pv_mmu_ops
.activate_mm
, prev
, next
);
282 static inline void paravirt_arch_dup_mmap(struct mm_struct
*oldmm
,
283 struct mm_struct
*mm
)
285 PVOP_VCALL2(pv_mmu_ops
.dup_mmap
, oldmm
, mm
);
288 static inline void paravirt_arch_exit_mmap(struct mm_struct
*mm
)
290 PVOP_VCALL1(pv_mmu_ops
.exit_mmap
, mm
);
293 static inline void __flush_tlb(void)
295 PVOP_VCALL0(pv_mmu_ops
.flush_tlb_user
);
297 static inline void __flush_tlb_global(void)
299 PVOP_VCALL0(pv_mmu_ops
.flush_tlb_kernel
);
301 static inline void __flush_tlb_one_user(unsigned long addr
)
303 PVOP_VCALL1(pv_mmu_ops
.flush_tlb_one_user
, addr
);
306 static inline void flush_tlb_others(const struct cpumask
*cpumask
,
307 const struct flush_tlb_info
*info
)
309 PVOP_VCALL2(pv_mmu_ops
.flush_tlb_others
, cpumask
, info
);
312 static inline int paravirt_pgd_alloc(struct mm_struct
*mm
)
314 return PVOP_CALL1(int, pv_mmu_ops
.pgd_alloc
, mm
);
317 static inline void paravirt_pgd_free(struct mm_struct
*mm
, pgd_t
*pgd
)
319 PVOP_VCALL2(pv_mmu_ops
.pgd_free
, mm
, pgd
);
322 static inline void paravirt_alloc_pte(struct mm_struct
*mm
, unsigned long pfn
)
324 PVOP_VCALL2(pv_mmu_ops
.alloc_pte
, mm
, pfn
);
326 static inline void paravirt_release_pte(unsigned long pfn
)
328 PVOP_VCALL1(pv_mmu_ops
.release_pte
, pfn
);
331 static inline void paravirt_alloc_pmd(struct mm_struct
*mm
, unsigned long pfn
)
333 PVOP_VCALL2(pv_mmu_ops
.alloc_pmd
, mm
, pfn
);
336 static inline void paravirt_release_pmd(unsigned long pfn
)
338 PVOP_VCALL1(pv_mmu_ops
.release_pmd
, pfn
);
341 static inline void paravirt_alloc_pud(struct mm_struct
*mm
, unsigned long pfn
)
343 PVOP_VCALL2(pv_mmu_ops
.alloc_pud
, mm
, pfn
);
345 static inline void paravirt_release_pud(unsigned long pfn
)
347 PVOP_VCALL1(pv_mmu_ops
.release_pud
, pfn
);
350 static inline void paravirt_alloc_p4d(struct mm_struct
*mm
, unsigned long pfn
)
352 PVOP_VCALL2(pv_mmu_ops
.alloc_p4d
, mm
, pfn
);
355 static inline void paravirt_release_p4d(unsigned long pfn
)
357 PVOP_VCALL1(pv_mmu_ops
.release_p4d
, pfn
);
360 static inline pte_t
__pte(pteval_t val
)
364 if (sizeof(pteval_t
) > sizeof(long))
365 ret
= PVOP_CALLEE2(pteval_t
,
367 val
, (u64
)val
>> 32);
369 ret
= PVOP_CALLEE1(pteval_t
,
373 return (pte_t
) { .pte
= ret
};
376 static inline pteval_t
pte_val(pte_t pte
)
380 if (sizeof(pteval_t
) > sizeof(long))
381 ret
= PVOP_CALLEE2(pteval_t
, pv_mmu_ops
.pte_val
,
382 pte
.pte
, (u64
)pte
.pte
>> 32);
384 ret
= PVOP_CALLEE1(pteval_t
, pv_mmu_ops
.pte_val
,
390 static inline pgd_t
__pgd(pgdval_t val
)
394 if (sizeof(pgdval_t
) > sizeof(long))
395 ret
= PVOP_CALLEE2(pgdval_t
, pv_mmu_ops
.make_pgd
,
396 val
, (u64
)val
>> 32);
398 ret
= PVOP_CALLEE1(pgdval_t
, pv_mmu_ops
.make_pgd
,
401 return (pgd_t
) { ret
};
404 static inline pgdval_t
pgd_val(pgd_t pgd
)
408 if (sizeof(pgdval_t
) > sizeof(long))
409 ret
= PVOP_CALLEE2(pgdval_t
, pv_mmu_ops
.pgd_val
,
410 pgd
.pgd
, (u64
)pgd
.pgd
>> 32);
412 ret
= PVOP_CALLEE1(pgdval_t
, pv_mmu_ops
.pgd_val
,
418 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
419 static inline pte_t
ptep_modify_prot_start(struct mm_struct
*mm
, unsigned long addr
,
424 ret
= PVOP_CALL3(pteval_t
, pv_mmu_ops
.ptep_modify_prot_start
,
427 return (pte_t
) { .pte
= ret
};
430 static inline void ptep_modify_prot_commit(struct mm_struct
*mm
, unsigned long addr
,
431 pte_t
*ptep
, pte_t pte
)
433 if (sizeof(pteval_t
) > sizeof(long))
435 pv_mmu_ops
.ptep_modify_prot_commit(mm
, addr
, ptep
, pte
);
437 PVOP_VCALL4(pv_mmu_ops
.ptep_modify_prot_commit
,
438 mm
, addr
, ptep
, pte
.pte
);
441 static inline void set_pte(pte_t
*ptep
, pte_t pte
)
443 if (sizeof(pteval_t
) > sizeof(long))
444 PVOP_VCALL3(pv_mmu_ops
.set_pte
, ptep
,
445 pte
.pte
, (u64
)pte
.pte
>> 32);
447 PVOP_VCALL2(pv_mmu_ops
.set_pte
, ptep
,
451 static inline void set_pte_at(struct mm_struct
*mm
, unsigned long addr
,
452 pte_t
*ptep
, pte_t pte
)
454 if (sizeof(pteval_t
) > sizeof(long))
456 pv_mmu_ops
.set_pte_at(mm
, addr
, ptep
, pte
);
458 PVOP_VCALL4(pv_mmu_ops
.set_pte_at
, mm
, addr
, ptep
, pte
.pte
);
461 static inline void set_pmd(pmd_t
*pmdp
, pmd_t pmd
)
463 pmdval_t val
= native_pmd_val(pmd
);
465 if (sizeof(pmdval_t
) > sizeof(long))
466 PVOP_VCALL3(pv_mmu_ops
.set_pmd
, pmdp
, val
, (u64
)val
>> 32);
468 PVOP_VCALL2(pv_mmu_ops
.set_pmd
, pmdp
, val
);
471 #if CONFIG_PGTABLE_LEVELS >= 3
472 static inline pmd_t
__pmd(pmdval_t val
)
476 if (sizeof(pmdval_t
) > sizeof(long))
477 ret
= PVOP_CALLEE2(pmdval_t
, pv_mmu_ops
.make_pmd
,
478 val
, (u64
)val
>> 32);
480 ret
= PVOP_CALLEE1(pmdval_t
, pv_mmu_ops
.make_pmd
,
483 return (pmd_t
) { ret
};
486 static inline pmdval_t
pmd_val(pmd_t pmd
)
490 if (sizeof(pmdval_t
) > sizeof(long))
491 ret
= PVOP_CALLEE2(pmdval_t
, pv_mmu_ops
.pmd_val
,
492 pmd
.pmd
, (u64
)pmd
.pmd
>> 32);
494 ret
= PVOP_CALLEE1(pmdval_t
, pv_mmu_ops
.pmd_val
,
500 static inline void set_pud(pud_t
*pudp
, pud_t pud
)
502 pudval_t val
= native_pud_val(pud
);
504 if (sizeof(pudval_t
) > sizeof(long))
505 PVOP_VCALL3(pv_mmu_ops
.set_pud
, pudp
,
506 val
, (u64
)val
>> 32);
508 PVOP_VCALL2(pv_mmu_ops
.set_pud
, pudp
,
511 #if CONFIG_PGTABLE_LEVELS >= 4
512 static inline pud_t
__pud(pudval_t val
)
516 if (sizeof(pudval_t
) > sizeof(long))
517 ret
= PVOP_CALLEE2(pudval_t
, pv_mmu_ops
.make_pud
,
518 val
, (u64
)val
>> 32);
520 ret
= PVOP_CALLEE1(pudval_t
, pv_mmu_ops
.make_pud
,
523 return (pud_t
) { ret
};
526 static inline pudval_t
pud_val(pud_t pud
)
530 if (sizeof(pudval_t
) > sizeof(long))
531 ret
= PVOP_CALLEE2(pudval_t
, pv_mmu_ops
.pud_val
,
532 pud
.pud
, (u64
)pud
.pud
>> 32);
534 ret
= PVOP_CALLEE1(pudval_t
, pv_mmu_ops
.pud_val
,
540 static inline void pud_clear(pud_t
*pudp
)
542 set_pud(pudp
, __pud(0));
545 static inline void set_p4d(p4d_t
*p4dp
, p4d_t p4d
)
547 p4dval_t val
= native_p4d_val(p4d
);
549 if (sizeof(p4dval_t
) > sizeof(long))
550 PVOP_VCALL3(pv_mmu_ops
.set_p4d
, p4dp
,
551 val
, (u64
)val
>> 32);
553 PVOP_VCALL2(pv_mmu_ops
.set_p4d
, p4dp
,
557 #if CONFIG_PGTABLE_LEVELS >= 5
559 static inline p4d_t
__p4d(p4dval_t val
)
561 p4dval_t ret
= PVOP_CALLEE1(p4dval_t
, pv_mmu_ops
.make_p4d
, val
);
563 return (p4d_t
) { ret
};
566 static inline p4dval_t
p4d_val(p4d_t p4d
)
568 return PVOP_CALLEE1(p4dval_t
, pv_mmu_ops
.p4d_val
, p4d
.p4d
);
571 static inline void set_pgd(pgd_t
*pgdp
, pgd_t pgd
)
573 pgdval_t val
= native_pgd_val(pgd
);
575 PVOP_VCALL2(pv_mmu_ops
.set_pgd
, pgdp
, val
);
578 static inline void pgd_clear(pgd_t
*pgdp
)
580 set_pgd(pgdp
, __pgd(0));
583 #endif /* CONFIG_PGTABLE_LEVELS == 5 */
585 static inline void p4d_clear(p4d_t
*p4dp
)
587 set_p4d(p4dp
, __p4d(0));
590 #endif /* CONFIG_PGTABLE_LEVELS == 4 */
592 #endif /* CONFIG_PGTABLE_LEVELS >= 3 */
594 #ifdef CONFIG_X86_PAE
595 /* Special-case pte-setting operations for PAE, which can't update a
596 64-bit pte atomically */
597 static inline void set_pte_atomic(pte_t
*ptep
, pte_t pte
)
599 PVOP_VCALL3(pv_mmu_ops
.set_pte_atomic
, ptep
,
600 pte
.pte
, pte
.pte
>> 32);
603 static inline void pte_clear(struct mm_struct
*mm
, unsigned long addr
,
606 PVOP_VCALL3(pv_mmu_ops
.pte_clear
, mm
, addr
, ptep
);
609 static inline void pmd_clear(pmd_t
*pmdp
)
611 PVOP_VCALL1(pv_mmu_ops
.pmd_clear
, pmdp
);
613 #else /* !CONFIG_X86_PAE */
614 static inline void set_pte_atomic(pte_t
*ptep
, pte_t pte
)
619 static inline void pte_clear(struct mm_struct
*mm
, unsigned long addr
,
622 set_pte_at(mm
, addr
, ptep
, __pte(0));
625 static inline void pmd_clear(pmd_t
*pmdp
)
627 set_pmd(pmdp
, __pmd(0));
629 #endif /* CONFIG_X86_PAE */
631 #define __HAVE_ARCH_START_CONTEXT_SWITCH
632 static inline void arch_start_context_switch(struct task_struct
*prev
)
634 PVOP_VCALL1(pv_cpu_ops
.start_context_switch
, prev
);
637 static inline void arch_end_context_switch(struct task_struct
*next
)
639 PVOP_VCALL1(pv_cpu_ops
.end_context_switch
, next
);
642 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
643 static inline void arch_enter_lazy_mmu_mode(void)
645 PVOP_VCALL0(pv_mmu_ops
.lazy_mode
.enter
);
648 static inline void arch_leave_lazy_mmu_mode(void)
650 PVOP_VCALL0(pv_mmu_ops
.lazy_mode
.leave
);
653 static inline void arch_flush_lazy_mmu_mode(void)
655 PVOP_VCALL0(pv_mmu_ops
.lazy_mode
.flush
);
658 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx
,
659 phys_addr_t phys
, pgprot_t flags
)
661 pv_mmu_ops
.set_fixmap(idx
, phys
, flags
);
664 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
666 static __always_inline
void pv_queued_spin_lock_slowpath(struct qspinlock
*lock
,
669 PVOP_VCALL2(pv_lock_ops
.queued_spin_lock_slowpath
, lock
, val
);
672 static __always_inline
void pv_queued_spin_unlock(struct qspinlock
*lock
)
674 PVOP_VCALLEE1(pv_lock_ops
.queued_spin_unlock
, lock
);
677 static __always_inline
void pv_wait(u8
*ptr
, u8 val
)
679 PVOP_VCALL2(pv_lock_ops
.wait
, ptr
, val
);
682 static __always_inline
void pv_kick(int cpu
)
684 PVOP_VCALL1(pv_lock_ops
.kick
, cpu
);
687 static __always_inline
bool pv_vcpu_is_preempted(long cpu
)
689 return PVOP_CALLEE1(bool, pv_lock_ops
.vcpu_is_preempted
, cpu
);
692 #endif /* SMP && PARAVIRT_SPINLOCKS */
695 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
696 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
698 /* save and restore all caller-save registers, except return value */
699 #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;"
700 #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;"
702 #define PV_FLAGS_ARG "0"
703 #define PV_EXTRA_CLOBBERS
704 #define PV_VEXTRA_CLOBBERS
706 /* save and restore all caller-save registers, except return value */
707 #define PV_SAVE_ALL_CALLER_REGS \
716 #define PV_RESTORE_ALL_CALLER_REGS \
726 /* We save some registers, but all of them, that's too much. We clobber all
727 * caller saved registers but the argument parameter */
728 #define PV_SAVE_REGS "pushq %%rdi;"
729 #define PV_RESTORE_REGS "popq %%rdi;"
730 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
731 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
732 #define PV_FLAGS_ARG "D"
736 * Generate a thunk around a function which saves all caller-save
737 * registers except for the return value. This allows C functions to
738 * be called from assembler code where fewer than normal registers are
739 * available. It may also help code generation around calls from C
740 * code if the common case doesn't use many registers.
742 * When a callee is wrapped in a thunk, the caller can assume that all
743 * arg regs and all scratch registers are preserved across the
744 * call. The return value in rax/eax will not be saved, even for void
747 #define PV_THUNK_NAME(func) "__raw_callee_save_" #func
748 #define PV_CALLEE_SAVE_REGS_THUNK(func) \
749 extern typeof(func) __raw_callee_save_##func; \
751 asm(".pushsection .text;" \
752 ".globl " PV_THUNK_NAME(func) ";" \
753 ".type " PV_THUNK_NAME(func) ", @function;" \
754 PV_THUNK_NAME(func) ":" \
756 PV_SAVE_ALL_CALLER_REGS \
758 PV_RESTORE_ALL_CALLER_REGS \
763 /* Get a reference to a callee-save function */
764 #define PV_CALLEE_SAVE(func) \
765 ((struct paravirt_callee_save) { __raw_callee_save_##func })
767 /* Promise that "func" already uses the right calling convention */
768 #define __PV_IS_CALLEE_SAVE(func) \
769 ((struct paravirt_callee_save) { func })
771 static inline notrace
unsigned long arch_local_save_flags(void)
773 return PVOP_CALLEE0(unsigned long, pv_irq_ops
.save_fl
);
776 static inline notrace
void arch_local_irq_restore(unsigned long f
)
778 PVOP_VCALLEE1(pv_irq_ops
.restore_fl
, f
);
781 static inline notrace
void arch_local_irq_disable(void)
783 PVOP_VCALLEE0(pv_irq_ops
.irq_disable
);
786 static inline notrace
void arch_local_irq_enable(void)
788 PVOP_VCALLEE0(pv_irq_ops
.irq_enable
);
791 static inline notrace
unsigned long arch_local_irq_save(void)
795 f
= arch_local_save_flags();
796 arch_local_irq_disable();
801 /* Make sure as little as possible of this mess escapes. */
816 extern void default_banner(void);
818 #else /* __ASSEMBLY__ */
820 #define _PVSITE(ptype, clobbers, ops, word, algn) \
824 .pushsection .parainstructions,"a"; \
833 #define COND_PUSH(set, mask, reg) \
834 .if ((~(set)) & mask); push %reg; .endif
835 #define COND_POP(set, mask, reg) \
836 .if ((~(set)) & mask); pop %reg; .endif
840 #define PV_SAVE_REGS(set) \
841 COND_PUSH(set, CLBR_RAX, rax); \
842 COND_PUSH(set, CLBR_RCX, rcx); \
843 COND_PUSH(set, CLBR_RDX, rdx); \
844 COND_PUSH(set, CLBR_RSI, rsi); \
845 COND_PUSH(set, CLBR_RDI, rdi); \
846 COND_PUSH(set, CLBR_R8, r8); \
847 COND_PUSH(set, CLBR_R9, r9); \
848 COND_PUSH(set, CLBR_R10, r10); \
849 COND_PUSH(set, CLBR_R11, r11)
850 #define PV_RESTORE_REGS(set) \
851 COND_POP(set, CLBR_R11, r11); \
852 COND_POP(set, CLBR_R10, r10); \
853 COND_POP(set, CLBR_R9, r9); \
854 COND_POP(set, CLBR_R8, r8); \
855 COND_POP(set, CLBR_RDI, rdi); \
856 COND_POP(set, CLBR_RSI, rsi); \
857 COND_POP(set, CLBR_RDX, rdx); \
858 COND_POP(set, CLBR_RCX, rcx); \
859 COND_POP(set, CLBR_RAX, rax)
861 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
862 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
863 #define PARA_INDIRECT(addr) *addr(%rip)
865 #define PV_SAVE_REGS(set) \
866 COND_PUSH(set, CLBR_EAX, eax); \
867 COND_PUSH(set, CLBR_EDI, edi); \
868 COND_PUSH(set, CLBR_ECX, ecx); \
869 COND_PUSH(set, CLBR_EDX, edx)
870 #define PV_RESTORE_REGS(set) \
871 COND_POP(set, CLBR_EDX, edx); \
872 COND_POP(set, CLBR_ECX, ecx); \
873 COND_POP(set, CLBR_EDI, edi); \
874 COND_POP(set, CLBR_EAX, eax)
876 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
877 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
878 #define PARA_INDIRECT(addr) *%cs:addr
881 #define INTERRUPT_RETURN \
882 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
883 ANNOTATE_RETPOLINE_SAFE; \
884 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret);)
886 #define DISABLE_INTERRUPTS(clobbers) \
887 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
888 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
889 ANNOTATE_RETPOLINE_SAFE; \
890 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \
891 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
893 #define ENABLE_INTERRUPTS(clobbers) \
894 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
895 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
896 ANNOTATE_RETPOLINE_SAFE; \
897 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \
898 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
901 #define GET_CR0_INTO_EAX \
902 push %ecx; push %edx; \
903 ANNOTATE_RETPOLINE_SAFE; \
904 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \
906 #else /* !CONFIG_X86_32 */
909 * If swapgs is used while the userspace stack is still current,
910 * there's no way to call a pvop. The PV replacement *must* be
911 * inlined, or the swapgs instruction must be trapped and emulated.
913 #define SWAPGS_UNSAFE_STACK \
914 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
918 * Note: swapgs is very special, and in practise is either going to be
919 * implemented with a single "swapgs" instruction or something very
920 * special. Either way, we don't need to save any registers for
924 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
925 ANNOTATE_RETPOLINE_SAFE; \
926 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs); \
929 #define GET_CR2_INTO_RAX \
930 ANNOTATE_RETPOLINE_SAFE; \
931 call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2);
933 #define USERGS_SYSRET64 \
934 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \
936 ANNOTATE_RETPOLINE_SAFE; \
937 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64);)
939 #ifdef CONFIG_DEBUG_ENTRY
940 #define SAVE_FLAGS(clobbers) \
941 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_save_fl), clobbers, \
942 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
943 ANNOTATE_RETPOLINE_SAFE; \
944 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_save_fl); \
945 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
948 #endif /* CONFIG_X86_32 */
950 #endif /* __ASSEMBLY__ */
951 #else /* CONFIG_PARAVIRT */
952 # define default_banner x86_init_noop
954 static inline void paravirt_arch_dup_mmap(struct mm_struct
*oldmm
,
955 struct mm_struct
*mm
)
959 static inline void paravirt_arch_exit_mmap(struct mm_struct
*mm
)
962 #endif /* __ASSEMBLY__ */
963 #endif /* !CONFIG_PARAVIRT */
964 #endif /* _ASM_X86_PARAVIRT_H */