2 * arch/xtensa/include/asm/traps.h
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2012 Tensilica Inc.
10 #ifndef _XTENSA_TRAPS_H
11 #define _XTENSA_TRAPS_H
13 #include <asm/ptrace.h>
16 * Per-CPU exception handling data structure.
17 * EXCSAVE1 points to it.
22 /* Double exception save area for a0 */
23 unsigned long double_save
;
26 /* For passing a parameter to fixup */
28 /* For fast syscall handler */
29 unsigned long syscall_save
;
30 /* Fast user exception handlers */
31 void *fast_user_handler
[EXCCAUSE_N
];
32 /* Fast kernel exception handlers */
33 void *fast_kernel_handler
[EXCCAUSE_N
];
34 /* Default C-Handlers */
35 void *default_handler
[EXCCAUSE_N
];
39 * handler must be either of the following:
40 * void (*)(struct pt_regs *regs);
41 * void (*)(struct pt_regs *regs, unsigned long exccause);
43 extern void * __init
trap_set_handler(int cause
, void *handler
);
44 extern void do_unhandled(struct pt_regs
*regs
, unsigned long exccause
);
45 void fast_second_level_miss(void);
47 /* Initialize minimal exc_table structure sufficient for basic paging */
48 static inline void __init
early_trap_init(void)
50 static struct exc_table exc_table __initdata
= {
51 .fast_kernel_handler
[EXCCAUSE_DTLB_MISS
] =
52 fast_second_level_miss
,
54 __asm__
__volatile__("wsr %0, excsave1\n" : : "a" (&exc_table
));
57 void secondary_trap_init(void);
59 static inline void spill_registers(void)
61 #if XCHAL_NUM_AREGS > 16
62 __asm__
__volatile__ (
68 #if XCHAL_NUM_AREGS == 32
80 " .rept (" __stringify(XCHAL_NUM_AREGS
) " - 16) / 12\n"
85 #if XCHAL_NUM_AREGS % 12 == 0
87 #elif XCHAL_NUM_AREGS % 12 == 4
89 #elif XCHAL_NUM_AREGS % 12 == 8
95 : : : "a8", "a9", "memory");
97 __asm__
__volatile__ (
104 /* Pointer to debug exception handler */
105 void (*debug_exception
)(void);
106 /* Temporary register save area */
107 unsigned long debug_save
[1];
108 #ifdef CONFIG_HAVE_HW_BREAKPOINT
109 /* Save area for DBREAKC registers */
110 unsigned long dbreakc_save
[XCHAL_NUM_DBREAK
];
111 /* Saved ICOUNT register */
112 unsigned long icount_save
;
113 /* Saved ICOUNTLEVEL register */
114 unsigned long icount_level_save
;
118 void debug_exception(void);
120 #endif /* _XTENSA_TRAPS_H */