arch/xtensa/kernel/pci.c

   1 /*
   2  * arch/xtensa/kernel/pci.c
   3  *
   4  * PCI bios-type initialisation for PCI machines
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  * Copyright (C) 2001-2005 Tensilica Inc.
  12  *
  13  * Based largely on work from Cort (ppc/kernel/pci.c)
  14  * IO functions copied from sparc.
  15  *
  16  * Chris Zankel <chris@zankel.net>
  17  *
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/delay.h>
  23 #include <linux/string.h>
  24 #include <linux/init.h>
  25 #include <linux/sched.h>
  26 #include <linux/errno.h>
  27 #include <linux/bootmem.h>
  28
  29 #include <asm/pci-bridge.h>
  30 #include <asm/platform.h>
  31
  32 /* PCI Controller */
  33
  34
  35 /*
  36  * pcibios_alloc_controller
  37  * pcibios_enable_device
  38  * pcibios_fixups
  39  * pcibios_align_resource
  40  * pcibios_fixup_bus
  41  * pci_bus_add_device
  42  * pci_mmap_page_range
  43  */
  44
  45 struct pci_controller* pci_ctrl_head;
  46 struct pci_controller** pci_ctrl_tail = &pci_ctrl_head;
  47
  48 static int pci_bus_count;
  49
  50 /*
  51  * We need to avoid collisions with `mirrored' VGA ports
  52  * and other strange ISA hardware, so we always want the
  53  * addresses to be allocated in the 0x000-0x0ff region
  54  * modulo 0x400.
  55  *
  56  * Why? Because some silly external IO cards only decode
  57  * the low 10 bits of the IO address. The 0x00-0xff region
  58  * is reserved for motherboard devices that decode all 16
  59  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  60  * but we want to try to avoid allocating at 0x2900-0x2bff
  61  * which might have be mirrored at 0x0100-0x03ff..
  62  */
  63 resource_size_t
  64 pcibios_align_resource(void *data, const struct resource *res,
  65                        resource_size_t size, resource_size_t align)
  66 {
  67         struct pci_dev *dev = data;
  68         resource_size_t start = res->start;
  69
  70         if (res->flags & IORESOURCE_IO) {
  71                 if (size > 0x100) {
  72                         pr_err("PCI: I/O Region %s/%d too large (%u bytes)\n",
  73                                         pci_name(dev), dev->resource - res,
  74                                         size);
  75                 }
  76
  77                 if (start & 0x300)
  78                         start = (start + 0x3ff) & ~0x3ff;
  79         }
  80
  81         return start;
  82 }
  83
  84 int
  85 pcibios_enable_resources(struct pci_dev *dev, int mask)
  86 {
  87         u16 cmd, old_cmd;
  88         int idx;
  89         struct resource *r;
  90
  91         pci_read_config_word(dev, PCI_COMMAND, &cmd);
  92         old_cmd = cmd;
  93         for(idx=0; idx<6; idx++) {
  94                 r = &dev->resource[idx];
  95                 if (!r->start && r->end) {
  96                         pr_err("PCI: Device %s not available because "
  97                                "of resource collisions\n", pci_name(dev));
  98                         return -EINVAL;
  99                 }
 100                 if (r->flags & IORESOURCE_IO)
 101                         cmd |= PCI_COMMAND_IO;
 102                 if (r->flags & IORESOURCE_MEM)
 103                         cmd |= PCI_COMMAND_MEMORY;
 104         }
 105         if (dev->resource[PCI_ROM_RESOURCE].start)
 106                 cmd |= PCI_COMMAND_MEMORY;
 107         if (cmd != old_cmd) {
 108                 pr_info("PCI: Enabling device %s (%04x -> %04x)\n",
 109                         pci_name(dev), old_cmd, cmd);
 110                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 111         }
 112         return 0;
 113 }
 114
 115 struct pci_controller * __init pcibios_alloc_controller(void)
 116 {
 117         struct pci_controller *pci_ctrl;
 118
 119         pci_ctrl = (struct pci_controller *)alloc_bootmem(sizeof(*pci_ctrl));
 120         memset(pci_ctrl, 0, sizeof(struct pci_controller));
 121
 122         *pci_ctrl_tail = pci_ctrl;
 123         pci_ctrl_tail = &pci_ctrl->next;
 124
 125         return pci_ctrl;
 126 }
 127
 128 static void __init pci_controller_apertures(struct pci_controller *pci_ctrl,
 129                                             struct list_head *resources)
 130 {
 131         struct resource *res;
 132         unsigned long io_offset;
 133         int i;
 134
 135         io_offset = (unsigned long)pci_ctrl->io_space.base;
 136         res = &pci_ctrl->io_resource;
 137         if (!res->flags) {
 138                 if (io_offset)
 139                         pr_err("I/O resource not set for host bridge %d\n",
 140                                pci_ctrl->index);
 141                 res->start = 0;
 142                 res->end = IO_SPACE_LIMIT;
 143                 res->flags = IORESOURCE_IO;
 144         }
 145         res->start += io_offset;
 146         res->end += io_offset;
 147         pci_add_resource_offset(resources, res, io_offset);
 148
 149         for (i = 0; i < 3; i++) {
 150                 res = &pci_ctrl->mem_resources[i];
 151                 if (!res->flags) {
 152                         if (i > 0)
 153                                 continue;
 154                         pr_err("Memory resource not set for host bridge %d\n",
 155                                pci_ctrl->index);
 156                         res->start = 0;
 157                         res->end = ~0U;
 158                         res->flags = IORESOURCE_MEM;
 159                 }
 160                 pci_add_resource(resources, res);
 161         }
 162 }
 163
 164 static int __init pcibios_init(void)
 165 {
 166         struct pci_controller *pci_ctrl;
 167         struct list_head resources;
 168         struct pci_bus *bus;
 169         int next_busno = 0, ret;
 170
 171         pr_info("PCI: Probing PCI hardware\n");
 172
 173         /* Scan all of the recorded PCI controllers.  */
 174         for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
 175                 pci_ctrl->last_busno = 0xff;
 176                 INIT_LIST_HEAD(&resources);
 177                 pci_controller_apertures(pci_ctrl, &resources);
 178                 bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
 179                                         pci_ctrl->ops, pci_ctrl, &resources);
 180                 if (!bus)
 181                         continue;
 182
 183                 pci_ctrl->bus = bus;
 184                 pci_ctrl->last_busno = bus->busn_res.end;
 185                 if (next_busno <= pci_ctrl->last_busno)
 186                         next_busno = pci_ctrl->last_busno+1;
 187         }
 188         pci_bus_count = next_busno;
 189         ret = platform_pcibios_fixup();
 190         if (ret)
 191                 return ret;
 192
 193         for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
 194                 if (pci_ctrl->bus)
 195                         pci_bus_add_devices(pci_ctrl->bus);
 196         }
 197
 198         return 0;
 199 }
 200
 201 subsys_initcall(pcibios_init);
 202
 203 void pcibios_fixup_bus(struct pci_bus *bus)
 204 {
 205         if (bus->parent) {
 206                 /* This is a subordinate bridge */
 207                 pci_read_bridge_bases(bus);
 208         }
 209 }
 210
 211 void pcibios_set_master(struct pci_dev *dev)
 212 {
 213         /* No special bus mastering setup handling */
 214 }
 215
 216 int pcibios_enable_device(struct pci_dev *dev, int mask)
 217 {
 218         u16 cmd, old_cmd;
 219         int idx;
 220         struct resource *r;
 221
 222         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 223         old_cmd = cmd;
 224         for (idx=0; idx<6; idx++) {
 225                 r = &dev->resource[idx];
 226                 if (!r->start && r->end) {
 227                         pr_err("PCI: Device %s not available because "
 228                                "of resource collisions\n", pci_name(dev));
 229                         return -EINVAL;
 230                 }
 231                 if (r->flags & IORESOURCE_IO)
 232                         cmd |= PCI_COMMAND_IO;
 233                 if (r->flags & IORESOURCE_MEM)
 234                         cmd |= PCI_COMMAND_MEMORY;
 235         }
 236         if (cmd != old_cmd) {
 237                 pr_info("PCI: Enabling device %s (%04x -> %04x)\n",
 238                         pci_name(dev), old_cmd, cmd);
 239                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 240         }
 241
 242         return 0;
 243 }
 244
 245 #ifdef CONFIG_PROC_FS
 246
 247 /*
 248  * Return the index of the PCI controller for device pdev.
 249  */
 250
 251 int
 252 pci_controller_num(struct pci_dev *dev)
 253 {
 254         struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
 255         return pci_ctrl->index;
 256 }
 257
 258 #endif /* CONFIG_PROC_FS */
 259
 260 /*
 261  * Platform support for /proc/bus/pci/X/Y mmap()s,
 262  * modelled on the sparc64 implementation by Dave Miller.
 263  *  -- paulus.
 264  */
 265
 266 /*
 267  * Adjust vm_pgoff of VMA such that it is the physical page offset
 268  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
 269  *
 270  * Basically, the user finds the base address for his device which he wishes
 271  * to mmap.  They read the 32-bit value from the config space base register,
 272  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 273  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 274  *
 275  * Returns negative error code on failure, zero on success.
 276  */
 277 static __inline__ int
 278 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
 279                        enum pci_mmap_state mmap_state)
 280 {
 281         struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
 282         unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
 283         unsigned long io_offset = 0;
 284         int i, res_bit;
 285
 286         if (pci_ctrl == 0)
 287                 return -EINVAL;         /* should never happen */
 288
 289         /* If memory, add on the PCI bridge address offset */
 290         if (mmap_state == pci_mmap_mem) {
 291                 res_bit = IORESOURCE_MEM;
 292         } else {
 293                 io_offset = (unsigned long)pci_ctrl->io_space.base;
 294                 offset += io_offset;
 295                 res_bit = IORESOURCE_IO;
 296         }
 297
 298         /*
 299          * Check that the offset requested corresponds to one of the
 300          * resources of the device.
 301          */
 302         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 303                 struct resource *rp = &dev->resource[i];
 304                 int flags = rp->flags;
 305
 306                 /* treat ROM as memory (should be already) */
 307                 if (i == PCI_ROM_RESOURCE)
 308                         flags |= IORESOURCE_MEM;
 309
 310                 /* Active and same type? */
 311                 if ((flags & res_bit) == 0)
 312                         continue;
 313
 314                 /* In the range of this resource? */
 315                 if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
 316                         continue;
 317
 318                 /* found it! construct the final physical address */
 319                 if (mmap_state == pci_mmap_io)
 320                         offset += pci_ctrl->io_space.start - io_offset;
 321                 vma->vm_pgoff = offset >> PAGE_SHIFT;
 322                 return 0;
 323         }
 324
 325         return -EINVAL;
 326 }
 327
 328 /*
 329  * Perform the actual remap of the pages for a PCI device mapping, as
 330  * appropriate for this architecture.  The region in the process to map
 331  * is described by vm_start and vm_end members of VMA, the base physical
 332  * address is found in vm_pgoff.
 333  * The pci device structure is provided so that architectures may make mapping
 334  * decisions on a per-device or per-bus basis.
 335  *
 336  * Returns a negative error code on failure, zero on success.
 337  */
 338 int pci_mmap_page_range(struct pci_dev *dev, int bar,
 339                         struct vm_area_struct *vma,
 340                         enum pci_mmap_state mmap_state,
 341                         int write_combine)
 342 {
 343         int ret;
 344
 345         ret = __pci_mmap_make_offset(dev, vma, mmap_state);
 346         if (ret < 0)
 347                 return ret;
 348
 349         vma->vm_page_prot = pgprot_device(vma->vm_page_prot);
 350
 351         ret = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 352                                  vma->vm_end - vma->vm_start,vma->vm_page_prot);
 353
 354         return ret;
 355 }