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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / edac / skx_edac.c
blob912c4930c9efb8e58116731c9711d53311515574
1 /*
2 * EDAC driver for Intel(R) Xeon(R) Skylake processors
3 * Copyright (c) 2016, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/pci.h>
18 #include <linux/pci_ids.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/edac.h>
22 #include <linux/mmzone.h>
23 #include <linux/smp.h>
24 #include <linux/bitmap.h>
25 #include <linux/math64.h>
26 #include <linux/mod_devicetable.h>
27 #include <asm/cpu_device_id.h>
28 #include <asm/intel-family.h>
29 #include <asm/processor.h>
30 #include <asm/mce.h>
31
32 #include "edac_module.h"
33
34 #define EDAC_MOD_STR "skx_edac"
35
36 /*
37 * Debug macros
38 */
39 #define skx_printk(level, fmt, arg...) \
40 edac_printk(level, "skx", fmt, ##arg)
41
42 #define skx_mc_printk(mci, level, fmt, arg...) \
43 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
44
45 /*
46 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
47 */
48 #define GET_BITFIELD(v, lo, hi) \
49 (((v) & GENMASK_ULL((hi), (lo))) >> (lo))
50
51 static LIST_HEAD(skx_edac_list);
52
53 static u64 skx_tolm, skx_tohm;
54
55 #define NUM_IMC 2 /* memory controllers per socket */
56 #define NUM_CHANNELS 3 /* channels per memory controller */
57 #define NUM_DIMMS 2 /* Max DIMMS per channel */
58
59 #define MASK26 0x3FFFFFF /* Mask for 2^26 */
60 #define MASK29 0x1FFFFFFF /* Mask for 2^29 */
61
62 /*
63 * Each cpu socket contains some pci devices that provide global
64 * information, and also some that are local to each of the two
65 * memory controllers on the die.
66 */
67 struct skx_dev {
68 struct list_head list;
69 u8 bus[4];
70 int seg;
71 struct pci_dev *sad_all;
72 struct pci_dev *util_all;
73 u32 mcroute;
74 struct skx_imc {
75 struct mem_ctl_info *mci;
76 u8 mc; /* system wide mc# */
77 u8 lmc; /* socket relative mc# */
78 u8 src_id, node_id;
79 struct skx_channel {
80 struct pci_dev *cdev;
81 struct skx_dimm {
82 u8 close_pg;
83 u8 bank_xor_enable;
84 u8 fine_grain_bank;
85 u8 rowbits;
86 u8 colbits;
87 } dimms[NUM_DIMMS];
88 } chan[NUM_CHANNELS];
89 } imc[NUM_IMC];
90 };
91 static int skx_num_sockets;
92
93 struct skx_pvt {
94 struct skx_imc *imc;
95 };
96
97 struct decoded_addr {
98 struct skx_dev *dev;
99 u64 addr;
100 int socket;
101 int imc;
102 int channel;
103 u64 chan_addr;
104 int sktways;
105 int chanways;
106 int dimm;
107 int rank;
108 int channel_rank;
109 u64 rank_address;
110 int row;
111 int column;
112 int bank_address;
113 int bank_group;
114 };
115
116 static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx)
117 {
118 struct skx_dev *d;
119
120 list_for_each_entry(d, &skx_edac_list, list) {
121 if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number)
122 return d;
123 }
124
125 return NULL;
126 }
127
128 enum munittype {
129 CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD
130 };
131
132 struct munit {
133 u16 did;
134 u16 devfn[NUM_IMC];
135 u8 busidx;
136 u8 per_socket;
137 enum munittype mtype;
138 };
139
140 /*
141 * List of PCI device ids that we need together with some device
142 * number and function numbers to tell which memory controller the
143 * device belongs to.
144 */
145 static const struct munit skx_all_munits[] = {
146 { 0x2054, { }, 1, 1, SAD_ALL },
147 { 0x2055, { }, 1, 1, UTIL_ALL },
148 { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 },
149 { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 },
150 { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 },
151 { 0x208e, { }, 1, 0, SAD },
152 { }
153 };
154
155 /*
156 * We use the per-socket device 0x2016 to count how many sockets are present,
157 * and to detemine which PCI buses are associated with each socket. Allocate
158 * and build the full list of all the skx_dev structures that we need here.
159 */
160 static int get_all_bus_mappings(void)
161 {
162 struct pci_dev *pdev, *prev;
163 struct skx_dev *d;
164 u32 reg;
165 int ndev = 0;
166
167 prev = NULL;
168 for (;;) {
169 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2016, prev);
170 if (!pdev)
171 break;
172 ndev++;
173 d = kzalloc(sizeof(*d), GFP_KERNEL);
174 if (!d) {
175 pci_dev_put(pdev);
176 return -ENOMEM;
177 }
178 d->seg = pci_domain_nr(pdev->bus);
179 pci_read_config_dword(pdev, 0xCC, &reg);
180 d->bus[0] = GET_BITFIELD(reg, 0, 7);
181 d->bus[1] = GET_BITFIELD(reg, 8, 15);
182 d->bus[2] = GET_BITFIELD(reg, 16, 23);
183 d->bus[3] = GET_BITFIELD(reg, 24, 31);
184 edac_dbg(2, "busses: %x, %x, %x, %x\n",
185 d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
186 list_add_tail(&d->list, &skx_edac_list);
187 skx_num_sockets++;
188 prev = pdev;
189 }
190
191 return ndev;
192 }
193
194 static int get_all_munits(const struct munit *m)
195 {
196 struct pci_dev *pdev, *prev;
197 struct skx_dev *d;
198 u32 reg;
199 int i = 0, ndev = 0;
200
201 prev = NULL;
202 for (;;) {
203 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev);
204 if (!pdev)
205 break;
206 ndev++;
207 if (m->per_socket == NUM_IMC) {
208 for (i = 0; i < NUM_IMC; i++)
209 if (m->devfn[i] == pdev->devfn)
210 break;
211 if (i == NUM_IMC)
212 goto fail;
213 }
214 d = get_skx_dev(pdev->bus, m->busidx);
215 if (!d)
216 goto fail;
217
218 /* Be sure that the device is enabled */
219 if (unlikely(pci_enable_device(pdev) < 0)) {
220 skx_printk(KERN_ERR,
221 "Couldn't enable %04x:%04x\n", PCI_VENDOR_ID_INTEL, m->did);
222 goto fail;
223 }
224
225 switch (m->mtype) {
226 case CHAN0: case CHAN1: case CHAN2:
227 pci_dev_get(pdev);
228 d->imc[i].chan[m->mtype].cdev = pdev;
229 break;
230 case SAD_ALL:
231 pci_dev_get(pdev);
232 d->sad_all = pdev;
233 break;
234 case UTIL_ALL:
235 pci_dev_get(pdev);
236 d->util_all = pdev;
237 break;
238 case SAD:
239 /*
240 * one of these devices per core, including cores
241 * that don't exist on this SKU. Ignore any that
242 * read a route table of zero, make sure all the
243 * non-zero values match.
244 */
245 pci_read_config_dword(pdev, 0xB4, &reg);
246 if (reg != 0) {
247 if (d->mcroute == 0)
248 d->mcroute = reg;
249 else if (d->mcroute != reg) {
250 skx_printk(KERN_ERR,
251 "mcroute mismatch\n");
252 goto fail;
253 }
254 }
255 ndev--;
256 break;
257 }
258
259 prev = pdev;
260 }
261
262 return ndev;
263 fail:
264 pci_dev_put(pdev);
265 return -ENODEV;
266 }
267
268 static const struct x86_cpu_id skx_cpuids[] = {
269 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X, 0, 0 },
270 { }
271 };
272 MODULE_DEVICE_TABLE(x86cpu, skx_cpuids);
273
274 static u8 get_src_id(struct skx_dev *d)
275 {
276 u32 reg;
277
278 pci_read_config_dword(d->util_all, 0xF0, &reg);
279
280 return GET_BITFIELD(reg, 12, 14);
281 }
282
283 static u8 skx_get_node_id(struct skx_dev *d)
284 {
285 u32 reg;
286
287 pci_read_config_dword(d->util_all, 0xF4, &reg);
288
289 return GET_BITFIELD(reg, 0, 2);
290 }
291
292 static int get_dimm_attr(u32 reg, int lobit, int hibit, int add, int minval,
293 int maxval, char *name)
294 {
295 u32 val = GET_BITFIELD(reg, lobit, hibit);
296
297 if (val < minval || val > maxval) {
298 edac_dbg(2, "bad %s = %d (raw=%x)\n", name, val, reg);
299 return -EINVAL;
300 }
301 return val + add;
302 }
303
304 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD((mtr), 15, 15)
305
306 #define numrank(reg) get_dimm_attr((reg), 12, 13, 0, 0, 2, "ranks")
307 #define numrow(reg) get_dimm_attr((reg), 2, 4, 12, 1, 6, "rows")
308 #define numcol(reg) get_dimm_attr((reg), 0, 1, 10, 0, 2, "cols")
309
310 static int get_width(u32 mtr)
311 {
312 switch (GET_BITFIELD(mtr, 8, 9)) {
313 case 0:
314 return DEV_X4;
315 case 1:
316 return DEV_X8;
317 case 2:
318 return DEV_X16;
319 }
320 return DEV_UNKNOWN;
321 }
322
323 static int skx_get_hi_lo(void)
324 {
325 struct pci_dev *pdev;
326 u32 reg;
327
328 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2034, NULL);
329 if (!pdev) {
330 edac_dbg(0, "Can't get tolm/tohm\n");
331 return -ENODEV;
332 }
333
334 pci_read_config_dword(pdev, 0xD0, &reg);
335 skx_tolm = reg;
336 pci_read_config_dword(pdev, 0xD4, &reg);
337 skx_tohm = reg;
338 pci_read_config_dword(pdev, 0xD8, &reg);
339 skx_tohm |= (u64)reg << 32;
340
341 pci_dev_put(pdev);
342 edac_dbg(2, "tolm=%llx tohm=%llx\n", skx_tolm, skx_tohm);
343
344 return 0;
345 }
346
347 static int get_dimm_info(u32 mtr, u32 amap, struct dimm_info *dimm,
348 struct skx_imc *imc, int chan, int dimmno)
349 {
350 int banks = 16, ranks, rows, cols, npages;
351 u64 size;
352
353 if (!IS_DIMM_PRESENT(mtr))
354 return 0;
355 ranks = numrank(mtr);
356 rows = numrow(mtr);
357 cols = numcol(mtr);
358
359 /*
360 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
361 */
362 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
363 npages = MiB_TO_PAGES(size);
364
365 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
366 imc->mc, chan, dimmno, size, npages,
367 banks, 1 << ranks, rows, cols);
368
369 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mtr, 0, 0);
370 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mtr, 9, 9);
371 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
372 imc->chan[chan].dimms[dimmno].rowbits = rows;
373 imc->chan[chan].dimms[dimmno].colbits = cols;
374
375 dimm->nr_pages = npages;
376 dimm->grain = 32;
377 dimm->dtype = get_width(mtr);
378 dimm->mtype = MEM_DDR4;
379 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
380 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
381 imc->src_id, imc->lmc, chan, dimmno);
382
383 return 1;
384 }
385
386 #define SKX_GET_MTMTR(dev, reg) \
387 pci_read_config_dword((dev), 0x87c, &reg)
388
389 static bool skx_check_ecc(struct pci_dev *pdev)
390 {
391 u32 mtmtr;
392
393 SKX_GET_MTMTR(pdev, mtmtr);
394
395 return !!GET_BITFIELD(mtmtr, 2, 2);
396 }
397
398 static int skx_get_dimm_config(struct mem_ctl_info *mci)
399 {
400 struct skx_pvt *pvt = mci->pvt_info;
401 struct skx_imc *imc = pvt->imc;
402 struct dimm_info *dimm;
403 int i, j;
404 u32 mtr, amap;
405 int ndimms;
406
407 for (i = 0; i < NUM_CHANNELS; i++) {
408 ndimms = 0;
409 pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap);
410 for (j = 0; j < NUM_DIMMS; j++) {
411 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
412 mci->n_layers, i, j, 0);
413 pci_read_config_dword(imc->chan[i].cdev,
414 0x80 + 4*j, &mtr);
415 ndimms += get_dimm_info(mtr, amap, dimm, imc, i, j);
416 }
417 if (ndimms && !skx_check_ecc(imc->chan[0].cdev)) {
418 skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc);
419 return -ENODEV;
420 }
421 }
422
423 return 0;
424 }
425
426 static void skx_unregister_mci(struct skx_imc *imc)
427 {
428 struct mem_ctl_info *mci = imc->mci;
429
430 if (!mci)
431 return;
432
433 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
434
435 /* Remove MC sysfs nodes */
436 edac_mc_del_mc(mci->pdev);
437
438 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
439 kfree(mci->ctl_name);
440 edac_mc_free(mci);
441 }
442
443 static int skx_register_mci(struct skx_imc *imc)
444 {
445 struct mem_ctl_info *mci;
446 struct edac_mc_layer layers[2];
447 struct pci_dev *pdev = imc->chan[0].cdev;
448 struct skx_pvt *pvt;
449 int rc;
450
451 /* allocate a new MC control structure */
452 layers[0].type = EDAC_MC_LAYER_CHANNEL;
453 layers[0].size = NUM_CHANNELS;
454 layers[0].is_virt_csrow = false;
455 layers[1].type = EDAC_MC_LAYER_SLOT;
456 layers[1].size = NUM_DIMMS;
457 layers[1].is_virt_csrow = true;
458 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
459 sizeof(struct skx_pvt));
460
461 if (unlikely(!mci))
462 return -ENOMEM;
463
464 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
465
466 /* Associate skx_dev and mci for future usage */
467 imc->mci = mci;
468 pvt = mci->pvt_info;
469 pvt->imc = imc;
470
471 mci->ctl_name = kasprintf(GFP_KERNEL, "Skylake Socket#%d IMC#%d", imc->node_id, imc->lmc);
472 if (!mci->ctl_name) {
473 rc = -ENOMEM;
474 goto fail0;
475 }
476
477 mci->mtype_cap = MEM_FLAG_DDR4;
478 mci->edac_ctl_cap = EDAC_FLAG_NONE;
479 mci->edac_cap = EDAC_FLAG_NONE;
480 mci->mod_name = EDAC_MOD_STR;
481 mci->dev_name = pci_name(imc->chan[0].cdev);
482 mci->ctl_page_to_phys = NULL;
483
484 rc = skx_get_dimm_config(mci);
485 if (rc < 0)
486 goto fail;
487
488 /* record ptr to the generic device */
489 mci->pdev = &pdev->dev;
490
491 /* add this new MC control structure to EDAC's list of MCs */
492 if (unlikely(edac_mc_add_mc(mci))) {
493 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
494 rc = -EINVAL;
495 goto fail;
496 }
497
498 return 0;
499
500 fail:
501 kfree(mci->ctl_name);
502 fail0:
503 edac_mc_free(mci);
504 imc->mci = NULL;
505 return rc;
506 }
507
508 #define SKX_MAX_SAD 24
509
510 #define SKX_GET_SAD(d, i, reg) \
511 pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &reg)
512 #define SKX_GET_ILV(d, i, reg) \
513 pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &reg)
514
515 #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31)
516 #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27)
517 #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26)
518 #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6)
519 #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4)
520 #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2)
521 #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0)
522
523 #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0)
524 #define SKX_ILV_TARGET(tgt) ((tgt) & 7)
525
526 static bool skx_sad_decode(struct decoded_addr *res)
527 {
528 struct skx_dev *d = list_first_entry(&skx_edac_list, typeof(*d), list);
529 u64 addr = res->addr;
530 int i, idx, tgt, lchan, shift;
531 u32 sad, ilv;
532 u64 limit, prev_limit;
533 int remote = 0;
534
535 /* Simple sanity check for I/O space or out of range */
536 if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) {
537 edac_dbg(0, "Address %llx out of range\n", addr);
538 return false;
539 }
540
541 restart:
542 prev_limit = 0;
543 for (i = 0; i < SKX_MAX_SAD; i++) {
544 SKX_GET_SAD(d, i, sad);
545 limit = SKX_SAD_LIMIT(sad);
546 if (SKX_SAD_ENABLE(sad)) {
547 if (addr >= prev_limit && addr <= limit)
548 goto sad_found;
549 }
550 prev_limit = limit + 1;
551 }
552 edac_dbg(0, "No SAD entry for %llx\n", addr);
553 return false;
554
555 sad_found:
556 SKX_GET_ILV(d, i, ilv);
557
558 switch (SKX_SAD_INTERLEAVE(sad)) {
559 case 0:
560 idx = GET_BITFIELD(addr, 6, 8);
561 break;
562 case 1:
563 idx = GET_BITFIELD(addr, 8, 10);
564 break;
565 case 2:
566 idx = GET_BITFIELD(addr, 12, 14);
567 break;
568 case 3:
569 idx = GET_BITFIELD(addr, 30, 32);
570 break;
571 }
572
573 tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3);
574
575 /* If point to another node, find it and start over */
576 if (SKX_ILV_REMOTE(tgt)) {
577 if (remote) {
578 edac_dbg(0, "Double remote!\n");
579 return false;
580 }
581 remote = 1;
582 list_for_each_entry(d, &skx_edac_list, list) {
583 if (d->imc[0].src_id == SKX_ILV_TARGET(tgt))
584 goto restart;
585 }
586 edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt));
587 return false;
588 }
589
590 if (SKX_SAD_MOD3(sad) == 0)
591 lchan = SKX_ILV_TARGET(tgt);
592 else {
593 switch (SKX_SAD_MOD3MODE(sad)) {
594 case 0:
595 shift = 6;
596 break;
597 case 1:
598 shift = 8;
599 break;
600 case 2:
601 shift = 12;
602 break;
603 default:
604 edac_dbg(0, "illegal mod3mode\n");
605 return false;
606 }
607 switch (SKX_SAD_MOD3ASMOD2(sad)) {
608 case 0:
609 lchan = (addr >> shift) % 3;
610 break;
611 case 1:
612 lchan = (addr >> shift) % 2;
613 break;
614 case 2:
615 lchan = (addr >> shift) % 2;
616 lchan = (lchan << 1) | ~lchan;
617 break;
618 case 3:
619 lchan = ((addr >> shift) % 2) << 1;
620 break;
621 }
622 lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1);
623 }
624
625 res->dev = d;
626 res->socket = d->imc[0].src_id;
627 res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2);
628 res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19);
629
630 edac_dbg(2, "%llx: socket=%d imc=%d channel=%d\n",
631 res->addr, res->socket, res->imc, res->channel);
632 return true;
633 }
634
635 #define SKX_MAX_TAD 8
636
637 #define SKX_GET_TADBASE(d, mc, i, reg) \
638 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &reg)
639 #define SKX_GET_TADWAYNESS(d, mc, i, reg) \
640 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &reg)
641 #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \
642 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &reg)
643
644 #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26)
645 #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5)
646 #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7)
647 #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26)
648 #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26)
649 #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11))
650 #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1)
651
652 /* which bit used for both socket and channel interleave */
653 static int skx_granularity[] = { 6, 8, 12, 30 };
654
655 static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits)
656 {
657 addr >>= shift;
658 addr /= ways;
659 addr <<= shift;
660
661 return addr | (lowbits & ((1ull << shift) - 1));
662 }
663
664 static bool skx_tad_decode(struct decoded_addr *res)
665 {
666 int i;
667 u32 base, wayness, chnilvoffset;
668 int skt_interleave_bit, chn_interleave_bit;
669 u64 channel_addr;
670
671 for (i = 0; i < SKX_MAX_TAD; i++) {
672 SKX_GET_TADBASE(res->dev, res->imc, i, base);
673 SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness);
674 if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness))
675 goto tad_found;
676 }
677 edac_dbg(0, "No TAD entry for %llx\n", res->addr);
678 return false;
679
680 tad_found:
681 res->sktways = SKX_TAD_SKTWAYS(wayness);
682 res->chanways = SKX_TAD_CHNWAYS(wayness);
683 skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)];
684 chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)];
685
686 SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset);
687 channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset);
688
689 if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) {
690 /* Must handle channel first, then socket */
691 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
692 res->chanways, channel_addr);
693 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
694 res->sktways, channel_addr);
695 } else {
696 /* Handle socket then channel. Preserve low bits from original address */
697 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
698 res->sktways, res->addr);
699 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
700 res->chanways, res->addr);
701 }
702
703 res->chan_addr = channel_addr;
704
705 edac_dbg(2, "%llx: chan_addr=%llx sktways=%d chanways=%d\n",
706 res->addr, res->chan_addr, res->sktways, res->chanways);
707 return true;
708 }
709
710 #define SKX_MAX_RIR 4
711
712 #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \
713 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
714 0x108 + 4 * (i), &reg)
715 #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \
716 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
717 0x120 + 16 * idx + 4 * (i), &reg)
718
719 #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31)
720 #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29)
721 #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29))
722 #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19)
723 #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26))
724
725 static bool skx_rir_decode(struct decoded_addr *res)
726 {
727 int i, idx, chan_rank;
728 int shift;
729 u32 rirway, rirlv;
730 u64 rank_addr, prev_limit = 0, limit;
731
732 if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg)
733 shift = 6;
734 else
735 shift = 13;
736
737 for (i = 0; i < SKX_MAX_RIR; i++) {
738 SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway);
739 limit = SKX_RIR_LIMIT(rirway);
740 if (SKX_RIR_VALID(rirway)) {
741 if (prev_limit <= res->chan_addr &&
742 res->chan_addr <= limit)
743 goto rir_found;
744 }
745 prev_limit = limit;
746 }
747 edac_dbg(0, "No RIR entry for %llx\n", res->addr);
748 return false;
749
750 rir_found:
751 rank_addr = res->chan_addr >> shift;
752 rank_addr /= SKX_RIR_WAYS(rirway);
753 rank_addr <<= shift;
754 rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0);
755
756 res->rank_address = rank_addr;
757 idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway);
758
759 SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv);
760 res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv);
761 chan_rank = SKX_RIR_CHAN_RANK(rirlv);
762 res->channel_rank = chan_rank;
763 res->dimm = chan_rank / 4;
764 res->rank = chan_rank % 4;
765
766 edac_dbg(2, "%llx: dimm=%d rank=%d chan_rank=%d rank_addr=%llx\n",
767 res->addr, res->dimm, res->rank,
768 res->channel_rank, res->rank_address);
769 return true;
770 }
771
772 static u8 skx_close_row[] = {
773 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33
774 };
775 static u8 skx_close_column[] = {
776 3, 4, 5, 14, 19, 23, 24, 25, 26, 27
777 };
778 static u8 skx_open_row[] = {
779 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33
780 };
781 static u8 skx_open_column[] = {
782 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
783 };
784 static u8 skx_open_fine_column[] = {
785 3, 4, 5, 7, 8, 9, 10, 11, 12, 13
786 };
787
788 static int skx_bits(u64 addr, int nbits, u8 *bits)
789 {
790 int i, res = 0;
791
792 for (i = 0; i < nbits; i++)
793 res |= ((addr >> bits[i]) & 1) << i;
794 return res;
795 }
796
797 static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1)
798 {
799 int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);
800
801 if (do_xor)
802 ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);
803
804 return ret;
805 }
806
807 static bool skx_mad_decode(struct decoded_addr *r)
808 {
809 struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm];
810 int bg0 = dimm->fine_grain_bank ? 6 : 13;
811
812 if (dimm->close_pg) {
813 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row);
814 r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column);
815 r->column |= 0x400; /* C10 is autoprecharge, always set */
816 r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28);
817 r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21);
818 } else {
819 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row);
820 if (dimm->fine_grain_bank)
821 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column);
822 else
823 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column);
824 r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23);
825 r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21);
826 }
827 r->row &= (1u << dimm->rowbits) - 1;
828
829 edac_dbg(2, "%llx: row=%x col=%x bank_addr=%d bank_group=%d\n",
830 r->addr, r->row, r->column, r->bank_address,
831 r->bank_group);
832 return true;
833 }
834
835 static bool skx_decode(struct decoded_addr *res)
836 {
837
838 return skx_sad_decode(res) && skx_tad_decode(res) &&
839 skx_rir_decode(res) && skx_mad_decode(res);
840 }
841
842 #ifdef CONFIG_EDAC_DEBUG
843 /*
844 * Debug feature. Make /sys/kernel/debug/skx_edac_test/addr.
845 * Write an address to this file to exercise the address decode
846 * logic in this driver.
847 */
848 static struct dentry *skx_test;
849 static u64 skx_fake_addr;
850
851 static int debugfs_u64_set(void *data, u64 val)
852 {
853 struct decoded_addr res;
854
855 res.addr = val;
856 skx_decode(&res);
857
858 return 0;
859 }
860
861 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
862
863 static struct dentry *mydebugfs_create(const char *name, umode_t mode,
864 struct dentry *parent, u64 *value)
865 {
866 return debugfs_create_file(name, mode, parent, value, &fops_u64_wo);
867 }
868
869 static void setup_skx_debug(void)
870 {
871 skx_test = debugfs_create_dir("skx_edac_test", NULL);
872 mydebugfs_create("addr", S_IWUSR, skx_test, &skx_fake_addr);
873 }
874
875 static void teardown_skx_debug(void)
876 {
877 debugfs_remove_recursive(skx_test);
878 }
879 #else
880 static void setup_skx_debug(void)
881 {
882 }
883
884 static void teardown_skx_debug(void)
885 {
886 }
887 #endif /*CONFIG_EDAC_DEBUG*/
888
889 static void skx_mce_output_error(struct mem_ctl_info *mci,
890 const struct mce *m,
891 struct decoded_addr *res)
892 {
893 enum hw_event_mc_err_type tp_event;
894 char *type, *optype, msg[256];
895 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
896 bool overflow = GET_BITFIELD(m->status, 62, 62);
897 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
898 bool recoverable;
899 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
900 u32 mscod = GET_BITFIELD(m->status, 16, 31);
901 u32 errcode = GET_BITFIELD(m->status, 0, 15);
902 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
903
904 recoverable = GET_BITFIELD(m->status, 56, 56);
905
906 if (uncorrected_error) {
907 if (ripv) {
908 type = "FATAL";
909 tp_event = HW_EVENT_ERR_FATAL;
910 } else {
911 type = "NON_FATAL";
912 tp_event = HW_EVENT_ERR_UNCORRECTED;
913 }
914 } else {
915 type = "CORRECTED";
916 tp_event = HW_EVENT_ERR_CORRECTED;
917 }
918
919 /*
920 * According with Table 15-9 of the Intel Architecture spec vol 3A,
921 * memory errors should fit in this mask:
922 * 000f 0000 1mmm cccc (binary)
923 * where:
924 * f = Correction Report Filtering Bit. If 1, subsequent errors
925 * won't be shown
926 * mmm = error type
927 * cccc = channel
928 * If the mask doesn't match, report an error to the parsing logic
929 */
930 if (!((errcode & 0xef80) == 0x80)) {
931 optype = "Can't parse: it is not a mem";
932 } else {
933 switch (optypenum) {
934 case 0:
935 optype = "generic undef request error";
936 break;
937 case 1:
938 optype = "memory read error";
939 break;
940 case 2:
941 optype = "memory write error";
942 break;
943 case 3:
944 optype = "addr/cmd error";
945 break;
946 case 4:
947 optype = "memory scrubbing error";
948 break;
949 default:
950 optype = "reserved";
951 break;
952 }
953 }
954
955 snprintf(msg, sizeof(msg),
956 "%s%s err_code:%04x:%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:%x col:%x",
957 overflow ? " OVERFLOW" : "",
958 (uncorrected_error && recoverable) ? " recoverable" : "",
959 mscod, errcode,
960 res->socket, res->imc, res->rank,
961 res->bank_group, res->bank_address, res->row, res->column);
962
963 edac_dbg(0, "%s\n", msg);
964
965 /* Call the helper to output message */
966 edac_mc_handle_error(tp_event, mci, core_err_cnt,
967 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
968 res->channel, res->dimm, -1,
969 optype, msg);
970 }
971
972 static int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
973 void *data)
974 {
975 struct mce *mce = (struct mce *)data;
976 struct decoded_addr res;
977 struct mem_ctl_info *mci;
978 char *type;
979
980 if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
981 return NOTIFY_DONE;
982
983 /* ignore unless this is memory related with an address */
984 if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV))
985 return NOTIFY_DONE;
986
987 res.addr = mce->addr;
988 if (!skx_decode(&res))
989 return NOTIFY_DONE;
990 mci = res.dev->imc[res.imc].mci;
991
992 if (mce->mcgstatus & MCG_STATUS_MCIP)
993 type = "Exception";
994 else
995 type = "Event";
996
997 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
998
999 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
1000 "Bank %d: %016Lx\n", mce->extcpu, type,
1001 mce->mcgstatus, mce->bank, mce->status);
1002 skx_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
1003 skx_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
1004 skx_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
1005
1006 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
1007 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
1008 mce->time, mce->socketid, mce->apicid);
1009
1010 skx_mce_output_error(mci, mce, &res);
1011
1012 return NOTIFY_DONE;
1013 }
1014
1015 static struct notifier_block skx_mce_dec = {
1016 .notifier_call = skx_mce_check_error,
1017 .priority = MCE_PRIO_EDAC,
1018 };
1019
1020 static void skx_remove(void)
1021 {
1022 int i, j;
1023 struct skx_dev *d, *tmp;
1024
1025 edac_dbg(0, "\n");
1026
1027 list_for_each_entry_safe(d, tmp, &skx_edac_list, list) {
1028 list_del(&d->list);
1029 for (i = 0; i < NUM_IMC; i++) {
1030 skx_unregister_mci(&d->imc[i]);
1031 for (j = 0; j < NUM_CHANNELS; j++)
1032 pci_dev_put(d->imc[i].chan[j].cdev);
1033 }
1034 pci_dev_put(d->util_all);
1035 pci_dev_put(d->sad_all);
1036
1037 kfree(d);
1038 }
1039 }
1040
1041 /*
1042 * skx_init:
1043 * make sure we are running on the correct cpu model
1044 * search for all the devices we need
1045 * check which DIMMs are present.
1046 */
1047 static int __init skx_init(void)
1048 {
1049 const struct x86_cpu_id *id;
1050 const struct munit *m;
1051 const char *owner;
1052 int rc = 0, i;
1053 u8 mc = 0, src_id, node_id;
1054 struct skx_dev *d;
1055
1056 edac_dbg(2, "\n");
1057
1058 owner = edac_get_owner();
1059 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
1060 return -EBUSY;
1061
1062 id = x86_match_cpu(skx_cpuids);
1063 if (!id)
1064 return -ENODEV;
1065
1066 rc = skx_get_hi_lo();
1067 if (rc)
1068 return rc;
1069
1070 rc = get_all_bus_mappings();
1071 if (rc < 0)
1072 goto fail;
1073 if (rc == 0) {
1074 edac_dbg(2, "No memory controllers found\n");
1075 return -ENODEV;
1076 }
1077
1078 for (m = skx_all_munits; m->did; m++) {
1079 rc = get_all_munits(m);
1080 if (rc < 0)
1081 goto fail;
1082 if (rc != m->per_socket * skx_num_sockets) {
1083 edac_dbg(2, "Expected %d, got %d of %x\n",
1084 m->per_socket * skx_num_sockets, rc, m->did);
1085 rc = -ENODEV;
1086 goto fail;
1087 }
1088 }
1089
1090 list_for_each_entry(d, &skx_edac_list, list) {
1091 src_id = get_src_id(d);
1092 node_id = skx_get_node_id(d);
1093 edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id);
1094 for (i = 0; i < NUM_IMC; i++) {
1095 d->imc[i].mc = mc++;
1096 d->imc[i].lmc = i;
1097 d->imc[i].src_id = src_id;
1098 d->imc[i].node_id = node_id;
1099 rc = skx_register_mci(&d->imc[i]);
1100 if (rc < 0)
1101 goto fail;
1102 }
1103 }
1104
1105 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1106 opstate_init();
1107
1108 setup_skx_debug();
1109
1110 mce_register_decode_chain(&skx_mce_dec);
1111
1112 return 0;
1113 fail:
1114 skx_remove();
1115 return rc;
1116 }
1117
1118 static void __exit skx_exit(void)
1119 {
1120 edac_dbg(2, "\n");
1121 mce_unregister_decode_chain(&skx_mce_dec);
1122 skx_remove();
1123 teardown_skx_debug();
1124 }
1125
1126 module_init(skx_init);
1127 module_exit(skx_exit);
1128
1129 module_param(edac_op_state, int, 0444);
1130 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1131
1132 MODULE_LICENSE("GPL v2");
1133 MODULE_AUTHOR("Tony Luck");
1134 MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors");
CRIS linux kernel tree