drivers/gpio/gpio-sch.c

   1 /*
   2  * GPIO interface for Intel Poulsbo SCH
   3  *
   4  *  Copyright (c) 2010 CompuLab Ltd
   5  *  Author: Denis Turischev <denis@compulab.co.il>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License 2 as published
   9  *  by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; see the file COPYING.  If not, write to
  18  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/io.h>
  25 #include <linux/errno.h>
  26 #include <linux/acpi.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pci_ids.h>
  29
  30 #include <linux/gpio.h>
  31
  32 #define GEN     0x00
  33 #define GIO     0x04
  34 #define GLV     0x08
  35
  36 struct sch_gpio {
  37         struct gpio_chip chip;
  38         spinlock_t lock;
  39         unsigned short iobase;
  40         unsigned short core_base;
  41         unsigned short resume_base;
  42 };
  43
  44 static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
  45                                 unsigned reg)
  46 {
  47         unsigned base = 0;
  48
  49         if (gpio >= sch->resume_base) {
  50                 gpio -= sch->resume_base;
  51                 base += 0x20;
  52         }
  53
  54         return base + reg + gpio / 8;
  55 }
  56
  57 static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
  58 {
  59         if (gpio >= sch->resume_base)
  60                 gpio -= sch->resume_base;
  61         return gpio % 8;
  62 }
  63
  64 static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned gpio, unsigned reg)
  65 {
  66         unsigned short offset, bit;
  67         u8 reg_val;
  68
  69         offset = sch_gpio_offset(sch, gpio, reg);
  70         bit = sch_gpio_bit(sch, gpio);
  71
  72         reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
  73
  74         return reg_val;
  75 }
  76
  77 static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned gpio, unsigned reg,
  78                              int val)
  79 {
  80         unsigned short offset, bit;
  81         u8 reg_val;
  82
  83         offset = sch_gpio_offset(sch, gpio, reg);
  84         bit = sch_gpio_bit(sch, gpio);
  85
  86         reg_val = inb(sch->iobase + offset);
  87
  88         if (val)
  89                 outb(reg_val | BIT(bit), sch->iobase + offset);
  90         else
  91                 outb((reg_val & ~BIT(bit)), sch->iobase + offset);
  92 }
  93
  94 static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
  95 {
  96         struct sch_gpio *sch = gpiochip_get_data(gc);
  97
  98         spin_lock(&sch->lock);
  99         sch_gpio_reg_set(sch, gpio_num, GIO, 1);
 100         spin_unlock(&sch->lock);
 101         return 0;
 102 }
 103
 104 static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
 105 {
 106         struct sch_gpio *sch = gpiochip_get_data(gc);
 107         return sch_gpio_reg_get(sch, gpio_num, GLV);
 108 }
 109
 110 static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
 111 {
 112         struct sch_gpio *sch = gpiochip_get_data(gc);
 113
 114         spin_lock(&sch->lock);
 115         sch_gpio_reg_set(sch, gpio_num, GLV, val);
 116         spin_unlock(&sch->lock);
 117 }
 118
 119 static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
 120                                   int val)
 121 {
 122         struct sch_gpio *sch = gpiochip_get_data(gc);
 123
 124         spin_lock(&sch->lock);
 125         sch_gpio_reg_set(sch, gpio_num, GIO, 0);
 126         spin_unlock(&sch->lock);
 127
 128         /*
 129          * according to the datasheet, writing to the level register has no
 130          * effect when GPIO is programmed as input.
 131          * Actually the the level register is read-only when configured as input.
 132          * Thus presetting the output level before switching to output is _NOT_ possible.
 133          * Hence we set the level after configuring the GPIO as output.
 134          * But we cannot prevent a short low pulse if direction is set to high
 135          * and an external pull-up is connected.
 136          */
 137         sch_gpio_set(gc, gpio_num, val);
 138         return 0;
 139 }
 140
 141 static const struct gpio_chip sch_gpio_chip = {
 142         .label                  = "sch_gpio",
 143         .owner                  = THIS_MODULE,
 144         .direction_input        = sch_gpio_direction_in,
 145         .get                    = sch_gpio_get,
 146         .direction_output       = sch_gpio_direction_out,
 147         .set                    = sch_gpio_set,
 148 };
 149
 150 static int sch_gpio_probe(struct platform_device *pdev)
 151 {
 152         struct sch_gpio *sch;
 153         struct resource *res;
 154
 155         sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
 156         if (!sch)
 157                 return -ENOMEM;
 158
 159         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
 160         if (!res)
 161                 return -EBUSY;
 162
 163         if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
 164                                  pdev->name))
 165                 return -EBUSY;
 166
 167         spin_lock_init(&sch->lock);
 168         sch->iobase = res->start;
 169         sch->chip = sch_gpio_chip;
 170         sch->chip.label = dev_name(&pdev->dev);
 171         sch->chip.parent = &pdev->dev;
 172
 173         switch (pdev->id) {
 174         case PCI_DEVICE_ID_INTEL_SCH_LPC:
 175                 sch->core_base = 0;
 176                 sch->resume_base = 10;
 177                 sch->chip.ngpio = 14;
 178
 179                 /*
 180                  * GPIO[6:0] enabled by default
 181                  * GPIO7 is configured by the CMC as SLPIOVR
 182                  * Enable GPIO[9:8] core powered gpios explicitly
 183                  */
 184                 sch_gpio_reg_set(sch, 8, GEN, 1);
 185                 sch_gpio_reg_set(sch, 9, GEN, 1);
 186                 /*
 187                  * SUS_GPIO[2:0] enabled by default
 188                  * Enable SUS_GPIO3 resume powered gpio explicitly
 189                  */
 190                 sch_gpio_reg_set(sch, 13, GEN, 1);
 191                 break;
 192
 193         case PCI_DEVICE_ID_INTEL_ITC_LPC:
 194                 sch->core_base = 0;
 195                 sch->resume_base = 5;
 196                 sch->chip.ngpio = 14;
 197                 break;
 198
 199         case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
 200                 sch->core_base = 0;
 201                 sch->resume_base = 21;
 202                 sch->chip.ngpio = 30;
 203                 break;
 204
 205         case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
 206                 sch->core_base = 0;
 207                 sch->resume_base = 2;
 208                 sch->chip.ngpio = 8;
 209                 break;
 210
 211         default:
 212                 return -ENODEV;
 213         }
 214
 215         platform_set_drvdata(pdev, sch);
 216
 217         return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
 218 }
 219
 220 static struct platform_driver sch_gpio_driver = {
 221         .driver = {
 222                 .name = "sch_gpio",
 223         },
 224         .probe          = sch_gpio_probe,
 225 };
 226
 227 module_platform_driver(sch_gpio_driver);
 228
 229 MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
 230 MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
 231 MODULE_LICENSE("GPL");
 232 MODULE_ALIAS("platform:sch_gpio");