drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/printk.h>
  25 #include <linux/slab.h>
  26 #include <linux/mm_types.h>
  27
  28 #include "kfd_priv.h"
  29 #include "kfd_mqd_manager.h"
  30 #include "vi_structs.h"
  31 #include "gca/gfx_8_0_sh_mask.h"
  32 #include "gca/gfx_8_0_enum.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
  35
  36 static inline struct vi_mqd *get_mqd(void *mqd)
  37 {
  38         return (struct vi_mqd *)mqd;
  39 }
  40
  41 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
  42 {
  43         return (struct vi_sdma_mqd *)mqd;
  44 }
  45
  46 static int init_mqd(struct mqd_manager *mm, void **mqd,
  47                         struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
  48                         struct queue_properties *q)
  49 {
  50         int retval;
  51         uint64_t addr;
  52         struct vi_mqd *m;
  53
  54         retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct vi_mqd),
  55                         mqd_mem_obj);
  56         if (retval != 0)
  57                 return -ENOMEM;
  58
  59         m = (struct vi_mqd *) (*mqd_mem_obj)->cpu_ptr;
  60         addr = (*mqd_mem_obj)->gpu_addr;
  61
  62         memset(m, 0, sizeof(struct vi_mqd));
  63
  64         m->header = 0xC0310800;
  65         m->compute_pipelinestat_enable = 1;
  66         m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
  67         m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
  68         m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
  69         m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
  70
  71         m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
  72                         0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
  73
  74         m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT |
  75                         MTYPE_UC << CP_MQD_CONTROL__MTYPE__SHIFT;
  76
  77         m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
  78         m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
  79
  80         m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
  81                         1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
  82                         10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
  83
  84         m->cp_hqd_pipe_priority = 1;
  85         m->cp_hqd_queue_priority = 15;
  86
  87         m->cp_hqd_eop_rptr = 1 << CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT;
  88
  89         if (q->format == KFD_QUEUE_FORMAT_AQL)
  90                 m->cp_hqd_iq_rptr = 1;
  91
  92         if (q->tba_addr) {
  93                 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8);
  94                 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8);
  95                 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8);
  96                 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8);
  97                 m->compute_pgm_rsrc2 |=
  98                         (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT);
  99         }
 100
 101         if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) {
 102                 m->cp_hqd_persistent_state |=
 103                         (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
 104                 m->cp_hqd_ctx_save_base_addr_lo =
 105                         lower_32_bits(q->ctx_save_restore_area_address);
 106                 m->cp_hqd_ctx_save_base_addr_hi =
 107                         upper_32_bits(q->ctx_save_restore_area_address);
 108                 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
 109                 m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
 110                 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
 111                 m->cp_hqd_wg_state_offset = q->ctl_stack_size;
 112         }
 113
 114         *mqd = m;
 115         if (gart_addr)
 116                 *gart_addr = addr;
 117         retval = mm->update_mqd(mm, m, q);
 118
 119         return retval;
 120 }
 121
 122 static int load_mqd(struct mqd_manager *mm, void *mqd,
 123                         uint32_t pipe_id, uint32_t queue_id,
 124                         struct queue_properties *p, struct mm_struct *mms)
 125 {
 126         /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
 127         uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
 128         uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
 129
 130         return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
 131                                           (uint32_t __user *)p->write_ptr,
 132                                           wptr_shift, wptr_mask, mms);
 133 }
 134
 135 static int __update_mqd(struct mqd_manager *mm, void *mqd,
 136                         struct queue_properties *q, unsigned int mtype,
 137                         unsigned int atc_bit)
 138 {
 139         struct vi_mqd *m;
 140
 141         m = get_mqd(mqd);
 142
 143         m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
 144                         atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
 145                         mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
 146         m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
 147         pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
 148
 149         m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
 150         m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
 151
 152         m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
 153         m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
 154
 155         m->cp_hqd_pq_doorbell_control =
 156                 q->doorbell_off <<
 157                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
 158         pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
 159                         m->cp_hqd_pq_doorbell_control);
 160
 161         m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT |
 162                         mtype << CP_HQD_EOP_CONTROL__MTYPE__SHIFT;
 163
 164         m->cp_hqd_ib_control = atc_bit << CP_HQD_IB_CONTROL__IB_ATC__SHIFT |
 165                         3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
 166                         mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT;
 167
 168         /*
 169          * HW does not clamp this field correctly. Maximum EOP queue size
 170          * is constrained by per-SE EOP done signal count, which is 8-bit.
 171          * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
 172          * more than (EOP entry count - 1) so a queue size of 0x800 dwords
 173          * is safe, giving a maximum field value of 0xA.
 174          */
 175         m->cp_hqd_eop_control |= min(0xA,
 176                 order_base_2(q->eop_ring_buffer_size / 4) - 1);
 177         m->cp_hqd_eop_base_addr_lo =
 178                         lower_32_bits(q->eop_ring_buffer_address >> 8);
 179         m->cp_hqd_eop_base_addr_hi =
 180                         upper_32_bits(q->eop_ring_buffer_address >> 8);
 181
 182         m->cp_hqd_iq_timer = atc_bit << CP_HQD_IQ_TIMER__IQ_ATC__SHIFT |
 183                         mtype << CP_HQD_IQ_TIMER__MTYPE__SHIFT;
 184
 185         m->cp_hqd_vmid = q->vmid;
 186
 187         if (q->format == KFD_QUEUE_FORMAT_AQL) {
 188                 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
 189                                 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT;
 190         }
 191
 192         if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address)
 193                 m->cp_hqd_ctx_save_control =
 194                         atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT |
 195                         mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT;
 196
 197         q->is_active = (q->queue_size > 0 &&
 198                         q->queue_address != 0 &&
 199                         q->queue_percent > 0);
 200
 201         return 0;
 202 }
 203
 204
 205 static int update_mqd(struct mqd_manager *mm, void *mqd,
 206                         struct queue_properties *q)
 207 {
 208         return __update_mqd(mm, mqd, q, MTYPE_CC, 1);
 209 }
 210
 211 static int destroy_mqd(struct mqd_manager *mm, void *mqd,
 212                         enum kfd_preempt_type type,
 213                         unsigned int timeout, uint32_t pipe_id,
 214                         uint32_t queue_id)
 215 {
 216         return mm->dev->kfd2kgd->hqd_destroy
 217                 (mm->dev->kgd, mqd, type, timeout,
 218                 pipe_id, queue_id);
 219 }
 220
 221 static void uninit_mqd(struct mqd_manager *mm, void *mqd,
 222                         struct kfd_mem_obj *mqd_mem_obj)
 223 {
 224         kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
 225 }
 226
 227 static bool is_occupied(struct mqd_manager *mm, void *mqd,
 228                         uint64_t queue_address, uint32_t pipe_id,
 229                         uint32_t queue_id)
 230 {
 231         return mm->dev->kfd2kgd->hqd_is_occupied(
 232                 mm->dev->kgd, queue_address,
 233                 pipe_id, queue_id);
 234 }
 235
 236 static int init_mqd_hiq(struct mqd_manager *mm, void **mqd,
 237                         struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
 238                         struct queue_properties *q)
 239 {
 240         struct vi_mqd *m;
 241         int retval = init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
 242
 243         if (retval != 0)
 244                 return retval;
 245
 246         m = get_mqd(*mqd);
 247
 248         m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
 249                         1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
 250
 251         return retval;
 252 }
 253
 254 static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
 255                         struct queue_properties *q)
 256 {
 257         struct vi_mqd *m;
 258         int retval = __update_mqd(mm, mqd, q, MTYPE_UC, 0);
 259
 260         if (retval != 0)
 261                 return retval;
 262
 263         m = get_mqd(mqd);
 264         m->cp_hqd_vmid = q->vmid;
 265         return retval;
 266 }
 267
 268 static int init_mqd_sdma(struct mqd_manager *mm, void **mqd,
 269                 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
 270                 struct queue_properties *q)
 271 {
 272         int retval;
 273         struct vi_sdma_mqd *m;
 274
 275
 276         retval = kfd_gtt_sa_allocate(mm->dev,
 277                         sizeof(struct vi_sdma_mqd),
 278                         mqd_mem_obj);
 279
 280         if (retval != 0)
 281                 return -ENOMEM;
 282
 283         m = (struct vi_sdma_mqd *) (*mqd_mem_obj)->cpu_ptr;
 284
 285         memset(m, 0, sizeof(struct vi_sdma_mqd));
 286
 287         *mqd = m;
 288         if (gart_addr != NULL)
 289                 *gart_addr = (*mqd_mem_obj)->gpu_addr;
 290
 291         retval = mm->update_mqd(mm, m, q);
 292
 293         return retval;
 294 }
 295
 296 static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd,
 297                 struct kfd_mem_obj *mqd_mem_obj)
 298 {
 299         kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
 300 }
 301
 302 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
 303                 uint32_t pipe_id, uint32_t queue_id,
 304                 struct queue_properties *p, struct mm_struct *mms)
 305 {
 306         return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
 307                                                (uint32_t __user *)p->write_ptr,
 308                                                mms);
 309 }
 310
 311 static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
 312                 struct queue_properties *q)
 313 {
 314         struct vi_sdma_mqd *m;
 315
 316         m = get_sdma_mqd(mqd);
 317         m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
 318                 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 319                 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
 320                 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 321                 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
 322
 323         m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
 324         m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
 325         m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
 326         m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
 327         m->sdmax_rlcx_doorbell =
 328                 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
 329
 330         m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr;
 331
 332         m->sdma_engine_id = q->sdma_engine_id;
 333         m->sdma_queue_id = q->sdma_queue_id;
 334
 335         q->is_active = (q->queue_size > 0 &&
 336                         q->queue_address != 0 &&
 337                         q->queue_percent > 0);
 338
 339         return 0;
 340 }
 341
 342 /*
 343  *  * preempt type here is ignored because there is only one way
 344  *  * to preempt sdma queue
 345  */
 346 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
 347                 enum kfd_preempt_type type,
 348                 unsigned int timeout, uint32_t pipe_id,
 349                 uint32_t queue_id)
 350 {
 351         return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
 352 }
 353
 354 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
 355                 uint64_t queue_address, uint32_t pipe_id,
 356                 uint32_t queue_id)
 357 {
 358         return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
 359 }
 360
 361 #if defined(CONFIG_DEBUG_FS)
 362
 363 static int debugfs_show_mqd(struct seq_file *m, void *data)
 364 {
 365         seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
 366                      data, sizeof(struct vi_mqd), false);
 367         return 0;
 368 }
 369
 370 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
 371 {
 372         seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
 373                      data, sizeof(struct vi_sdma_mqd), false);
 374         return 0;
 375 }
 376
 377 #endif
 378
 379 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
 380                 struct kfd_dev *dev)
 381 {
 382         struct mqd_manager *mqd;
 383
 384         if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
 385                 return NULL;
 386
 387         mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
 388         if (!mqd)
 389                 return NULL;
 390
 391         mqd->dev = dev;
 392
 393         switch (type) {
 394         case KFD_MQD_TYPE_CP:
 395         case KFD_MQD_TYPE_COMPUTE:
 396                 mqd->init_mqd = init_mqd;
 397                 mqd->uninit_mqd = uninit_mqd;
 398                 mqd->load_mqd = load_mqd;
 399                 mqd->update_mqd = update_mqd;
 400                 mqd->destroy_mqd = destroy_mqd;
 401                 mqd->is_occupied = is_occupied;
 402 #if defined(CONFIG_DEBUG_FS)
 403                 mqd->debugfs_show_mqd = debugfs_show_mqd;
 404 #endif
 405                 break;
 406         case KFD_MQD_TYPE_HIQ:
 407                 mqd->init_mqd = init_mqd_hiq;
 408                 mqd->uninit_mqd = uninit_mqd;
 409                 mqd->load_mqd = load_mqd;
 410                 mqd->update_mqd = update_mqd_hiq;
 411                 mqd->destroy_mqd = destroy_mqd;
 412                 mqd->is_occupied = is_occupied;
 413 #if defined(CONFIG_DEBUG_FS)
 414                 mqd->debugfs_show_mqd = debugfs_show_mqd;
 415 #endif
 416                 break;
 417         case KFD_MQD_TYPE_SDMA:
 418                 mqd->init_mqd = init_mqd_sdma;
 419                 mqd->uninit_mqd = uninit_mqd_sdma;
 420                 mqd->load_mqd = load_mqd_sdma;
 421                 mqd->update_mqd = update_mqd_sdma;
 422                 mqd->destroy_mqd = destroy_mqd_sdma;
 423                 mqd->is_occupied = is_occupied_sdma;
 424 #if defined(CONFIG_DEBUG_FS)
 425                 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
 426 #endif
 427                 break;
 428         default:
 429                 kfree(mqd);
 430                 return NULL;
 431         }
 432
 433         return mqd;
 434 }