?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / gpu / drm / i915 / intel_dp.c
blob35c5299feab6862659023ce54f3d99dd45aacbec
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
35 #include <drm/drmP.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
42 #include "i915_drv.h"
43
44 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
45 #define DP_DPRX_ESI_LEN 14
46
47 /* Compliance test status bits */
48 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
49 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
50 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
51 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
52
53 struct dp_link_dpll {
54 int clock;
55 struct dpll dpll;
56 };
57
58 static const struct dp_link_dpll gen4_dpll[] = {
59 { 162000,
60 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
61 { 270000,
62 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
63 };
64
65 static const struct dp_link_dpll pch_dpll[] = {
66 { 162000,
67 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
68 { 270000,
69 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
70 };
71
72 static const struct dp_link_dpll vlv_dpll[] = {
73 { 162000,
74 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
75 { 270000,
76 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
77 };
78
79 /*
80 * CHV supports eDP 1.4 that have more link rates.
81 * Below only provides the fixed rate but exclude variable rate.
82 */
83 static const struct dp_link_dpll chv_dpll[] = {
84 /*
85 * CHV requires to program fractional division for m2.
86 * m2 is stored in fixed point format using formula below
87 * (m2_int << 22) | m2_fraction
88 */
89 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
90 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
91 { 270000, /* m2_int = 27, m2_fraction = 0 */
92 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
93 { 540000, /* m2_int = 27, m2_fraction = 0 */
94 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
95 };
96
97 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
98 324000, 432000, 540000 };
99 static const int skl_rates[] = { 162000, 216000, 270000,
100 324000, 432000, 540000 };
101 static const int cnl_rates[] = { 162000, 216000, 270000,
102 324000, 432000, 540000,
103 648000, 810000 };
104 static const int default_rates[] = { 162000, 270000, 540000 };
105
106 /**
107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
108 * @intel_dp: DP struct
109 *
110 * If a CPU or PCH DP output is attached to an eDP panel, this function
111 * will return true, and false otherwise.
112 */
113 bool intel_dp_is_edp(struct intel_dp *intel_dp)
114 {
115 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
116
117 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
118 }
119
120 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
121 {
122 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
123
124 return intel_dig_port->base.base.dev;
125 }
126
127 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
128 {
129 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
130 }
131
132 static void intel_dp_link_down(struct intel_encoder *encoder,
133 const struct intel_crtc_state *old_crtc_state);
134 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
135 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
136 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
137 const struct intel_crtc_state *crtc_state);
138 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
139 enum pipe pipe);
140 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
141
142 /* update sink rates from dpcd */
143 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
144 {
145 int i, max_rate;
146
147 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
148
149 for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
150 if (default_rates[i] > max_rate)
151 break;
152 intel_dp->sink_rates[i] = default_rates[i];
153 }
154
155 intel_dp->num_sink_rates = i;
156 }
157
158 /* Theoretical max between source and sink */
159 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
160 {
161 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
162 }
163
164 /* Theoretical max between source and sink */
165 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
166 {
167 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
168 int source_max = intel_dig_port->max_lanes;
169 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
170
171 return min(source_max, sink_max);
172 }
173
174 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
175 {
176 return intel_dp->max_link_lane_count;
177 }
178
179 int
180 intel_dp_link_required(int pixel_clock, int bpp)
181 {
182 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
183 return DIV_ROUND_UP(pixel_clock * bpp, 8);
184 }
185
186 int
187 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188 {
189 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
190 * link rate that is generally expressed in Gbps. Since, 8 bits of data
191 * is transmitted every LS_Clk per lane, there is no need to account for
192 * the channel encoding that is done in the PHY layer here.
193 */
194
195 return max_link_clock * max_lanes;
196 }
197
198 static int
199 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
200 {
201 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
202 struct intel_encoder *encoder = &intel_dig_port->base;
203 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
204 int max_dotclk = dev_priv->max_dotclk_freq;
205 int ds_max_dotclk;
206
207 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
208
209 if (type != DP_DS_PORT_TYPE_VGA)
210 return max_dotclk;
211
212 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
213 intel_dp->downstream_ports);
214
215 if (ds_max_dotclk != 0)
216 max_dotclk = min(max_dotclk, ds_max_dotclk);
217
218 return max_dotclk;
219 }
220
221 static void
222 intel_dp_set_source_rates(struct intel_dp *intel_dp)
223 {
224 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
225 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
226 enum port port = dig_port->base.port;
227 const int *source_rates;
228 int size;
229 u32 voltage;
230
231 /* This should only be done once */
232 WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
233
234 if (IS_GEN9_LP(dev_priv)) {
235 source_rates = bxt_rates;
236 size = ARRAY_SIZE(bxt_rates);
237 } else if (IS_CANNONLAKE(dev_priv)) {
238 source_rates = cnl_rates;
239 size = ARRAY_SIZE(cnl_rates);
240 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
241 if (port == PORT_A || port == PORT_D ||
242 voltage == VOLTAGE_INFO_0_85V)
243 size -= 2;
244 } else if (IS_GEN9_BC(dev_priv)) {
245 source_rates = skl_rates;
246 size = ARRAY_SIZE(skl_rates);
247 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
248 IS_BROADWELL(dev_priv)) {
249 source_rates = default_rates;
250 size = ARRAY_SIZE(default_rates);
251 } else {
252 source_rates = default_rates;
253 size = ARRAY_SIZE(default_rates) - 1;
254 }
255
256 intel_dp->source_rates = source_rates;
257 intel_dp->num_source_rates = size;
258 }
259
260 static int intersect_rates(const int *source_rates, int source_len,
261 const int *sink_rates, int sink_len,
262 int *common_rates)
263 {
264 int i = 0, j = 0, k = 0;
265
266 while (i < source_len && j < sink_len) {
267 if (source_rates[i] == sink_rates[j]) {
268 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
269 return k;
270 common_rates[k] = source_rates[i];
271 ++k;
272 ++i;
273 ++j;
274 } else if (source_rates[i] < sink_rates[j]) {
275 ++i;
276 } else {
277 ++j;
278 }
279 }
280 return k;
281 }
282
283 /* return index of rate in rates array, or -1 if not found */
284 static int intel_dp_rate_index(const int *rates, int len, int rate)
285 {
286 int i;
287
288 for (i = 0; i < len; i++)
289 if (rate == rates[i])
290 return i;
291
292 return -1;
293 }
294
295 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
296 {
297 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
298
299 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
300 intel_dp->num_source_rates,
301 intel_dp->sink_rates,
302 intel_dp->num_sink_rates,
303 intel_dp->common_rates);
304
305 /* Paranoia, there should always be something in common. */
306 if (WARN_ON(intel_dp->num_common_rates == 0)) {
307 intel_dp->common_rates[0] = default_rates[0];
308 intel_dp->num_common_rates = 1;
309 }
310 }
311
312 /* get length of common rates potentially limited by max_rate */
313 static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
314 int max_rate)
315 {
316 const int *common_rates = intel_dp->common_rates;
317 int i, common_len = intel_dp->num_common_rates;
318
319 /* Limit results by potentially reduced max rate */
320 for (i = 0; i < common_len; i++) {
321 if (common_rates[common_len - i - 1] <= max_rate)
322 return common_len - i;
323 }
324
325 return 0;
326 }
327
328 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
329 uint8_t lane_count)
330 {
331 /*
332 * FIXME: we need to synchronize the current link parameters with
333 * hardware readout. Currently fast link training doesn't work on
334 * boot-up.
335 */
336 if (link_rate == 0 ||
337 link_rate > intel_dp->max_link_rate)
338 return false;
339
340 if (lane_count == 0 ||
341 lane_count > intel_dp_max_lane_count(intel_dp))
342 return false;
343
344 return true;
345 }
346
347 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
348 int link_rate, uint8_t lane_count)
349 {
350 int index;
351
352 index = intel_dp_rate_index(intel_dp->common_rates,
353 intel_dp->num_common_rates,
354 link_rate);
355 if (index > 0) {
356 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
357 intel_dp->max_link_lane_count = lane_count;
358 } else if (lane_count > 1) {
359 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
360 intel_dp->max_link_lane_count = lane_count >> 1;
361 } else {
362 DRM_ERROR("Link Training Unsuccessful\n");
363 return -1;
364 }
365
366 return 0;
367 }
368
369 static enum drm_mode_status
370 intel_dp_mode_valid(struct drm_connector *connector,
371 struct drm_display_mode *mode)
372 {
373 struct intel_dp *intel_dp = intel_attached_dp(connector);
374 struct intel_connector *intel_connector = to_intel_connector(connector);
375 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
376 int target_clock = mode->clock;
377 int max_rate, mode_rate, max_lanes, max_link_clock;
378 int max_dotclk;
379
380 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
381
382 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
383 if (mode->hdisplay > fixed_mode->hdisplay)
384 return MODE_PANEL;
385
386 if (mode->vdisplay > fixed_mode->vdisplay)
387 return MODE_PANEL;
388
389 target_clock = fixed_mode->clock;
390 }
391
392 max_link_clock = intel_dp_max_link_rate(intel_dp);
393 max_lanes = intel_dp_max_lane_count(intel_dp);
394
395 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
396 mode_rate = intel_dp_link_required(target_clock, 18);
397
398 if (mode_rate > max_rate || target_clock > max_dotclk)
399 return MODE_CLOCK_HIGH;
400
401 if (mode->clock < 10000)
402 return MODE_CLOCK_LOW;
403
404 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
405 return MODE_H_ILLEGAL;
406
407 return MODE_OK;
408 }
409
410 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
411 {
412 int i;
413 uint32_t v = 0;
414
415 if (src_bytes > 4)
416 src_bytes = 4;
417 for (i = 0; i < src_bytes; i++)
418 v |= ((uint32_t) src[i]) << ((3-i) * 8);
419 return v;
420 }
421
422 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
423 {
424 int i;
425 if (dst_bytes > 4)
426 dst_bytes = 4;
427 for (i = 0; i < dst_bytes; i++)
428 dst[i] = src >> ((3-i) * 8);
429 }
430
431 static void
432 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
433 static void
434 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
435 bool force_disable_vdd);
436 static void
437 intel_dp_pps_init(struct intel_dp *intel_dp);
438
439 static void pps_lock(struct intel_dp *intel_dp)
440 {
441 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
442
443 /*
444 * See intel_power_sequencer_reset() why we need
445 * a power domain reference here.
446 */
447 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
448
449 mutex_lock(&dev_priv->pps_mutex);
450 }
451
452 static void pps_unlock(struct intel_dp *intel_dp)
453 {
454 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
455
456 mutex_unlock(&dev_priv->pps_mutex);
457
458 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
459 }
460
461 static void
462 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
463 {
464 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
465 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
466 enum pipe pipe = intel_dp->pps_pipe;
467 bool pll_enabled, release_cl_override = false;
468 enum dpio_phy phy = DPIO_PHY(pipe);
469 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
470 uint32_t DP;
471
472 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
473 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
474 pipe_name(pipe), port_name(intel_dig_port->base.port)))
475 return;
476
477 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
478 pipe_name(pipe), port_name(intel_dig_port->base.port));
479
480 /* Preserve the BIOS-computed detected bit. This is
481 * supposed to be read-only.
482 */
483 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
484 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
485 DP |= DP_PORT_WIDTH(1);
486 DP |= DP_LINK_TRAIN_PAT_1;
487
488 if (IS_CHERRYVIEW(dev_priv))
489 DP |= DP_PIPE_SELECT_CHV(pipe);
490 else if (pipe == PIPE_B)
491 DP |= DP_PIPEB_SELECT;
492
493 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
494
495 /*
496 * The DPLL for the pipe must be enabled for this to work.
497 * So enable temporarily it if it's not already enabled.
498 */
499 if (!pll_enabled) {
500 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
501 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
502
503 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
504 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
505 DRM_ERROR("Failed to force on pll for pipe %c!\n",
506 pipe_name(pipe));
507 return;
508 }
509 }
510
511 /*
512 * Similar magic as in intel_dp_enable_port().
513 * We _must_ do this port enable + disable trick
514 * to make this power seqeuencer lock onto the port.
515 * Otherwise even VDD force bit won't work.
516 */
517 I915_WRITE(intel_dp->output_reg, DP);
518 POSTING_READ(intel_dp->output_reg);
519
520 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
521 POSTING_READ(intel_dp->output_reg);
522
523 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
524 POSTING_READ(intel_dp->output_reg);
525
526 if (!pll_enabled) {
527 vlv_force_pll_off(dev_priv, pipe);
528
529 if (release_cl_override)
530 chv_phy_powergate_ch(dev_priv, phy, ch, false);
531 }
532 }
533
534 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
535 {
536 struct intel_encoder *encoder;
537 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
538
539 /*
540 * We don't have power sequencer currently.
541 * Pick one that's not used by other ports.
542 */
543 for_each_intel_encoder(&dev_priv->drm, encoder) {
544 struct intel_dp *intel_dp;
545
546 if (encoder->type != INTEL_OUTPUT_DP &&
547 encoder->type != INTEL_OUTPUT_EDP)
548 continue;
549
550 intel_dp = enc_to_intel_dp(&encoder->base);
551
552 if (encoder->type == INTEL_OUTPUT_EDP) {
553 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
554 intel_dp->active_pipe != intel_dp->pps_pipe);
555
556 if (intel_dp->pps_pipe != INVALID_PIPE)
557 pipes &= ~(1 << intel_dp->pps_pipe);
558 } else {
559 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
560
561 if (intel_dp->active_pipe != INVALID_PIPE)
562 pipes &= ~(1 << intel_dp->active_pipe);
563 }
564 }
565
566 if (pipes == 0)
567 return INVALID_PIPE;
568
569 return ffs(pipes) - 1;
570 }
571
572 static enum pipe
573 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
574 {
575 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
576 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
577 enum pipe pipe;
578
579 lockdep_assert_held(&dev_priv->pps_mutex);
580
581 /* We should never land here with regular DP ports */
582 WARN_ON(!intel_dp_is_edp(intel_dp));
583
584 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
585 intel_dp->active_pipe != intel_dp->pps_pipe);
586
587 if (intel_dp->pps_pipe != INVALID_PIPE)
588 return intel_dp->pps_pipe;
589
590 pipe = vlv_find_free_pps(dev_priv);
591
592 /*
593 * Didn't find one. This should not happen since there
594 * are two power sequencers and up to two eDP ports.
595 */
596 if (WARN_ON(pipe == INVALID_PIPE))
597 pipe = PIPE_A;
598
599 vlv_steal_power_sequencer(dev_priv, pipe);
600 intel_dp->pps_pipe = pipe;
601
602 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
603 pipe_name(intel_dp->pps_pipe),
604 port_name(intel_dig_port->base.port));
605
606 /* init power sequencer on this pipe and port */
607 intel_dp_init_panel_power_sequencer(intel_dp);
608 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
609
610 /*
611 * Even vdd force doesn't work until we've made
612 * the power sequencer lock in on the port.
613 */
614 vlv_power_sequencer_kick(intel_dp);
615
616 return intel_dp->pps_pipe;
617 }
618
619 static int
620 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
621 {
622 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
623
624 lockdep_assert_held(&dev_priv->pps_mutex);
625
626 /* We should never land here with regular DP ports */
627 WARN_ON(!intel_dp_is_edp(intel_dp));
628
629 /*
630 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
631 * mapping needs to be retrieved from VBT, for now just hard-code to
632 * use instance #0 always.
633 */
634 if (!intel_dp->pps_reset)
635 return 0;
636
637 intel_dp->pps_reset = false;
638
639 /*
640 * Only the HW needs to be reprogrammed, the SW state is fixed and
641 * has been setup during connector init.
642 */
643 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
644
645 return 0;
646 }
647
648 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
649 enum pipe pipe);
650
651 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
652 enum pipe pipe)
653 {
654 return I915_READ(PP_STATUS(pipe)) & PP_ON;
655 }
656
657 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
658 enum pipe pipe)
659 {
660 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
661 }
662
663 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
664 enum pipe pipe)
665 {
666 return true;
667 }
668
669 static enum pipe
670 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
671 enum port port,
672 vlv_pipe_check pipe_check)
673 {
674 enum pipe pipe;
675
676 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
677 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
678 PANEL_PORT_SELECT_MASK;
679
680 if (port_sel != PANEL_PORT_SELECT_VLV(port))
681 continue;
682
683 if (!pipe_check(dev_priv, pipe))
684 continue;
685
686 return pipe;
687 }
688
689 return INVALID_PIPE;
690 }
691
692 static void
693 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
694 {
695 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
696 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
697 enum port port = intel_dig_port->base.port;
698
699 lockdep_assert_held(&dev_priv->pps_mutex);
700
701 /* try to find a pipe with this port selected */
702 /* first pick one where the panel is on */
703 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
704 vlv_pipe_has_pp_on);
705 /* didn't find one? pick one where vdd is on */
706 if (intel_dp->pps_pipe == INVALID_PIPE)
707 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
708 vlv_pipe_has_vdd_on);
709 /* didn't find one? pick one with just the correct port */
710 if (intel_dp->pps_pipe == INVALID_PIPE)
711 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
712 vlv_pipe_any);
713
714 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
715 if (intel_dp->pps_pipe == INVALID_PIPE) {
716 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
717 port_name(port));
718 return;
719 }
720
721 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
722 port_name(port), pipe_name(intel_dp->pps_pipe));
723
724 intel_dp_init_panel_power_sequencer(intel_dp);
725 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
726 }
727
728 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
729 {
730 struct intel_encoder *encoder;
731
732 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
733 !IS_GEN9_LP(dev_priv)))
734 return;
735
736 /*
737 * We can't grab pps_mutex here due to deadlock with power_domain
738 * mutex when power_domain functions are called while holding pps_mutex.
739 * That also means that in order to use pps_pipe the code needs to
740 * hold both a power domain reference and pps_mutex, and the power domain
741 * reference get/put must be done while _not_ holding pps_mutex.
742 * pps_{lock,unlock}() do these steps in the correct order, so one
743 * should use them always.
744 */
745
746 for_each_intel_encoder(&dev_priv->drm, encoder) {
747 struct intel_dp *intel_dp;
748
749 if (encoder->type != INTEL_OUTPUT_DP &&
750 encoder->type != INTEL_OUTPUT_EDP &&
751 encoder->type != INTEL_OUTPUT_DDI)
752 continue;
753
754 intel_dp = enc_to_intel_dp(&encoder->base);
755
756 /* Skip pure DVI/HDMI DDI encoders */
757 if (!i915_mmio_reg_valid(intel_dp->output_reg))
758 continue;
759
760 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
761
762 if (encoder->type != INTEL_OUTPUT_EDP)
763 continue;
764
765 if (IS_GEN9_LP(dev_priv))
766 intel_dp->pps_reset = true;
767 else
768 intel_dp->pps_pipe = INVALID_PIPE;
769 }
770 }
771
772 struct pps_registers {
773 i915_reg_t pp_ctrl;
774 i915_reg_t pp_stat;
775 i915_reg_t pp_on;
776 i915_reg_t pp_off;
777 i915_reg_t pp_div;
778 };
779
780 static void intel_pps_get_registers(struct intel_dp *intel_dp,
781 struct pps_registers *regs)
782 {
783 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
784 int pps_idx = 0;
785
786 memset(regs, 0, sizeof(*regs));
787
788 if (IS_GEN9_LP(dev_priv))
789 pps_idx = bxt_power_sequencer_idx(intel_dp);
790 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
791 pps_idx = vlv_power_sequencer_pipe(intel_dp);
792
793 regs->pp_ctrl = PP_CONTROL(pps_idx);
794 regs->pp_stat = PP_STATUS(pps_idx);
795 regs->pp_on = PP_ON_DELAYS(pps_idx);
796 regs->pp_off = PP_OFF_DELAYS(pps_idx);
797 if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
798 regs->pp_div = PP_DIVISOR(pps_idx);
799 }
800
801 static i915_reg_t
802 _pp_ctrl_reg(struct intel_dp *intel_dp)
803 {
804 struct pps_registers regs;
805
806 intel_pps_get_registers(intel_dp, &regs);
807
808 return regs.pp_ctrl;
809 }
810
811 static i915_reg_t
812 _pp_stat_reg(struct intel_dp *intel_dp)
813 {
814 struct pps_registers regs;
815
816 intel_pps_get_registers(intel_dp, &regs);
817
818 return regs.pp_stat;
819 }
820
821 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
822 This function only applicable when panel PM state is not to be tracked */
823 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
824 void *unused)
825 {
826 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
827 edp_notifier);
828 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
829
830 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
831 return 0;
832
833 pps_lock(intel_dp);
834
835 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
836 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
837 i915_reg_t pp_ctrl_reg, pp_div_reg;
838 u32 pp_div;
839
840 pp_ctrl_reg = PP_CONTROL(pipe);
841 pp_div_reg = PP_DIVISOR(pipe);
842 pp_div = I915_READ(pp_div_reg);
843 pp_div &= PP_REFERENCE_DIVIDER_MASK;
844
845 /* 0x1F write to PP_DIV_REG sets max cycle delay */
846 I915_WRITE(pp_div_reg, pp_div | 0x1F);
847 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
848 msleep(intel_dp->panel_power_cycle_delay);
849 }
850
851 pps_unlock(intel_dp);
852
853 return 0;
854 }
855
856 static bool edp_have_panel_power(struct intel_dp *intel_dp)
857 {
858 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
859
860 lockdep_assert_held(&dev_priv->pps_mutex);
861
862 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
863 intel_dp->pps_pipe == INVALID_PIPE)
864 return false;
865
866 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
867 }
868
869 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
870 {
871 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
872
873 lockdep_assert_held(&dev_priv->pps_mutex);
874
875 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
876 intel_dp->pps_pipe == INVALID_PIPE)
877 return false;
878
879 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
880 }
881
882 static void
883 intel_dp_check_edp(struct intel_dp *intel_dp)
884 {
885 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
886
887 if (!intel_dp_is_edp(intel_dp))
888 return;
889
890 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
891 WARN(1, "eDP powered off while attempting aux channel communication.\n");
892 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
893 I915_READ(_pp_stat_reg(intel_dp)),
894 I915_READ(_pp_ctrl_reg(intel_dp)));
895 }
896 }
897
898 static uint32_t
899 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
900 {
901 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
902 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
903 uint32_t status;
904 bool done;
905
906 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
907 if (has_aux_irq)
908 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
909 msecs_to_jiffies_timeout(10));
910 else
911 done = wait_for(C, 10) == 0;
912 if (!done)
913 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
914 has_aux_irq);
915 #undef C
916
917 return status;
918 }
919
920 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
921 {
922 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
923 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
924
925 if (index)
926 return 0;
927
928 /*
929 * The clock divider is based off the hrawclk, and would like to run at
930 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
931 */
932 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
933 }
934
935 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
936 {
937 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
938 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
939
940 if (index)
941 return 0;
942
943 /*
944 * The clock divider is based off the cdclk or PCH rawclk, and would
945 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
946 * divide by 2000 and use that
947 */
948 if (intel_dig_port->base.port == PORT_A)
949 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
950 else
951 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
952 }
953
954 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
955 {
956 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
957 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
958
959 if (intel_dig_port->base.port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
960 /* Workaround for non-ULT HSW */
961 switch (index) {
962 case 0: return 63;
963 case 1: return 72;
964 default: return 0;
965 }
966 }
967
968 return ilk_get_aux_clock_divider(intel_dp, index);
969 }
970
971 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
972 {
973 /*
974 * SKL doesn't need us to program the AUX clock divider (Hardware will
975 * derive the clock from CDCLK automatically). We still implement the
976 * get_aux_clock_divider vfunc to plug-in into the existing code.
977 */
978 return index ? 0 : 1;
979 }
980
981 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
982 bool has_aux_irq,
983 int send_bytes,
984 uint32_t aux_clock_divider)
985 {
986 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
987 struct drm_i915_private *dev_priv =
988 to_i915(intel_dig_port->base.base.dev);
989 uint32_t precharge, timeout;
990
991 if (IS_GEN6(dev_priv))
992 precharge = 3;
993 else
994 precharge = 5;
995
996 if (IS_BROADWELL(dev_priv))
997 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
998 else
999 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1000
1001 return DP_AUX_CH_CTL_SEND_BUSY |
1002 DP_AUX_CH_CTL_DONE |
1003 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1004 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1005 timeout |
1006 DP_AUX_CH_CTL_RECEIVE_ERROR |
1007 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1008 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1009 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1010 }
1011
1012 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1013 bool has_aux_irq,
1014 int send_bytes,
1015 uint32_t unused)
1016 {
1017 return DP_AUX_CH_CTL_SEND_BUSY |
1018 DP_AUX_CH_CTL_DONE |
1019 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1020 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1021 DP_AUX_CH_CTL_TIME_OUT_MAX |
1022 DP_AUX_CH_CTL_RECEIVE_ERROR |
1023 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1024 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1025 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1026 }
1027
1028 static int
1029 intel_dp_aux_ch(struct intel_dp *intel_dp,
1030 const uint8_t *send, int send_bytes,
1031 uint8_t *recv, int recv_size)
1032 {
1033 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1034 struct drm_i915_private *dev_priv =
1035 to_i915(intel_dig_port->base.base.dev);
1036 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1037 uint32_t aux_clock_divider;
1038 int i, ret, recv_bytes;
1039 uint32_t status;
1040 int try, clock = 0;
1041 bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1042 bool vdd;
1043
1044 pps_lock(intel_dp);
1045
1046 /*
1047 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1048 * In such cases we want to leave VDD enabled and it's up to upper layers
1049 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1050 * ourselves.
1051 */
1052 vdd = edp_panel_vdd_on(intel_dp);
1053
1054 /* dp aux is extremely sensitive to irq latency, hence request the
1055 * lowest possible wakeup latency and so prevent the cpu from going into
1056 * deep sleep states.
1057 */
1058 pm_qos_update_request(&dev_priv->pm_qos, 0);
1059
1060 intel_dp_check_edp(intel_dp);
1061
1062 /* Try to wait for any previous AUX channel activity */
1063 for (try = 0; try < 3; try++) {
1064 status = I915_READ_NOTRACE(ch_ctl);
1065 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1066 break;
1067 msleep(1);
1068 }
1069
1070 if (try == 3) {
1071 static u32 last_status = -1;
1072 const u32 status = I915_READ(ch_ctl);
1073
1074 if (status != last_status) {
1075 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1076 status);
1077 last_status = status;
1078 }
1079
1080 ret = -EBUSY;
1081 goto out;
1082 }
1083
1084 /* Only 5 data registers! */
1085 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1086 ret = -E2BIG;
1087 goto out;
1088 }
1089
1090 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1091 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1092 has_aux_irq,
1093 send_bytes,
1094 aux_clock_divider);
1095
1096 /* Must try at least 3 times according to DP spec */
1097 for (try = 0; try < 5; try++) {
1098 /* Load the send data into the aux channel data registers */
1099 for (i = 0; i < send_bytes; i += 4)
1100 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1101 intel_dp_pack_aux(send + i,
1102 send_bytes - i));
1103
1104 /* Send the command and wait for it to complete */
1105 I915_WRITE(ch_ctl, send_ctl);
1106
1107 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1108
1109 /* Clear done status and any errors */
1110 I915_WRITE(ch_ctl,
1111 status |
1112 DP_AUX_CH_CTL_DONE |
1113 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1114 DP_AUX_CH_CTL_RECEIVE_ERROR);
1115
1116 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1117 continue;
1118
1119 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1120 * 400us delay required for errors and timeouts
1121 * Timeout errors from the HW already meet this
1122 * requirement so skip to next iteration
1123 */
1124 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1125 usleep_range(400, 500);
1126 continue;
1127 }
1128 if (status & DP_AUX_CH_CTL_DONE)
1129 goto done;
1130 }
1131 }
1132
1133 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1134 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1135 ret = -EBUSY;
1136 goto out;
1137 }
1138
1139 done:
1140 /* Check for timeout or receive error.
1141 * Timeouts occur when the sink is not connected
1142 */
1143 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1144 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1145 ret = -EIO;
1146 goto out;
1147 }
1148
1149 /* Timeouts occur when the device isn't connected, so they're
1150 * "normal" -- don't fill the kernel log with these */
1151 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1152 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1153 ret = -ETIMEDOUT;
1154 goto out;
1155 }
1156
1157 /* Unload any bytes sent back from the other side */
1158 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1159 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1160
1161 /*
1162 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1163 * We have no idea of what happened so we return -EBUSY so
1164 * drm layer takes care for the necessary retries.
1165 */
1166 if (recv_bytes == 0 || recv_bytes > 20) {
1167 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1168 recv_bytes);
1169 /*
1170 * FIXME: This patch was created on top of a series that
1171 * organize the retries at drm level. There EBUSY should
1172 * also take care for 1ms wait before retrying.
1173 * That aux retries re-org is still needed and after that is
1174 * merged we remove this sleep from here.
1175 */
1176 usleep_range(1000, 1500);
1177 ret = -EBUSY;
1178 goto out;
1179 }
1180
1181 if (recv_bytes > recv_size)
1182 recv_bytes = recv_size;
1183
1184 for (i = 0; i < recv_bytes; i += 4)
1185 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1186 recv + i, recv_bytes - i);
1187
1188 ret = recv_bytes;
1189 out:
1190 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1191
1192 if (vdd)
1193 edp_panel_vdd_off(intel_dp, false);
1194
1195 pps_unlock(intel_dp);
1196
1197 return ret;
1198 }
1199
1200 #define BARE_ADDRESS_SIZE 3
1201 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1202 static ssize_t
1203 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1204 {
1205 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1206 uint8_t txbuf[20], rxbuf[20];
1207 size_t txsize, rxsize;
1208 int ret;
1209
1210 txbuf[0] = (msg->request << 4) |
1211 ((msg->address >> 16) & 0xf);
1212 txbuf[1] = (msg->address >> 8) & 0xff;
1213 txbuf[2] = msg->address & 0xff;
1214 txbuf[3] = msg->size - 1;
1215
1216 switch (msg->request & ~DP_AUX_I2C_MOT) {
1217 case DP_AUX_NATIVE_WRITE:
1218 case DP_AUX_I2C_WRITE:
1219 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1220 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1221 rxsize = 2; /* 0 or 1 data bytes */
1222
1223 if (WARN_ON(txsize > 20))
1224 return -E2BIG;
1225
1226 WARN_ON(!msg->buffer != !msg->size);
1227
1228 if (msg->buffer)
1229 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1230
1231 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1232 if (ret > 0) {
1233 msg->reply = rxbuf[0] >> 4;
1234
1235 if (ret > 1) {
1236 /* Number of bytes written in a short write. */
1237 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1238 } else {
1239 /* Return payload size. */
1240 ret = msg->size;
1241 }
1242 }
1243 break;
1244
1245 case DP_AUX_NATIVE_READ:
1246 case DP_AUX_I2C_READ:
1247 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1248 rxsize = msg->size + 1;
1249
1250 if (WARN_ON(rxsize > 20))
1251 return -E2BIG;
1252
1253 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1254 if (ret > 0) {
1255 msg->reply = rxbuf[0] >> 4;
1256 /*
1257 * Assume happy day, and copy the data. The caller is
1258 * expected to check msg->reply before touching it.
1259 *
1260 * Return payload size.
1261 */
1262 ret--;
1263 memcpy(msg->buffer, rxbuf + 1, ret);
1264 }
1265 break;
1266
1267 default:
1268 ret = -EINVAL;
1269 break;
1270 }
1271
1272 return ret;
1273 }
1274
1275 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1276 enum port port)
1277 {
1278 const struct ddi_vbt_port_info *info =
1279 &dev_priv->vbt.ddi_port_info[port];
1280 enum port aux_port;
1281
1282 if (!info->alternate_aux_channel) {
1283 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1284 port_name(port), port_name(port));
1285 return port;
1286 }
1287
1288 switch (info->alternate_aux_channel) {
1289 case DP_AUX_A:
1290 aux_port = PORT_A;
1291 break;
1292 case DP_AUX_B:
1293 aux_port = PORT_B;
1294 break;
1295 case DP_AUX_C:
1296 aux_port = PORT_C;
1297 break;
1298 case DP_AUX_D:
1299 aux_port = PORT_D;
1300 break;
1301 default:
1302 MISSING_CASE(info->alternate_aux_channel);
1303 aux_port = PORT_A;
1304 break;
1305 }
1306
1307 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1308 port_name(aux_port), port_name(port));
1309
1310 return aux_port;
1311 }
1312
1313 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1314 enum port port)
1315 {
1316 switch (port) {
1317 case PORT_B:
1318 case PORT_C:
1319 case PORT_D:
1320 return DP_AUX_CH_CTL(port);
1321 default:
1322 MISSING_CASE(port);
1323 return DP_AUX_CH_CTL(PORT_B);
1324 }
1325 }
1326
1327 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1328 enum port port, int index)
1329 {
1330 switch (port) {
1331 case PORT_B:
1332 case PORT_C:
1333 case PORT_D:
1334 return DP_AUX_CH_DATA(port, index);
1335 default:
1336 MISSING_CASE(port);
1337 return DP_AUX_CH_DATA(PORT_B, index);
1338 }
1339 }
1340
1341 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1342 enum port port)
1343 {
1344 switch (port) {
1345 case PORT_A:
1346 return DP_AUX_CH_CTL(port);
1347 case PORT_B:
1348 case PORT_C:
1349 case PORT_D:
1350 return PCH_DP_AUX_CH_CTL(port);
1351 default:
1352 MISSING_CASE(port);
1353 return DP_AUX_CH_CTL(PORT_A);
1354 }
1355 }
1356
1357 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1358 enum port port, int index)
1359 {
1360 switch (port) {
1361 case PORT_A:
1362 return DP_AUX_CH_DATA(port, index);
1363 case PORT_B:
1364 case PORT_C:
1365 case PORT_D:
1366 return PCH_DP_AUX_CH_DATA(port, index);
1367 default:
1368 MISSING_CASE(port);
1369 return DP_AUX_CH_DATA(PORT_A, index);
1370 }
1371 }
1372
1373 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1374 enum port port)
1375 {
1376 switch (port) {
1377 case PORT_A:
1378 case PORT_B:
1379 case PORT_C:
1380 case PORT_D:
1381 return DP_AUX_CH_CTL(port);
1382 default:
1383 MISSING_CASE(port);
1384 return DP_AUX_CH_CTL(PORT_A);
1385 }
1386 }
1387
1388 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1389 enum port port, int index)
1390 {
1391 switch (port) {
1392 case PORT_A:
1393 case PORT_B:
1394 case PORT_C:
1395 case PORT_D:
1396 return DP_AUX_CH_DATA(port, index);
1397 default:
1398 MISSING_CASE(port);
1399 return DP_AUX_CH_DATA(PORT_A, index);
1400 }
1401 }
1402
1403 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1404 enum port port)
1405 {
1406 if (INTEL_INFO(dev_priv)->gen >= 9)
1407 return skl_aux_ctl_reg(dev_priv, port);
1408 else if (HAS_PCH_SPLIT(dev_priv))
1409 return ilk_aux_ctl_reg(dev_priv, port);
1410 else
1411 return g4x_aux_ctl_reg(dev_priv, port);
1412 }
1413
1414 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1415 enum port port, int index)
1416 {
1417 if (INTEL_INFO(dev_priv)->gen >= 9)
1418 return skl_aux_data_reg(dev_priv, port, index);
1419 else if (HAS_PCH_SPLIT(dev_priv))
1420 return ilk_aux_data_reg(dev_priv, port, index);
1421 else
1422 return g4x_aux_data_reg(dev_priv, port, index);
1423 }
1424
1425 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1426 {
1427 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1428 enum port port = intel_aux_port(dev_priv,
1429 dp_to_dig_port(intel_dp)->base.port);
1430 int i;
1431
1432 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1433 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1434 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1435 }
1436
1437 static void
1438 intel_dp_aux_fini(struct intel_dp *intel_dp)
1439 {
1440 kfree(intel_dp->aux.name);
1441 }
1442
1443 static void
1444 intel_dp_aux_init(struct intel_dp *intel_dp)
1445 {
1446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1447 enum port port = intel_dig_port->base.port;
1448
1449 intel_aux_reg_init(intel_dp);
1450 drm_dp_aux_init(&intel_dp->aux);
1451
1452 /* Failure to allocate our preferred name is not critical */
1453 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1454 intel_dp->aux.transfer = intel_dp_aux_transfer;
1455 }
1456
1457 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1458 {
1459 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1460
1461 return max_rate >= 540000;
1462 }
1463
1464 static void
1465 intel_dp_set_clock(struct intel_encoder *encoder,
1466 struct intel_crtc_state *pipe_config)
1467 {
1468 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1469 const struct dp_link_dpll *divisor = NULL;
1470 int i, count = 0;
1471
1472 if (IS_G4X(dev_priv)) {
1473 divisor = gen4_dpll;
1474 count = ARRAY_SIZE(gen4_dpll);
1475 } else if (HAS_PCH_SPLIT(dev_priv)) {
1476 divisor = pch_dpll;
1477 count = ARRAY_SIZE(pch_dpll);
1478 } else if (IS_CHERRYVIEW(dev_priv)) {
1479 divisor = chv_dpll;
1480 count = ARRAY_SIZE(chv_dpll);
1481 } else if (IS_VALLEYVIEW(dev_priv)) {
1482 divisor = vlv_dpll;
1483 count = ARRAY_SIZE(vlv_dpll);
1484 }
1485
1486 if (divisor && count) {
1487 for (i = 0; i < count; i++) {
1488 if (pipe_config->port_clock == divisor[i].clock) {
1489 pipe_config->dpll = divisor[i].dpll;
1490 pipe_config->clock_set = true;
1491 break;
1492 }
1493 }
1494 }
1495 }
1496
1497 static void snprintf_int_array(char *str, size_t len,
1498 const int *array, int nelem)
1499 {
1500 int i;
1501
1502 str[0] = '\0';
1503
1504 for (i = 0; i < nelem; i++) {
1505 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1506 if (r >= len)
1507 return;
1508 str += r;
1509 len -= r;
1510 }
1511 }
1512
1513 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1514 {
1515 char str[128]; /* FIXME: too big for stack? */
1516
1517 if ((drm_debug & DRM_UT_KMS) == 0)
1518 return;
1519
1520 snprintf_int_array(str, sizeof(str),
1521 intel_dp->source_rates, intel_dp->num_source_rates);
1522 DRM_DEBUG_KMS("source rates: %s\n", str);
1523
1524 snprintf_int_array(str, sizeof(str),
1525 intel_dp->sink_rates, intel_dp->num_sink_rates);
1526 DRM_DEBUG_KMS("sink rates: %s\n", str);
1527
1528 snprintf_int_array(str, sizeof(str),
1529 intel_dp->common_rates, intel_dp->num_common_rates);
1530 DRM_DEBUG_KMS("common rates: %s\n", str);
1531 }
1532
1533 int
1534 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1535 {
1536 int len;
1537
1538 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1539 if (WARN_ON(len <= 0))
1540 return 162000;
1541
1542 return intel_dp->common_rates[len - 1];
1543 }
1544
1545 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1546 {
1547 int i = intel_dp_rate_index(intel_dp->sink_rates,
1548 intel_dp->num_sink_rates, rate);
1549
1550 if (WARN_ON(i < 0))
1551 i = 0;
1552
1553 return i;
1554 }
1555
1556 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1557 uint8_t *link_bw, uint8_t *rate_select)
1558 {
1559 /* eDP 1.4 rate select method. */
1560 if (intel_dp->use_rate_select) {
1561 *link_bw = 0;
1562 *rate_select =
1563 intel_dp_rate_select(intel_dp, port_clock);
1564 } else {
1565 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1566 *rate_select = 0;
1567 }
1568 }
1569
1570 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1571 struct intel_crtc_state *pipe_config)
1572 {
1573 int bpp, bpc;
1574
1575 bpp = pipe_config->pipe_bpp;
1576 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1577
1578 if (bpc > 0)
1579 bpp = min(bpp, 3*bpc);
1580
1581 /* For DP Compliance we override the computed bpp for the pipe */
1582 if (intel_dp->compliance.test_data.bpc != 0) {
1583 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1584 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1585 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1586 pipe_config->pipe_bpp);
1587 }
1588 return bpp;
1589 }
1590
1591 static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
1592 struct drm_display_mode *m2)
1593 {
1594 bool bres = false;
1595
1596 if (m1 && m2)
1597 bres = (m1->hdisplay == m2->hdisplay &&
1598 m1->hsync_start == m2->hsync_start &&
1599 m1->hsync_end == m2->hsync_end &&
1600 m1->htotal == m2->htotal &&
1601 m1->vdisplay == m2->vdisplay &&
1602 m1->vsync_start == m2->vsync_start &&
1603 m1->vsync_end == m2->vsync_end &&
1604 m1->vtotal == m2->vtotal);
1605 return bres;
1606 }
1607
1608 bool
1609 intel_dp_compute_config(struct intel_encoder *encoder,
1610 struct intel_crtc_state *pipe_config,
1611 struct drm_connector_state *conn_state)
1612 {
1613 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1614 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1615 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1616 enum port port = encoder->port;
1617 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1618 struct intel_connector *intel_connector = intel_dp->attached_connector;
1619 struct intel_digital_connector_state *intel_conn_state =
1620 to_intel_digital_connector_state(conn_state);
1621 int lane_count, clock;
1622 int min_lane_count = 1;
1623 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1624 /* Conveniently, the link BW constants become indices with a shift...*/
1625 int min_clock = 0;
1626 int max_clock;
1627 int bpp, mode_rate;
1628 int link_avail, link_clock;
1629 int common_len;
1630 uint8_t link_bw, rate_select;
1631 bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1632 DP_DPCD_QUIRK_LIMITED_M_N);
1633
1634 common_len = intel_dp_common_len_rate_limit(intel_dp,
1635 intel_dp->max_link_rate);
1636
1637 /* No common link rates between source and sink */
1638 WARN_ON(common_len <= 0);
1639
1640 max_clock = common_len - 1;
1641
1642 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1643 pipe_config->has_pch_encoder = true;
1644
1645 pipe_config->has_drrs = false;
1646 if (IS_G4X(dev_priv) || port == PORT_A)
1647 pipe_config->has_audio = false;
1648 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1649 pipe_config->has_audio = intel_dp->has_audio;
1650 else
1651 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1652
1653 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1654 struct drm_display_mode *panel_mode =
1655 intel_connector->panel.alt_fixed_mode;
1656 struct drm_display_mode *req_mode = &pipe_config->base.mode;
1657
1658 if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
1659 panel_mode = intel_connector->panel.fixed_mode;
1660
1661 drm_mode_debug_printmodeline(panel_mode);
1662
1663 intel_fixed_panel_mode(panel_mode, adjusted_mode);
1664
1665 if (INTEL_GEN(dev_priv) >= 9) {
1666 int ret;
1667 ret = skl_update_scaler_crtc(pipe_config);
1668 if (ret)
1669 return ret;
1670 }
1671
1672 if (HAS_GMCH_DISPLAY(dev_priv))
1673 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1674 conn_state->scaling_mode);
1675 else
1676 intel_pch_panel_fitting(intel_crtc, pipe_config,
1677 conn_state->scaling_mode);
1678 }
1679
1680 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1681 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1682 return false;
1683
1684 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1685 return false;
1686
1687 /* Use values requested by Compliance Test Request */
1688 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1689 int index;
1690
1691 /* Validate the compliance test data since max values
1692 * might have changed due to link train fallback.
1693 */
1694 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1695 intel_dp->compliance.test_lane_count)) {
1696 index = intel_dp_rate_index(intel_dp->common_rates,
1697 intel_dp->num_common_rates,
1698 intel_dp->compliance.test_link_rate);
1699 if (index >= 0)
1700 min_clock = max_clock = index;
1701 min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1702 }
1703 }
1704 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1705 "max bw %d pixel clock %iKHz\n",
1706 max_lane_count, intel_dp->common_rates[max_clock],
1707 adjusted_mode->crtc_clock);
1708
1709 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1710 * bpc in between. */
1711 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1712 if (intel_dp_is_edp(intel_dp)) {
1713
1714 /* Get bpp from vbt only for panels that dont have bpp in edid */
1715 if (intel_connector->base.display_info.bpc == 0 &&
1716 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1717 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1718 dev_priv->vbt.edp.bpp);
1719 bpp = dev_priv->vbt.edp.bpp;
1720 }
1721
1722 /*
1723 * Use the maximum clock and number of lanes the eDP panel
1724 * advertizes being capable of. The panels are generally
1725 * designed to support only a single clock and lane
1726 * configuration, and typically these values correspond to the
1727 * native resolution of the panel.
1728 */
1729 min_lane_count = max_lane_count;
1730 min_clock = max_clock;
1731 }
1732
1733 for (; bpp >= 6*3; bpp -= 2*3) {
1734 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1735 bpp);
1736
1737 for (clock = min_clock; clock <= max_clock; clock++) {
1738 for (lane_count = min_lane_count;
1739 lane_count <= max_lane_count;
1740 lane_count <<= 1) {
1741
1742 link_clock = intel_dp->common_rates[clock];
1743 link_avail = intel_dp_max_data_rate(link_clock,
1744 lane_count);
1745
1746 if (mode_rate <= link_avail) {
1747 goto found;
1748 }
1749 }
1750 }
1751 }
1752
1753 return false;
1754
1755 found:
1756 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1757 /*
1758 * See:
1759 * CEA-861-E - 5.1 Default Encoding Parameters
1760 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1761 */
1762 pipe_config->limited_color_range =
1763 bpp != 18 &&
1764 drm_default_rgb_quant_range(adjusted_mode) ==
1765 HDMI_QUANTIZATION_RANGE_LIMITED;
1766 } else {
1767 pipe_config->limited_color_range =
1768 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1769 }
1770
1771 pipe_config->lane_count = lane_count;
1772
1773 pipe_config->pipe_bpp = bpp;
1774 pipe_config->port_clock = intel_dp->common_rates[clock];
1775
1776 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1777 &link_bw, &rate_select);
1778
1779 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1780 link_bw, rate_select, pipe_config->lane_count,
1781 pipe_config->port_clock, bpp);
1782 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1783 mode_rate, link_avail);
1784
1785 intel_link_compute_m_n(bpp, lane_count,
1786 adjusted_mode->crtc_clock,
1787 pipe_config->port_clock,
1788 &pipe_config->dp_m_n,
1789 reduce_m_n);
1790
1791 if (intel_connector->panel.downclock_mode != NULL &&
1792 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1793 pipe_config->has_drrs = true;
1794 intel_link_compute_m_n(bpp, lane_count,
1795 intel_connector->panel.downclock_mode->clock,
1796 pipe_config->port_clock,
1797 &pipe_config->dp_m2_n2,
1798 reduce_m_n);
1799 }
1800
1801 /*
1802 * DPLL0 VCO may need to be adjusted to get the correct
1803 * clock for eDP. This will affect cdclk as well.
1804 */
1805 if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1806 int vco;
1807
1808 switch (pipe_config->port_clock / 2) {
1809 case 108000:
1810 case 216000:
1811 vco = 8640000;
1812 break;
1813 default:
1814 vco = 8100000;
1815 break;
1816 }
1817
1818 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1819 }
1820
1821 if (!HAS_DDI(dev_priv))
1822 intel_dp_set_clock(encoder, pipe_config);
1823
1824 intel_psr_compute_config(intel_dp, pipe_config);
1825
1826 return true;
1827 }
1828
1829 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1830 int link_rate, uint8_t lane_count,
1831 bool link_mst)
1832 {
1833 intel_dp->link_rate = link_rate;
1834 intel_dp->lane_count = lane_count;
1835 intel_dp->link_mst = link_mst;
1836 }
1837
1838 static void intel_dp_prepare(struct intel_encoder *encoder,
1839 const struct intel_crtc_state *pipe_config)
1840 {
1841 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1843 enum port port = encoder->port;
1844 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1845 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1846
1847 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1848 pipe_config->lane_count,
1849 intel_crtc_has_type(pipe_config,
1850 INTEL_OUTPUT_DP_MST));
1851
1852 /*
1853 * There are four kinds of DP registers:
1854 *
1855 * IBX PCH
1856 * SNB CPU
1857 * IVB CPU
1858 * CPT PCH
1859 *
1860 * IBX PCH and CPU are the same for almost everything,
1861 * except that the CPU DP PLL is configured in this
1862 * register
1863 *
1864 * CPT PCH is quite different, having many bits moved
1865 * to the TRANS_DP_CTL register instead. That
1866 * configuration happens (oddly) in ironlake_pch_enable
1867 */
1868
1869 /* Preserve the BIOS-computed detected bit. This is
1870 * supposed to be read-only.
1871 */
1872 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1873
1874 /* Handle DP bits in common between all three register formats */
1875 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1876 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1877
1878 /* Split out the IBX/CPU vs CPT settings */
1879
1880 if (IS_GEN7(dev_priv) && port == PORT_A) {
1881 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1882 intel_dp->DP |= DP_SYNC_HS_HIGH;
1883 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1884 intel_dp->DP |= DP_SYNC_VS_HIGH;
1885 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1886
1887 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1888 intel_dp->DP |= DP_ENHANCED_FRAMING;
1889
1890 intel_dp->DP |= crtc->pipe << 29;
1891 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1892 u32 trans_dp;
1893
1894 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1895
1896 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1897 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1898 trans_dp |= TRANS_DP_ENH_FRAMING;
1899 else
1900 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1901 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1902 } else {
1903 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1904 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1905
1906 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1907 intel_dp->DP |= DP_SYNC_HS_HIGH;
1908 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1909 intel_dp->DP |= DP_SYNC_VS_HIGH;
1910 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1911
1912 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1913 intel_dp->DP |= DP_ENHANCED_FRAMING;
1914
1915 if (IS_CHERRYVIEW(dev_priv))
1916 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1917 else if (crtc->pipe == PIPE_B)
1918 intel_dp->DP |= DP_PIPEB_SELECT;
1919 }
1920 }
1921
1922 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1923 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1924
1925 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1926 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1927
1928 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1929 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1930
1931 static void intel_pps_verify_state(struct intel_dp *intel_dp);
1932
1933 static void wait_panel_status(struct intel_dp *intel_dp,
1934 u32 mask,
1935 u32 value)
1936 {
1937 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1938 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1939
1940 lockdep_assert_held(&dev_priv->pps_mutex);
1941
1942 intel_pps_verify_state(intel_dp);
1943
1944 pp_stat_reg = _pp_stat_reg(intel_dp);
1945 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1946
1947 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1948 mask, value,
1949 I915_READ(pp_stat_reg),
1950 I915_READ(pp_ctrl_reg));
1951
1952 if (intel_wait_for_register(dev_priv,
1953 pp_stat_reg, mask, value,
1954 5000))
1955 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1956 I915_READ(pp_stat_reg),
1957 I915_READ(pp_ctrl_reg));
1958
1959 DRM_DEBUG_KMS("Wait complete\n");
1960 }
1961
1962 static void wait_panel_on(struct intel_dp *intel_dp)
1963 {
1964 DRM_DEBUG_KMS("Wait for panel power on\n");
1965 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1966 }
1967
1968 static void wait_panel_off(struct intel_dp *intel_dp)
1969 {
1970 DRM_DEBUG_KMS("Wait for panel power off time\n");
1971 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1972 }
1973
1974 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1975 {
1976 ktime_t panel_power_on_time;
1977 s64 panel_power_off_duration;
1978
1979 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1980
1981 /* take the difference of currrent time and panel power off time
1982 * and then make panel wait for t11_t12 if needed. */
1983 panel_power_on_time = ktime_get_boottime();
1984 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1985
1986 /* When we disable the VDD override bit last we have to do the manual
1987 * wait. */
1988 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1989 wait_remaining_ms_from_jiffies(jiffies,
1990 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1991
1992 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1993 }
1994
1995 static void wait_backlight_on(struct intel_dp *intel_dp)
1996 {
1997 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1998 intel_dp->backlight_on_delay);
1999 }
2000
2001 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2002 {
2003 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2004 intel_dp->backlight_off_delay);
2005 }
2006
2007 /* Read the current pp_control value, unlocking the register if it
2008 * is locked
2009 */
2010
2011 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2012 {
2013 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2014 u32 control;
2015
2016 lockdep_assert_held(&dev_priv->pps_mutex);
2017
2018 control = I915_READ(_pp_ctrl_reg(intel_dp));
2019 if (WARN_ON(!HAS_DDI(dev_priv) &&
2020 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2021 control &= ~PANEL_UNLOCK_MASK;
2022 control |= PANEL_UNLOCK_REGS;
2023 }
2024 return control;
2025 }
2026
2027 /*
2028 * Must be paired with edp_panel_vdd_off().
2029 * Must hold pps_mutex around the whole on/off sequence.
2030 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2031 */
2032 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2033 {
2034 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2035 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2036 u32 pp;
2037 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2038 bool need_to_disable = !intel_dp->want_panel_vdd;
2039
2040 lockdep_assert_held(&dev_priv->pps_mutex);
2041
2042 if (!intel_dp_is_edp(intel_dp))
2043 return false;
2044
2045 cancel_delayed_work(&intel_dp->panel_vdd_work);
2046 intel_dp->want_panel_vdd = true;
2047
2048 if (edp_have_panel_vdd(intel_dp))
2049 return need_to_disable;
2050
2051 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2052
2053 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2054 port_name(intel_dig_port->base.port));
2055
2056 if (!edp_have_panel_power(intel_dp))
2057 wait_panel_power_cycle(intel_dp);
2058
2059 pp = ironlake_get_pp_control(intel_dp);
2060 pp |= EDP_FORCE_VDD;
2061
2062 pp_stat_reg = _pp_stat_reg(intel_dp);
2063 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2064
2065 I915_WRITE(pp_ctrl_reg, pp);
2066 POSTING_READ(pp_ctrl_reg);
2067 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2068 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2069 /*
2070 * If the panel wasn't on, delay before accessing aux channel
2071 */
2072 if (!edp_have_panel_power(intel_dp)) {
2073 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2074 port_name(intel_dig_port->base.port));
2075 msleep(intel_dp->panel_power_up_delay);
2076 }
2077
2078 return need_to_disable;
2079 }
2080
2081 /*
2082 * Must be paired with intel_edp_panel_vdd_off() or
2083 * intel_edp_panel_off().
2084 * Nested calls to these functions are not allowed since
2085 * we drop the lock. Caller must use some higher level
2086 * locking to prevent nested calls from other threads.
2087 */
2088 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2089 {
2090 bool vdd;
2091
2092 if (!intel_dp_is_edp(intel_dp))
2093 return;
2094
2095 pps_lock(intel_dp);
2096 vdd = edp_panel_vdd_on(intel_dp);
2097 pps_unlock(intel_dp);
2098
2099 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2100 port_name(dp_to_dig_port(intel_dp)->base.port));
2101 }
2102
2103 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2104 {
2105 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2106 struct intel_digital_port *intel_dig_port =
2107 dp_to_dig_port(intel_dp);
2108 u32 pp;
2109 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2110
2111 lockdep_assert_held(&dev_priv->pps_mutex);
2112
2113 WARN_ON(intel_dp->want_panel_vdd);
2114
2115 if (!edp_have_panel_vdd(intel_dp))
2116 return;
2117
2118 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2119 port_name(intel_dig_port->base.port));
2120
2121 pp = ironlake_get_pp_control(intel_dp);
2122 pp &= ~EDP_FORCE_VDD;
2123
2124 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2125 pp_stat_reg = _pp_stat_reg(intel_dp);
2126
2127 I915_WRITE(pp_ctrl_reg, pp);
2128 POSTING_READ(pp_ctrl_reg);
2129
2130 /* Make sure sequencer is idle before allowing subsequent activity */
2131 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2132 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2133
2134 if ((pp & PANEL_POWER_ON) == 0)
2135 intel_dp->panel_power_off_time = ktime_get_boottime();
2136
2137 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2138 }
2139
2140 static void edp_panel_vdd_work(struct work_struct *__work)
2141 {
2142 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2143 struct intel_dp, panel_vdd_work);
2144
2145 pps_lock(intel_dp);
2146 if (!intel_dp->want_panel_vdd)
2147 edp_panel_vdd_off_sync(intel_dp);
2148 pps_unlock(intel_dp);
2149 }
2150
2151 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2152 {
2153 unsigned long delay;
2154
2155 /*
2156 * Queue the timer to fire a long time from now (relative to the power
2157 * down delay) to keep the panel power up across a sequence of
2158 * operations.
2159 */
2160 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2161 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2162 }
2163
2164 /*
2165 * Must be paired with edp_panel_vdd_on().
2166 * Must hold pps_mutex around the whole on/off sequence.
2167 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2168 */
2169 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2170 {
2171 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2172
2173 lockdep_assert_held(&dev_priv->pps_mutex);
2174
2175 if (!intel_dp_is_edp(intel_dp))
2176 return;
2177
2178 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2179 port_name(dp_to_dig_port(intel_dp)->base.port));
2180
2181 intel_dp->want_panel_vdd = false;
2182
2183 if (sync)
2184 edp_panel_vdd_off_sync(intel_dp);
2185 else
2186 edp_panel_vdd_schedule_off(intel_dp);
2187 }
2188
2189 static void edp_panel_on(struct intel_dp *intel_dp)
2190 {
2191 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2192 u32 pp;
2193 i915_reg_t pp_ctrl_reg;
2194
2195 lockdep_assert_held(&dev_priv->pps_mutex);
2196
2197 if (!intel_dp_is_edp(intel_dp))
2198 return;
2199
2200 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2201 port_name(dp_to_dig_port(intel_dp)->base.port));
2202
2203 if (WARN(edp_have_panel_power(intel_dp),
2204 "eDP port %c panel power already on\n",
2205 port_name(dp_to_dig_port(intel_dp)->base.port)))
2206 return;
2207
2208 wait_panel_power_cycle(intel_dp);
2209
2210 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2211 pp = ironlake_get_pp_control(intel_dp);
2212 if (IS_GEN5(dev_priv)) {
2213 /* ILK workaround: disable reset around power sequence */
2214 pp &= ~PANEL_POWER_RESET;
2215 I915_WRITE(pp_ctrl_reg, pp);
2216 POSTING_READ(pp_ctrl_reg);
2217 }
2218
2219 pp |= PANEL_POWER_ON;
2220 if (!IS_GEN5(dev_priv))
2221 pp |= PANEL_POWER_RESET;
2222
2223 I915_WRITE(pp_ctrl_reg, pp);
2224 POSTING_READ(pp_ctrl_reg);
2225
2226 wait_panel_on(intel_dp);
2227 intel_dp->last_power_on = jiffies;
2228
2229 if (IS_GEN5(dev_priv)) {
2230 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2231 I915_WRITE(pp_ctrl_reg, pp);
2232 POSTING_READ(pp_ctrl_reg);
2233 }
2234 }
2235
2236 void intel_edp_panel_on(struct intel_dp *intel_dp)
2237 {
2238 if (!intel_dp_is_edp(intel_dp))
2239 return;
2240
2241 pps_lock(intel_dp);
2242 edp_panel_on(intel_dp);
2243 pps_unlock(intel_dp);
2244 }
2245
2246
2247 static void edp_panel_off(struct intel_dp *intel_dp)
2248 {
2249 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2250 u32 pp;
2251 i915_reg_t pp_ctrl_reg;
2252
2253 lockdep_assert_held(&dev_priv->pps_mutex);
2254
2255 if (!intel_dp_is_edp(intel_dp))
2256 return;
2257
2258 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2259 port_name(dp_to_dig_port(intel_dp)->base.port));
2260
2261 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2262 port_name(dp_to_dig_port(intel_dp)->base.port));
2263
2264 pp = ironlake_get_pp_control(intel_dp);
2265 /* We need to switch off panel power _and_ force vdd, for otherwise some
2266 * panels get very unhappy and cease to work. */
2267 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2268 EDP_BLC_ENABLE);
2269
2270 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2271
2272 intel_dp->want_panel_vdd = false;
2273
2274 I915_WRITE(pp_ctrl_reg, pp);
2275 POSTING_READ(pp_ctrl_reg);
2276
2277 wait_panel_off(intel_dp);
2278 intel_dp->panel_power_off_time = ktime_get_boottime();
2279
2280 /* We got a reference when we enabled the VDD. */
2281 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2282 }
2283
2284 void intel_edp_panel_off(struct intel_dp *intel_dp)
2285 {
2286 if (!intel_dp_is_edp(intel_dp))
2287 return;
2288
2289 pps_lock(intel_dp);
2290 edp_panel_off(intel_dp);
2291 pps_unlock(intel_dp);
2292 }
2293
2294 /* Enable backlight in the panel power control. */
2295 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2296 {
2297 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2298 u32 pp;
2299 i915_reg_t pp_ctrl_reg;
2300
2301 /*
2302 * If we enable the backlight right away following a panel power
2303 * on, we may see slight flicker as the panel syncs with the eDP
2304 * link. So delay a bit to make sure the image is solid before
2305 * allowing it to appear.
2306 */
2307 wait_backlight_on(intel_dp);
2308
2309 pps_lock(intel_dp);
2310
2311 pp = ironlake_get_pp_control(intel_dp);
2312 pp |= EDP_BLC_ENABLE;
2313
2314 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2315
2316 I915_WRITE(pp_ctrl_reg, pp);
2317 POSTING_READ(pp_ctrl_reg);
2318
2319 pps_unlock(intel_dp);
2320 }
2321
2322 /* Enable backlight PWM and backlight PP control. */
2323 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2324 const struct drm_connector_state *conn_state)
2325 {
2326 struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2327
2328 if (!intel_dp_is_edp(intel_dp))
2329 return;
2330
2331 DRM_DEBUG_KMS("\n");
2332
2333 intel_panel_enable_backlight(crtc_state, conn_state);
2334 _intel_edp_backlight_on(intel_dp);
2335 }
2336
2337 /* Disable backlight in the panel power control. */
2338 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2339 {
2340 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2341 u32 pp;
2342 i915_reg_t pp_ctrl_reg;
2343
2344 if (!intel_dp_is_edp(intel_dp))
2345 return;
2346
2347 pps_lock(intel_dp);
2348
2349 pp = ironlake_get_pp_control(intel_dp);
2350 pp &= ~EDP_BLC_ENABLE;
2351
2352 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2353
2354 I915_WRITE(pp_ctrl_reg, pp);
2355 POSTING_READ(pp_ctrl_reg);
2356
2357 pps_unlock(intel_dp);
2358
2359 intel_dp->last_backlight_off = jiffies;
2360 edp_wait_backlight_off(intel_dp);
2361 }
2362
2363 /* Disable backlight PP control and backlight PWM. */
2364 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2365 {
2366 struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2367
2368 if (!intel_dp_is_edp(intel_dp))
2369 return;
2370
2371 DRM_DEBUG_KMS("\n");
2372
2373 _intel_edp_backlight_off(intel_dp);
2374 intel_panel_disable_backlight(old_conn_state);
2375 }
2376
2377 /*
2378 * Hook for controlling the panel power control backlight through the bl_power
2379 * sysfs attribute. Take care to handle multiple calls.
2380 */
2381 static void intel_edp_backlight_power(struct intel_connector *connector,
2382 bool enable)
2383 {
2384 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2385 bool is_enabled;
2386
2387 pps_lock(intel_dp);
2388 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2389 pps_unlock(intel_dp);
2390
2391 if (is_enabled == enable)
2392 return;
2393
2394 DRM_DEBUG_KMS("panel power control backlight %s\n",
2395 enable ? "enable" : "disable");
2396
2397 if (enable)
2398 _intel_edp_backlight_on(intel_dp);
2399 else
2400 _intel_edp_backlight_off(intel_dp);
2401 }
2402
2403 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2404 {
2405 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2406 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2407 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2408
2409 I915_STATE_WARN(cur_state != state,
2410 "DP port %c state assertion failure (expected %s, current %s)\n",
2411 port_name(dig_port->base.port),
2412 onoff(state), onoff(cur_state));
2413 }
2414 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2415
2416 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2417 {
2418 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2419
2420 I915_STATE_WARN(cur_state != state,
2421 "eDP PLL state assertion failure (expected %s, current %s)\n",
2422 onoff(state), onoff(cur_state));
2423 }
2424 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2425 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2426
2427 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2428 const struct intel_crtc_state *pipe_config)
2429 {
2430 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2432
2433 assert_pipe_disabled(dev_priv, crtc->pipe);
2434 assert_dp_port_disabled(intel_dp);
2435 assert_edp_pll_disabled(dev_priv);
2436
2437 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2438 pipe_config->port_clock);
2439
2440 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2441
2442 if (pipe_config->port_clock == 162000)
2443 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2444 else
2445 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2446
2447 I915_WRITE(DP_A, intel_dp->DP);
2448 POSTING_READ(DP_A);
2449 udelay(500);
2450
2451 /*
2452 * [DevILK] Work around required when enabling DP PLL
2453 * while a pipe is enabled going to FDI:
2454 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2455 * 2. Program DP PLL enable
2456 */
2457 if (IS_GEN5(dev_priv))
2458 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2459
2460 intel_dp->DP |= DP_PLL_ENABLE;
2461
2462 I915_WRITE(DP_A, intel_dp->DP);
2463 POSTING_READ(DP_A);
2464 udelay(200);
2465 }
2466
2467 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2468 const struct intel_crtc_state *old_crtc_state)
2469 {
2470 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2471 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2472
2473 assert_pipe_disabled(dev_priv, crtc->pipe);
2474 assert_dp_port_disabled(intel_dp);
2475 assert_edp_pll_enabled(dev_priv);
2476
2477 DRM_DEBUG_KMS("disabling eDP PLL\n");
2478
2479 intel_dp->DP &= ~DP_PLL_ENABLE;
2480
2481 I915_WRITE(DP_A, intel_dp->DP);
2482 POSTING_READ(DP_A);
2483 udelay(200);
2484 }
2485
2486 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2487 {
2488 /*
2489 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2490 * be capable of signalling downstream hpd with a long pulse.
2491 * Whether or not that means D3 is safe to use is not clear,
2492 * but let's assume so until proven otherwise.
2493 *
2494 * FIXME should really check all downstream ports...
2495 */
2496 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2497 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2498 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2499 }
2500
2501 /* If the sink supports it, try to set the power state appropriately */
2502 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2503 {
2504 int ret, i;
2505
2506 /* Should have a valid DPCD by this point */
2507 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2508 return;
2509
2510 if (mode != DRM_MODE_DPMS_ON) {
2511 if (downstream_hpd_needs_d0(intel_dp))
2512 return;
2513
2514 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2515 DP_SET_POWER_D3);
2516 } else {
2517 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2518
2519 /*
2520 * When turning on, we need to retry for 1ms to give the sink
2521 * time to wake up.
2522 */
2523 for (i = 0; i < 3; i++) {
2524 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2525 DP_SET_POWER_D0);
2526 if (ret == 1)
2527 break;
2528 msleep(1);
2529 }
2530
2531 if (ret == 1 && lspcon->active)
2532 lspcon_wait_pcon_mode(lspcon);
2533 }
2534
2535 if (ret != 1)
2536 DRM_DEBUG_KMS("failed to %s sink power state\n",
2537 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2538 }
2539
2540 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2541 enum pipe *pipe)
2542 {
2543 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2544 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2545 enum port port = encoder->port;
2546 u32 tmp;
2547 bool ret;
2548
2549 if (!intel_display_power_get_if_enabled(dev_priv,
2550 encoder->power_domain))
2551 return false;
2552
2553 ret = false;
2554
2555 tmp = I915_READ(intel_dp->output_reg);
2556
2557 if (!(tmp & DP_PORT_EN))
2558 goto out;
2559
2560 if (IS_GEN7(dev_priv) && port == PORT_A) {
2561 *pipe = PORT_TO_PIPE_CPT(tmp);
2562 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2563 enum pipe p;
2564
2565 for_each_pipe(dev_priv, p) {
2566 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2567 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2568 *pipe = p;
2569 ret = true;
2570
2571 goto out;
2572 }
2573 }
2574
2575 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2576 i915_mmio_reg_offset(intel_dp->output_reg));
2577 } else if (IS_CHERRYVIEW(dev_priv)) {
2578 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2579 } else {
2580 *pipe = PORT_TO_PIPE(tmp);
2581 }
2582
2583 ret = true;
2584
2585 out:
2586 intel_display_power_put(dev_priv, encoder->power_domain);
2587
2588 return ret;
2589 }
2590
2591 static void intel_dp_get_config(struct intel_encoder *encoder,
2592 struct intel_crtc_state *pipe_config)
2593 {
2594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2595 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2596 u32 tmp, flags = 0;
2597 enum port port = encoder->port;
2598 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2599
2600 if (encoder->type == INTEL_OUTPUT_EDP)
2601 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2602 else
2603 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2604
2605 tmp = I915_READ(intel_dp->output_reg);
2606
2607 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2608
2609 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2610 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2611
2612 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2613 flags |= DRM_MODE_FLAG_PHSYNC;
2614 else
2615 flags |= DRM_MODE_FLAG_NHSYNC;
2616
2617 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2618 flags |= DRM_MODE_FLAG_PVSYNC;
2619 else
2620 flags |= DRM_MODE_FLAG_NVSYNC;
2621 } else {
2622 if (tmp & DP_SYNC_HS_HIGH)
2623 flags |= DRM_MODE_FLAG_PHSYNC;
2624 else
2625 flags |= DRM_MODE_FLAG_NHSYNC;
2626
2627 if (tmp & DP_SYNC_VS_HIGH)
2628 flags |= DRM_MODE_FLAG_PVSYNC;
2629 else
2630 flags |= DRM_MODE_FLAG_NVSYNC;
2631 }
2632
2633 pipe_config->base.adjusted_mode.flags |= flags;
2634
2635 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2636 pipe_config->limited_color_range = true;
2637
2638 pipe_config->lane_count =
2639 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2640
2641 intel_dp_get_m_n(crtc, pipe_config);
2642
2643 if (port == PORT_A) {
2644 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2645 pipe_config->port_clock = 162000;
2646 else
2647 pipe_config->port_clock = 270000;
2648 }
2649
2650 pipe_config->base.adjusted_mode.crtc_clock =
2651 intel_dotclock_calculate(pipe_config->port_clock,
2652 &pipe_config->dp_m_n);
2653
2654 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2655 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2656 /*
2657 * This is a big fat ugly hack.
2658 *
2659 * Some machines in UEFI boot mode provide us a VBT that has 18
2660 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2661 * unknown we fail to light up. Yet the same BIOS boots up with
2662 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2663 * max, not what it tells us to use.
2664 *
2665 * Note: This will still be broken if the eDP panel is not lit
2666 * up by the BIOS, and thus we can't get the mode at module
2667 * load.
2668 */
2669 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2670 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2671 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2672 }
2673 }
2674
2675 static void intel_disable_dp(struct intel_encoder *encoder,
2676 const struct intel_crtc_state *old_crtc_state,
2677 const struct drm_connector_state *old_conn_state)
2678 {
2679 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2680
2681 if (old_crtc_state->has_audio)
2682 intel_audio_codec_disable(encoder,
2683 old_crtc_state, old_conn_state);
2684
2685 /* Make sure the panel is off before trying to change the mode. But also
2686 * ensure that we have vdd while we switch off the panel. */
2687 intel_edp_panel_vdd_on(intel_dp);
2688 intel_edp_backlight_off(old_conn_state);
2689 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2690 intel_edp_panel_off(intel_dp);
2691 }
2692
2693 static void g4x_disable_dp(struct intel_encoder *encoder,
2694 const struct intel_crtc_state *old_crtc_state,
2695 const struct drm_connector_state *old_conn_state)
2696 {
2697 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2698
2699 /* disable the port before the pipe on g4x */
2700 intel_dp_link_down(encoder, old_crtc_state);
2701 }
2702
2703 static void ilk_disable_dp(struct intel_encoder *encoder,
2704 const struct intel_crtc_state *old_crtc_state,
2705 const struct drm_connector_state *old_conn_state)
2706 {
2707 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2708 }
2709
2710 static void vlv_disable_dp(struct intel_encoder *encoder,
2711 const struct intel_crtc_state *old_crtc_state,
2712 const struct drm_connector_state *old_conn_state)
2713 {
2714 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2715
2716 intel_psr_disable(intel_dp, old_crtc_state);
2717
2718 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2719 }
2720
2721 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2722 const struct intel_crtc_state *old_crtc_state,
2723 const struct drm_connector_state *old_conn_state)
2724 {
2725 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2726 enum port port = encoder->port;
2727
2728 intel_dp_link_down(encoder, old_crtc_state);
2729
2730 /* Only ilk+ has port A */
2731 if (port == PORT_A)
2732 ironlake_edp_pll_off(intel_dp, old_crtc_state);
2733 }
2734
2735 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2736 const struct intel_crtc_state *old_crtc_state,
2737 const struct drm_connector_state *old_conn_state)
2738 {
2739 intel_dp_link_down(encoder, old_crtc_state);
2740 }
2741
2742 static void chv_post_disable_dp(struct intel_encoder *encoder,
2743 const struct intel_crtc_state *old_crtc_state,
2744 const struct drm_connector_state *old_conn_state)
2745 {
2746 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2747
2748 intel_dp_link_down(encoder, old_crtc_state);
2749
2750 mutex_lock(&dev_priv->sb_lock);
2751
2752 /* Assert data lane reset */
2753 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2754
2755 mutex_unlock(&dev_priv->sb_lock);
2756 }
2757
2758 static void
2759 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2760 uint32_t *DP,
2761 uint8_t dp_train_pat)
2762 {
2763 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2764 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2765 enum port port = intel_dig_port->base.port;
2766
2767 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2768 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2769 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2770
2771 if (HAS_DDI(dev_priv)) {
2772 uint32_t temp = I915_READ(DP_TP_CTL(port));
2773
2774 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2775 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2776 else
2777 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2778
2779 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2780 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2781 case DP_TRAINING_PATTERN_DISABLE:
2782 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2783
2784 break;
2785 case DP_TRAINING_PATTERN_1:
2786 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2787 break;
2788 case DP_TRAINING_PATTERN_2:
2789 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2790 break;
2791 case DP_TRAINING_PATTERN_3:
2792 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2793 break;
2794 }
2795 I915_WRITE(DP_TP_CTL(port), temp);
2796
2797 } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2798 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2799 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2800
2801 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2802 case DP_TRAINING_PATTERN_DISABLE:
2803 *DP |= DP_LINK_TRAIN_OFF_CPT;
2804 break;
2805 case DP_TRAINING_PATTERN_1:
2806 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2807 break;
2808 case DP_TRAINING_PATTERN_2:
2809 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2810 break;
2811 case DP_TRAINING_PATTERN_3:
2812 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2813 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2814 break;
2815 }
2816
2817 } else {
2818 if (IS_CHERRYVIEW(dev_priv))
2819 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2820 else
2821 *DP &= ~DP_LINK_TRAIN_MASK;
2822
2823 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2824 case DP_TRAINING_PATTERN_DISABLE:
2825 *DP |= DP_LINK_TRAIN_OFF;
2826 break;
2827 case DP_TRAINING_PATTERN_1:
2828 *DP |= DP_LINK_TRAIN_PAT_1;
2829 break;
2830 case DP_TRAINING_PATTERN_2:
2831 *DP |= DP_LINK_TRAIN_PAT_2;
2832 break;
2833 case DP_TRAINING_PATTERN_3:
2834 if (IS_CHERRYVIEW(dev_priv)) {
2835 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2836 } else {
2837 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2838 *DP |= DP_LINK_TRAIN_PAT_2;
2839 }
2840 break;
2841 }
2842 }
2843 }
2844
2845 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2846 const struct intel_crtc_state *old_crtc_state)
2847 {
2848 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2849
2850 /* enable with pattern 1 (as per spec) */
2851
2852 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2853
2854 /*
2855 * Magic for VLV/CHV. We _must_ first set up the register
2856 * without actually enabling the port, and then do another
2857 * write to enable the port. Otherwise link training will
2858 * fail when the power sequencer is freshly used for this port.
2859 */
2860 intel_dp->DP |= DP_PORT_EN;
2861 if (old_crtc_state->has_audio)
2862 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2863
2864 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2865 POSTING_READ(intel_dp->output_reg);
2866 }
2867
2868 static void intel_enable_dp(struct intel_encoder *encoder,
2869 const struct intel_crtc_state *pipe_config,
2870 const struct drm_connector_state *conn_state)
2871 {
2872 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2873 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2874 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2875 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2876 enum pipe pipe = crtc->pipe;
2877
2878 if (WARN_ON(dp_reg & DP_PORT_EN))
2879 return;
2880
2881 pps_lock(intel_dp);
2882
2883 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2884 vlv_init_panel_power_sequencer(encoder, pipe_config);
2885
2886 intel_dp_enable_port(intel_dp, pipe_config);
2887
2888 edp_panel_vdd_on(intel_dp);
2889 edp_panel_on(intel_dp);
2890 edp_panel_vdd_off(intel_dp, true);
2891
2892 pps_unlock(intel_dp);
2893
2894 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2895 unsigned int lane_mask = 0x0;
2896
2897 if (IS_CHERRYVIEW(dev_priv))
2898 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2899
2900 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2901 lane_mask);
2902 }
2903
2904 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2905 intel_dp_start_link_train(intel_dp);
2906 intel_dp_stop_link_train(intel_dp);
2907
2908 if (pipe_config->has_audio) {
2909 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2910 pipe_name(pipe));
2911 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2912 }
2913 }
2914
2915 static void g4x_enable_dp(struct intel_encoder *encoder,
2916 const struct intel_crtc_state *pipe_config,
2917 const struct drm_connector_state *conn_state)
2918 {
2919 intel_enable_dp(encoder, pipe_config, conn_state);
2920 intel_edp_backlight_on(pipe_config, conn_state);
2921 }
2922
2923 static void vlv_enable_dp(struct intel_encoder *encoder,
2924 const struct intel_crtc_state *pipe_config,
2925 const struct drm_connector_state *conn_state)
2926 {
2927 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2928
2929 intel_edp_backlight_on(pipe_config, conn_state);
2930 intel_psr_enable(intel_dp, pipe_config);
2931 }
2932
2933 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2934 const struct intel_crtc_state *pipe_config,
2935 const struct drm_connector_state *conn_state)
2936 {
2937 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2938 enum port port = encoder->port;
2939
2940 intel_dp_prepare(encoder, pipe_config);
2941
2942 /* Only ilk+ has port A */
2943 if (port == PORT_A)
2944 ironlake_edp_pll_on(intel_dp, pipe_config);
2945 }
2946
2947 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2948 {
2949 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2950 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2951 enum pipe pipe = intel_dp->pps_pipe;
2952 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2953
2954 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2955
2956 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2957 return;
2958
2959 edp_panel_vdd_off_sync(intel_dp);
2960
2961 /*
2962 * VLV seems to get confused when multiple power seqeuencers
2963 * have the same port selected (even if only one has power/vdd
2964 * enabled). The failure manifests as vlv_wait_port_ready() failing
2965 * CHV on the other hand doesn't seem to mind having the same port
2966 * selected in multiple power seqeuencers, but let's clear the
2967 * port select always when logically disconnecting a power sequencer
2968 * from a port.
2969 */
2970 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2971 pipe_name(pipe), port_name(intel_dig_port->base.port));
2972 I915_WRITE(pp_on_reg, 0);
2973 POSTING_READ(pp_on_reg);
2974
2975 intel_dp->pps_pipe = INVALID_PIPE;
2976 }
2977
2978 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
2979 enum pipe pipe)
2980 {
2981 struct intel_encoder *encoder;
2982
2983 lockdep_assert_held(&dev_priv->pps_mutex);
2984
2985 for_each_intel_encoder(&dev_priv->drm, encoder) {
2986 struct intel_dp *intel_dp;
2987 enum port port;
2988
2989 if (encoder->type != INTEL_OUTPUT_DP &&
2990 encoder->type != INTEL_OUTPUT_EDP)
2991 continue;
2992
2993 intel_dp = enc_to_intel_dp(&encoder->base);
2994 port = dp_to_dig_port(intel_dp)->base.port;
2995
2996 WARN(intel_dp->active_pipe == pipe,
2997 "stealing pipe %c power sequencer from active (e)DP port %c\n",
2998 pipe_name(pipe), port_name(port));
2999
3000 if (intel_dp->pps_pipe != pipe)
3001 continue;
3002
3003 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3004 pipe_name(pipe), port_name(port));
3005
3006 /* make sure vdd is off before we steal it */
3007 vlv_detach_power_sequencer(intel_dp);
3008 }
3009 }
3010
3011 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3012 const struct intel_crtc_state *crtc_state)
3013 {
3014 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3015 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3016 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3017
3018 lockdep_assert_held(&dev_priv->pps_mutex);
3019
3020 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3021
3022 if (intel_dp->pps_pipe != INVALID_PIPE &&
3023 intel_dp->pps_pipe != crtc->pipe) {
3024 /*
3025 * If another power sequencer was being used on this
3026 * port previously make sure to turn off vdd there while
3027 * we still have control of it.
3028 */
3029 vlv_detach_power_sequencer(intel_dp);
3030 }
3031
3032 /*
3033 * We may be stealing the power
3034 * sequencer from another port.
3035 */
3036 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3037
3038 intel_dp->active_pipe = crtc->pipe;
3039
3040 if (!intel_dp_is_edp(intel_dp))
3041 return;
3042
3043 /* now it's all ours */
3044 intel_dp->pps_pipe = crtc->pipe;
3045
3046 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3047 pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3048
3049 /* init power sequencer on this pipe and port */
3050 intel_dp_init_panel_power_sequencer(intel_dp);
3051 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3052 }
3053
3054 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3055 const struct intel_crtc_state *pipe_config,
3056 const struct drm_connector_state *conn_state)
3057 {
3058 vlv_phy_pre_encoder_enable(encoder, pipe_config);
3059
3060 intel_enable_dp(encoder, pipe_config, conn_state);
3061 }
3062
3063 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3064 const struct intel_crtc_state *pipe_config,
3065 const struct drm_connector_state *conn_state)
3066 {
3067 intel_dp_prepare(encoder, pipe_config);
3068
3069 vlv_phy_pre_pll_enable(encoder, pipe_config);
3070 }
3071
3072 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3073 const struct intel_crtc_state *pipe_config,
3074 const struct drm_connector_state *conn_state)
3075 {
3076 chv_phy_pre_encoder_enable(encoder, pipe_config);
3077
3078 intel_enable_dp(encoder, pipe_config, conn_state);
3079
3080 /* Second common lane will stay alive on its own now */
3081 chv_phy_release_cl2_override(encoder);
3082 }
3083
3084 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3085 const struct intel_crtc_state *pipe_config,
3086 const struct drm_connector_state *conn_state)
3087 {
3088 intel_dp_prepare(encoder, pipe_config);
3089
3090 chv_phy_pre_pll_enable(encoder, pipe_config);
3091 }
3092
3093 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3094 const struct intel_crtc_state *old_crtc_state,
3095 const struct drm_connector_state *old_conn_state)
3096 {
3097 chv_phy_post_pll_disable(encoder, old_crtc_state);
3098 }
3099
3100 /*
3101 * Fetch AUX CH registers 0x202 - 0x207 which contain
3102 * link status information
3103 */
3104 bool
3105 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3106 {
3107 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3108 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3109 }
3110
3111 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3112 {
3113 uint8_t psr_caps = 0;
3114
3115 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
3116 return false;
3117 return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3118 }
3119
3120 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3121 {
3122 uint8_t dprx = 0;
3123
3124 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3125 &dprx) != 1)
3126 return false;
3127 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3128 }
3129
3130 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3131 {
3132 uint8_t alpm_caps = 0;
3133
3134 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
3135 &alpm_caps) != 1)
3136 return false;
3137 return alpm_caps & DP_ALPM_CAP;
3138 }
3139
3140 /* These are source-specific values. */
3141 uint8_t
3142 intel_dp_voltage_max(struct intel_dp *intel_dp)
3143 {
3144 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3145 enum port port = dp_to_dig_port(intel_dp)->base.port;
3146
3147 if (INTEL_GEN(dev_priv) >= 9) {
3148 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3149 return intel_ddi_dp_voltage_max(encoder);
3150 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3151 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3152 else if (IS_GEN7(dev_priv) && port == PORT_A)
3153 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3154 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3155 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3156 else
3157 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3158 }
3159
3160 uint8_t
3161 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3162 {
3163 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3164 enum port port = dp_to_dig_port(intel_dp)->base.port;
3165
3166 if (INTEL_GEN(dev_priv) >= 9) {
3167 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3169 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3171 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3173 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3175 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3176 default:
3177 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3178 }
3179 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3180 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3182 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3184 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3186 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3188 default:
3189 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3190 }
3191 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3192 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3194 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3196 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3198 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3200 default:
3201 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3202 }
3203 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3204 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3206 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3209 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3210 default:
3211 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3212 }
3213 } else {
3214 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3216 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3218 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3220 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3222 default:
3223 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3224 }
3225 }
3226 }
3227
3228 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3229 {
3230 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3231 unsigned long demph_reg_value, preemph_reg_value,
3232 uniqtranscale_reg_value;
3233 uint8_t train_set = intel_dp->train_set[0];
3234
3235 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3236 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3237 preemph_reg_value = 0x0004000;
3238 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3240 demph_reg_value = 0x2B405555;
3241 uniqtranscale_reg_value = 0x552AB83A;
3242 break;
3243 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3244 demph_reg_value = 0x2B404040;
3245 uniqtranscale_reg_value = 0x5548B83A;
3246 break;
3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3248 demph_reg_value = 0x2B245555;
3249 uniqtranscale_reg_value = 0x5560B83A;
3250 break;
3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3252 demph_reg_value = 0x2B405555;
3253 uniqtranscale_reg_value = 0x5598DA3A;
3254 break;
3255 default:
3256 return 0;
3257 }
3258 break;
3259 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3260 preemph_reg_value = 0x0002000;
3261 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3263 demph_reg_value = 0x2B404040;
3264 uniqtranscale_reg_value = 0x5552B83A;
3265 break;
3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3267 demph_reg_value = 0x2B404848;
3268 uniqtranscale_reg_value = 0x5580B83A;
3269 break;
3270 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3271 demph_reg_value = 0x2B404040;
3272 uniqtranscale_reg_value = 0x55ADDA3A;
3273 break;
3274 default:
3275 return 0;
3276 }
3277 break;
3278 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3279 preemph_reg_value = 0x0000000;
3280 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3282 demph_reg_value = 0x2B305555;
3283 uniqtranscale_reg_value = 0x5570B83A;
3284 break;
3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3286 demph_reg_value = 0x2B2B4040;
3287 uniqtranscale_reg_value = 0x55ADDA3A;
3288 break;
3289 default:
3290 return 0;
3291 }
3292 break;
3293 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3294 preemph_reg_value = 0x0006000;
3295 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3297 demph_reg_value = 0x1B405555;
3298 uniqtranscale_reg_value = 0x55ADDA3A;
3299 break;
3300 default:
3301 return 0;
3302 }
3303 break;
3304 default:
3305 return 0;
3306 }
3307
3308 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3309 uniqtranscale_reg_value, 0);
3310
3311 return 0;
3312 }
3313
3314 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3315 {
3316 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3317 u32 deemph_reg_value, margin_reg_value;
3318 bool uniq_trans_scale = false;
3319 uint8_t train_set = intel_dp->train_set[0];
3320
3321 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3322 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3323 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3325 deemph_reg_value = 128;
3326 margin_reg_value = 52;
3327 break;
3328 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3329 deemph_reg_value = 128;
3330 margin_reg_value = 77;
3331 break;
3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3333 deemph_reg_value = 128;
3334 margin_reg_value = 102;
3335 break;
3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3337 deemph_reg_value = 128;
3338 margin_reg_value = 154;
3339 uniq_trans_scale = true;
3340 break;
3341 default:
3342 return 0;
3343 }
3344 break;
3345 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3346 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3347 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3348 deemph_reg_value = 85;
3349 margin_reg_value = 78;
3350 break;
3351 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3352 deemph_reg_value = 85;
3353 margin_reg_value = 116;
3354 break;
3355 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3356 deemph_reg_value = 85;
3357 margin_reg_value = 154;
3358 break;
3359 default:
3360 return 0;
3361 }
3362 break;
3363 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3364 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3365 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3366 deemph_reg_value = 64;
3367 margin_reg_value = 104;
3368 break;
3369 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3370 deemph_reg_value = 64;
3371 margin_reg_value = 154;
3372 break;
3373 default:
3374 return 0;
3375 }
3376 break;
3377 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3378 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3379 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3380 deemph_reg_value = 43;
3381 margin_reg_value = 154;
3382 break;
3383 default:
3384 return 0;
3385 }
3386 break;
3387 default:
3388 return 0;
3389 }
3390
3391 chv_set_phy_signal_level(encoder, deemph_reg_value,
3392 margin_reg_value, uniq_trans_scale);
3393
3394 return 0;
3395 }
3396
3397 static uint32_t
3398 gen4_signal_levels(uint8_t train_set)
3399 {
3400 uint32_t signal_levels = 0;
3401
3402 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3403 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3404 default:
3405 signal_levels |= DP_VOLTAGE_0_4;
3406 break;
3407 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3408 signal_levels |= DP_VOLTAGE_0_6;
3409 break;
3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3411 signal_levels |= DP_VOLTAGE_0_8;
3412 break;
3413 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3414 signal_levels |= DP_VOLTAGE_1_2;
3415 break;
3416 }
3417 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3418 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3419 default:
3420 signal_levels |= DP_PRE_EMPHASIS_0;
3421 break;
3422 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3423 signal_levels |= DP_PRE_EMPHASIS_3_5;
3424 break;
3425 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3426 signal_levels |= DP_PRE_EMPHASIS_6;
3427 break;
3428 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3429 signal_levels |= DP_PRE_EMPHASIS_9_5;
3430 break;
3431 }
3432 return signal_levels;
3433 }
3434
3435 /* Gen6's DP voltage swing and pre-emphasis control */
3436 static uint32_t
3437 gen6_edp_signal_levels(uint8_t train_set)
3438 {
3439 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3440 DP_TRAIN_PRE_EMPHASIS_MASK);
3441 switch (signal_levels) {
3442 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3443 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3444 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3445 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3446 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3448 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3449 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3450 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3451 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3452 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3454 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3455 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3456 default:
3457 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3458 "0x%x\n", signal_levels);
3459 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3460 }
3461 }
3462
3463 /* Gen7's DP voltage swing and pre-emphasis control */
3464 static uint32_t
3465 gen7_edp_signal_levels(uint8_t train_set)
3466 {
3467 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3468 DP_TRAIN_PRE_EMPHASIS_MASK);
3469 switch (signal_levels) {
3470 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3471 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3472 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3473 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3474 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3475 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3476
3477 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3478 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3479 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3480 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3481
3482 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3483 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3484 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3485 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3486
3487 default:
3488 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3489 "0x%x\n", signal_levels);
3490 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3491 }
3492 }
3493
3494 void
3495 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3496 {
3497 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3498 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3499 enum port port = intel_dig_port->base.port;
3500 uint32_t signal_levels, mask = 0;
3501 uint8_t train_set = intel_dp->train_set[0];
3502
3503 if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3504 signal_levels = bxt_signal_levels(intel_dp);
3505 } else if (HAS_DDI(dev_priv)) {
3506 signal_levels = ddi_signal_levels(intel_dp);
3507 mask = DDI_BUF_EMP_MASK;
3508 } else if (IS_CHERRYVIEW(dev_priv)) {
3509 signal_levels = chv_signal_levels(intel_dp);
3510 } else if (IS_VALLEYVIEW(dev_priv)) {
3511 signal_levels = vlv_signal_levels(intel_dp);
3512 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3513 signal_levels = gen7_edp_signal_levels(train_set);
3514 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3515 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3516 signal_levels = gen6_edp_signal_levels(train_set);
3517 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3518 } else {
3519 signal_levels = gen4_signal_levels(train_set);
3520 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3521 }
3522
3523 if (mask)
3524 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3525
3526 DRM_DEBUG_KMS("Using vswing level %d\n",
3527 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3528 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3529 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3530 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3531
3532 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3533
3534 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3535 POSTING_READ(intel_dp->output_reg);
3536 }
3537
3538 void
3539 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3540 uint8_t dp_train_pat)
3541 {
3542 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3543 struct drm_i915_private *dev_priv =
3544 to_i915(intel_dig_port->base.base.dev);
3545
3546 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3547
3548 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3549 POSTING_READ(intel_dp->output_reg);
3550 }
3551
3552 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3553 {
3554 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3556 enum port port = intel_dig_port->base.port;
3557 uint32_t val;
3558
3559 if (!HAS_DDI(dev_priv))
3560 return;
3561
3562 val = I915_READ(DP_TP_CTL(port));
3563 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3564 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3565 I915_WRITE(DP_TP_CTL(port), val);
3566
3567 /*
3568 * On PORT_A we can have only eDP in SST mode. There the only reason
3569 * we need to set idle transmission mode is to work around a HW issue
3570 * where we enable the pipe while not in idle link-training mode.
3571 * In this case there is requirement to wait for a minimum number of
3572 * idle patterns to be sent.
3573 */
3574 if (port == PORT_A)
3575 return;
3576
3577 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3578 DP_TP_STATUS_IDLE_DONE,
3579 DP_TP_STATUS_IDLE_DONE,
3580 1))
3581 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3582 }
3583
3584 static void
3585 intel_dp_link_down(struct intel_encoder *encoder,
3586 const struct intel_crtc_state *old_crtc_state)
3587 {
3588 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3589 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3590 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3591 enum port port = encoder->port;
3592 uint32_t DP = intel_dp->DP;
3593
3594 if (WARN_ON(HAS_DDI(dev_priv)))
3595 return;
3596
3597 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3598 return;
3599
3600 DRM_DEBUG_KMS("\n");
3601
3602 if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3603 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3604 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3605 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3606 } else {
3607 if (IS_CHERRYVIEW(dev_priv))
3608 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3609 else
3610 DP &= ~DP_LINK_TRAIN_MASK;
3611 DP |= DP_LINK_TRAIN_PAT_IDLE;
3612 }
3613 I915_WRITE(intel_dp->output_reg, DP);
3614 POSTING_READ(intel_dp->output_reg);
3615
3616 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3617 I915_WRITE(intel_dp->output_reg, DP);
3618 POSTING_READ(intel_dp->output_reg);
3619
3620 /*
3621 * HW workaround for IBX, we need to move the port
3622 * to transcoder A after disabling it to allow the
3623 * matching HDMI port to be enabled on transcoder A.
3624 */
3625 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3626 /*
3627 * We get CPU/PCH FIFO underruns on the other pipe when
3628 * doing the workaround. Sweep them under the rug.
3629 */
3630 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3631 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3632
3633 /* always enable with pattern 1 (as per spec) */
3634 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3635 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3636 I915_WRITE(intel_dp->output_reg, DP);
3637 POSTING_READ(intel_dp->output_reg);
3638
3639 DP &= ~DP_PORT_EN;
3640 I915_WRITE(intel_dp->output_reg, DP);
3641 POSTING_READ(intel_dp->output_reg);
3642
3643 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3644 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3645 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3646 }
3647
3648 msleep(intel_dp->panel_power_down_delay);
3649
3650 intel_dp->DP = DP;
3651
3652 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3653 pps_lock(intel_dp);
3654 intel_dp->active_pipe = INVALID_PIPE;
3655 pps_unlock(intel_dp);
3656 }
3657 }
3658
3659 bool
3660 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3661 {
3662 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3663 sizeof(intel_dp->dpcd)) < 0)
3664 return false; /* aux transfer failed */
3665
3666 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3667
3668 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3669 }
3670
3671 static bool
3672 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3673 {
3674 struct drm_i915_private *dev_priv =
3675 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3676
3677 /* this function is meant to be called only once */
3678 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3679
3680 if (!intel_dp_read_dpcd(intel_dp))
3681 return false;
3682
3683 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3684 drm_dp_is_branch(intel_dp->dpcd));
3685
3686 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3687 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3688 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3689
3690 /* Check if the panel supports PSR */
3691 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3692 intel_dp->psr_dpcd,
3693 sizeof(intel_dp->psr_dpcd));
3694 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3695 dev_priv->psr.sink_support = true;
3696 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3697 }
3698
3699 if (INTEL_GEN(dev_priv) >= 9 &&
3700 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3701 uint8_t frame_sync_cap;
3702
3703 dev_priv->psr.sink_support = true;
3704 if (drm_dp_dpcd_readb(&intel_dp->aux,
3705 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3706 &frame_sync_cap) != 1)
3707 frame_sync_cap = 0;
3708 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3709 /* PSR2 needs frame sync as well */
3710 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3711 DRM_DEBUG_KMS("PSR2 %s on sink",
3712 dev_priv->psr.psr2_support ? "supported" : "not supported");
3713
3714 if (dev_priv->psr.psr2_support) {
3715 dev_priv->psr.y_cord_support =
3716 intel_dp_get_y_cord_status(intel_dp);
3717 dev_priv->psr.colorimetry_support =
3718 intel_dp_get_colorimetry_status(intel_dp);
3719 dev_priv->psr.alpm =
3720 intel_dp_get_alpm_status(intel_dp);
3721 }
3722
3723 }
3724
3725 /*
3726 * Read the eDP display control registers.
3727 *
3728 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3729 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3730 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3731 * method). The display control registers should read zero if they're
3732 * not supported anyway.
3733 */
3734 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3735 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3736 sizeof(intel_dp->edp_dpcd))
3737 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3738 intel_dp->edp_dpcd);
3739
3740 /* Read the eDP 1.4+ supported link rates. */
3741 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3742 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3743 int i;
3744
3745 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3746 sink_rates, sizeof(sink_rates));
3747
3748 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3749 int val = le16_to_cpu(sink_rates[i]);
3750
3751 if (val == 0)
3752 break;
3753
3754 /* Value read multiplied by 200kHz gives the per-lane
3755 * link rate in kHz. The source rates are, however,
3756 * stored in terms of LS_Clk kHz. The full conversion
3757 * back to symbols is
3758 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3759 */
3760 intel_dp->sink_rates[i] = (val * 200) / 10;
3761 }
3762 intel_dp->num_sink_rates = i;
3763 }
3764
3765 /*
3766 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3767 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3768 */
3769 if (intel_dp->num_sink_rates)
3770 intel_dp->use_rate_select = true;
3771 else
3772 intel_dp_set_sink_rates(intel_dp);
3773
3774 intel_dp_set_common_rates(intel_dp);
3775
3776 return true;
3777 }
3778
3779
3780 static bool
3781 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3782 {
3783 u8 sink_count;
3784
3785 if (!intel_dp_read_dpcd(intel_dp))
3786 return false;
3787
3788 /* Don't clobber cached eDP rates. */
3789 if (!intel_dp_is_edp(intel_dp)) {
3790 intel_dp_set_sink_rates(intel_dp);
3791 intel_dp_set_common_rates(intel_dp);
3792 }
3793
3794 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3795 return false;
3796
3797 /*
3798 * Sink count can change between short pulse hpd hence
3799 * a member variable in intel_dp will track any changes
3800 * between short pulse interrupts.
3801 */
3802 intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3803
3804 /*
3805 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3806 * a dongle is present but no display. Unless we require to know
3807 * if a dongle is present or not, we don't need to update
3808 * downstream port information. So, an early return here saves
3809 * time from performing other operations which are not required.
3810 */
3811 if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3812 return false;
3813
3814 if (!drm_dp_is_branch(intel_dp->dpcd))
3815 return true; /* native DP sink */
3816
3817 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3818 return true; /* no per-port downstream info */
3819
3820 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3821 intel_dp->downstream_ports,
3822 DP_MAX_DOWNSTREAM_PORTS) < 0)
3823 return false; /* downstream port status fetch failed */
3824
3825 return true;
3826 }
3827
3828 static bool
3829 intel_dp_can_mst(struct intel_dp *intel_dp)
3830 {
3831 u8 mstm_cap;
3832
3833 if (!i915_modparams.enable_dp_mst)
3834 return false;
3835
3836 if (!intel_dp->can_mst)
3837 return false;
3838
3839 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3840 return false;
3841
3842 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3843 return false;
3844
3845 return mstm_cap & DP_MST_CAP;
3846 }
3847
3848 static void
3849 intel_dp_configure_mst(struct intel_dp *intel_dp)
3850 {
3851 if (!i915_modparams.enable_dp_mst)
3852 return;
3853
3854 if (!intel_dp->can_mst)
3855 return;
3856
3857 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3858
3859 if (intel_dp->is_mst)
3860 DRM_DEBUG_KMS("Sink is MST capable\n");
3861 else
3862 DRM_DEBUG_KMS("Sink is not MST capable\n");
3863
3864 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3865 intel_dp->is_mst);
3866 }
3867
3868 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp,
3869 struct intel_crtc_state *crtc_state, bool disable_wa)
3870 {
3871 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3872 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3874 u8 buf;
3875 int ret = 0;
3876 int count = 0;
3877 int attempts = 10;
3878
3879 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3880 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3881 ret = -EIO;
3882 goto out;
3883 }
3884
3885 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3886 buf & ~DP_TEST_SINK_START) < 0) {
3887 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3888 ret = -EIO;
3889 goto out;
3890 }
3891
3892 do {
3893 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3894
3895 if (drm_dp_dpcd_readb(&intel_dp->aux,
3896 DP_TEST_SINK_MISC, &buf) < 0) {
3897 ret = -EIO;
3898 goto out;
3899 }
3900 count = buf & DP_TEST_COUNT_MASK;
3901 } while (--attempts && count);
3902
3903 if (attempts == 0) {
3904 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3905 ret = -ETIMEDOUT;
3906 }
3907
3908 out:
3909 if (disable_wa)
3910 hsw_enable_ips(crtc_state);
3911 return ret;
3912 }
3913
3914 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp,
3915 struct intel_crtc_state *crtc_state)
3916 {
3917 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3918 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3920 u8 buf;
3921 int ret;
3922
3923 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3924 return -EIO;
3925
3926 if (!(buf & DP_TEST_CRC_SUPPORTED))
3927 return -ENOTTY;
3928
3929 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3930 return -EIO;
3931
3932 if (buf & DP_TEST_SINK_START) {
3933 ret = intel_dp_sink_crc_stop(intel_dp, crtc_state, false);
3934 if (ret)
3935 return ret;
3936 }
3937
3938 hsw_disable_ips(crtc_state);
3939
3940 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3941 buf | DP_TEST_SINK_START) < 0) {
3942 hsw_enable_ips(crtc_state);
3943 return -EIO;
3944 }
3945
3946 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3947 return 0;
3948 }
3949
3950 int intel_dp_sink_crc(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, u8 *crc)
3951 {
3952 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3953 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3955 u8 buf;
3956 int count, ret;
3957 int attempts = 6;
3958
3959 ret = intel_dp_sink_crc_start(intel_dp, crtc_state);
3960 if (ret)
3961 return ret;
3962
3963 do {
3964 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3965
3966 if (drm_dp_dpcd_readb(&intel_dp->aux,
3967 DP_TEST_SINK_MISC, &buf) < 0) {
3968 ret = -EIO;
3969 goto stop;
3970 }
3971 count = buf & DP_TEST_COUNT_MASK;
3972
3973 } while (--attempts && count == 0);
3974
3975 if (attempts == 0) {
3976 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3977 ret = -ETIMEDOUT;
3978 goto stop;
3979 }
3980
3981 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3982 ret = -EIO;
3983 goto stop;
3984 }
3985
3986 stop:
3987 intel_dp_sink_crc_stop(intel_dp, crtc_state, true);
3988 return ret;
3989 }
3990
3991 static bool
3992 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3993 {
3994 return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
3995 sink_irq_vector) == 1;
3996 }
3997
3998 static bool
3999 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4000 {
4001 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4002 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4003 DP_DPRX_ESI_LEN;
4004 }
4005
4006 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4007 {
4008 int status = 0;
4009 int test_link_rate;
4010 uint8_t test_lane_count, test_link_bw;
4011 /* (DP CTS 1.2)
4012 * 4.3.1.11
4013 */
4014 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4015 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4016 &test_lane_count);
4017
4018 if (status <= 0) {
4019 DRM_DEBUG_KMS("Lane count read failed\n");
4020 return DP_TEST_NAK;
4021 }
4022 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4023
4024 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4025 &test_link_bw);
4026 if (status <= 0) {
4027 DRM_DEBUG_KMS("Link Rate read failed\n");
4028 return DP_TEST_NAK;
4029 }
4030 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4031
4032 /* Validate the requested link rate and lane count */
4033 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4034 test_lane_count))
4035 return DP_TEST_NAK;
4036
4037 intel_dp->compliance.test_lane_count = test_lane_count;
4038 intel_dp->compliance.test_link_rate = test_link_rate;
4039
4040 return DP_TEST_ACK;
4041 }
4042
4043 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4044 {
4045 uint8_t test_pattern;
4046 uint8_t test_misc;
4047 __be16 h_width, v_height;
4048 int status = 0;
4049
4050 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4051 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4052 &test_pattern);
4053 if (status <= 0) {
4054 DRM_DEBUG_KMS("Test pattern read failed\n");
4055 return DP_TEST_NAK;
4056 }
4057 if (test_pattern != DP_COLOR_RAMP)
4058 return DP_TEST_NAK;
4059
4060 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4061 &h_width, 2);
4062 if (status <= 0) {
4063 DRM_DEBUG_KMS("H Width read failed\n");
4064 return DP_TEST_NAK;
4065 }
4066
4067 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4068 &v_height, 2);
4069 if (status <= 0) {
4070 DRM_DEBUG_KMS("V Height read failed\n");
4071 return DP_TEST_NAK;
4072 }
4073
4074 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4075 &test_misc);
4076 if (status <= 0) {
4077 DRM_DEBUG_KMS("TEST MISC read failed\n");
4078 return DP_TEST_NAK;
4079 }
4080 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4081 return DP_TEST_NAK;
4082 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4083 return DP_TEST_NAK;
4084 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4085 case DP_TEST_BIT_DEPTH_6:
4086 intel_dp->compliance.test_data.bpc = 6;
4087 break;
4088 case DP_TEST_BIT_DEPTH_8:
4089 intel_dp->compliance.test_data.bpc = 8;
4090 break;
4091 default:
4092 return DP_TEST_NAK;
4093 }
4094
4095 intel_dp->compliance.test_data.video_pattern = test_pattern;
4096 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4097 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4098 /* Set test active flag here so userspace doesn't interrupt things */
4099 intel_dp->compliance.test_active = 1;
4100
4101 return DP_TEST_ACK;
4102 }
4103
4104 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4105 {
4106 uint8_t test_result = DP_TEST_ACK;
4107 struct intel_connector *intel_connector = intel_dp->attached_connector;
4108 struct drm_connector *connector = &intel_connector->base;
4109
4110 if (intel_connector->detect_edid == NULL ||
4111 connector->edid_corrupt ||
4112 intel_dp->aux.i2c_defer_count > 6) {
4113 /* Check EDID read for NACKs, DEFERs and corruption
4114 * (DP CTS 1.2 Core r1.1)
4115 * 4.2.2.4 : Failed EDID read, I2C_NAK
4116 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4117 * 4.2.2.6 : EDID corruption detected
4118 * Use failsafe mode for all cases
4119 */
4120 if (intel_dp->aux.i2c_nack_count > 0 ||
4121 intel_dp->aux.i2c_defer_count > 0)
4122 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4123 intel_dp->aux.i2c_nack_count,
4124 intel_dp->aux.i2c_defer_count);
4125 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4126 } else {
4127 struct edid *block = intel_connector->detect_edid;
4128
4129 /* We have to write the checksum
4130 * of the last block read
4131 */
4132 block += intel_connector->detect_edid->extensions;
4133
4134 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4135 block->checksum) <= 0)
4136 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4137
4138 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4139 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4140 }
4141
4142 /* Set test active flag here so userspace doesn't interrupt things */
4143 intel_dp->compliance.test_active = 1;
4144
4145 return test_result;
4146 }
4147
4148 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4149 {
4150 uint8_t test_result = DP_TEST_NAK;
4151 return test_result;
4152 }
4153
4154 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4155 {
4156 uint8_t response = DP_TEST_NAK;
4157 uint8_t request = 0;
4158 int status;
4159
4160 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4161 if (status <= 0) {
4162 DRM_DEBUG_KMS("Could not read test request from sink\n");
4163 goto update_status;
4164 }
4165
4166 switch (request) {
4167 case DP_TEST_LINK_TRAINING:
4168 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4169 response = intel_dp_autotest_link_training(intel_dp);
4170 break;
4171 case DP_TEST_LINK_VIDEO_PATTERN:
4172 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4173 response = intel_dp_autotest_video_pattern(intel_dp);
4174 break;
4175 case DP_TEST_LINK_EDID_READ:
4176 DRM_DEBUG_KMS("EDID test requested\n");
4177 response = intel_dp_autotest_edid(intel_dp);
4178 break;
4179 case DP_TEST_LINK_PHY_TEST_PATTERN:
4180 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4181 response = intel_dp_autotest_phy_pattern(intel_dp);
4182 break;
4183 default:
4184 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4185 break;
4186 }
4187
4188 if (response & DP_TEST_ACK)
4189 intel_dp->compliance.test_type = request;
4190
4191 update_status:
4192 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4193 if (status <= 0)
4194 DRM_DEBUG_KMS("Could not write test response to sink\n");
4195 }
4196
4197 static int
4198 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4199 {
4200 bool bret;
4201
4202 if (intel_dp->is_mst) {
4203 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4204 int ret = 0;
4205 int retry;
4206 bool handled;
4207 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4208 go_again:
4209 if (bret == true) {
4210
4211 /* check link status - esi[10] = 0x200c */
4212 if (intel_dp->active_mst_links &&
4213 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4214 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4215 intel_dp_start_link_train(intel_dp);
4216 intel_dp_stop_link_train(intel_dp);
4217 }
4218
4219 DRM_DEBUG_KMS("got esi %3ph\n", esi);
4220 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4221
4222 if (handled) {
4223 for (retry = 0; retry < 3; retry++) {
4224 int wret;
4225 wret = drm_dp_dpcd_write(&intel_dp->aux,
4226 DP_SINK_COUNT_ESI+1,
4227 &esi[1], 3);
4228 if (wret == 3) {
4229 break;
4230 }
4231 }
4232
4233 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4234 if (bret == true) {
4235 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4236 goto go_again;
4237 }
4238 } else
4239 ret = 0;
4240
4241 return ret;
4242 } else {
4243 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4244 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4245 intel_dp->is_mst = false;
4246 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4247 /* send a hotplug event */
4248 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4249 }
4250 }
4251 return -EINVAL;
4252 }
4253
4254 static void
4255 intel_dp_retrain_link(struct intel_dp *intel_dp)
4256 {
4257 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4258 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4259 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4260
4261 /* Suppress underruns caused by re-training */
4262 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4263 if (crtc->config->has_pch_encoder)
4264 intel_set_pch_fifo_underrun_reporting(dev_priv,
4265 intel_crtc_pch_transcoder(crtc), false);
4266
4267 intel_dp_start_link_train(intel_dp);
4268 intel_dp_stop_link_train(intel_dp);
4269
4270 /* Keep underrun reporting disabled until things are stable */
4271 intel_wait_for_vblank(dev_priv, crtc->pipe);
4272
4273 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4274 if (crtc->config->has_pch_encoder)
4275 intel_set_pch_fifo_underrun_reporting(dev_priv,
4276 intel_crtc_pch_transcoder(crtc), true);
4277 }
4278
4279 static void
4280 intel_dp_check_link_status(struct intel_dp *intel_dp)
4281 {
4282 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4283 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4284 struct drm_connector_state *conn_state =
4285 intel_dp->attached_connector->base.state;
4286 u8 link_status[DP_LINK_STATUS_SIZE];
4287
4288 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4289
4290 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4291 DRM_ERROR("Failed to get link status\n");
4292 return;
4293 }
4294
4295 if (!conn_state->crtc)
4296 return;
4297
4298 WARN_ON(!drm_modeset_is_locked(&conn_state->crtc->mutex));
4299
4300 if (!conn_state->crtc->state->active)
4301 return;
4302
4303 if (conn_state->commit &&
4304 !try_wait_for_completion(&conn_state->commit->hw_done))
4305 return;
4306
4307 /*
4308 * Validate the cached values of intel_dp->link_rate and
4309 * intel_dp->lane_count before attempting to retrain.
4310 */
4311 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4312 intel_dp->lane_count))
4313 return;
4314
4315 /* Retrain if Channel EQ or CR not ok */
4316 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4317 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4318 intel_encoder->base.name);
4319
4320 intel_dp_retrain_link(intel_dp);
4321 }
4322 }
4323
4324 /*
4325 * According to DP spec
4326 * 5.1.2:
4327 * 1. Read DPCD
4328 * 2. Configure link according to Receiver Capabilities
4329 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4330 * 4. Check link status on receipt of hot-plug interrupt
4331 *
4332 * intel_dp_short_pulse - handles short pulse interrupts
4333 * when full detection is not required.
4334 * Returns %true if short pulse is handled and full detection
4335 * is NOT required and %false otherwise.
4336 */
4337 static bool
4338 intel_dp_short_pulse(struct intel_dp *intel_dp)
4339 {
4340 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4341 u8 sink_irq_vector = 0;
4342 u8 old_sink_count = intel_dp->sink_count;
4343 bool ret;
4344
4345 /*
4346 * Clearing compliance test variables to allow capturing
4347 * of values for next automated test request.
4348 */
4349 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4350
4351 /*
4352 * Now read the DPCD to see if it's actually running
4353 * If the current value of sink count doesn't match with
4354 * the value that was stored earlier or dpcd read failed
4355 * we need to do full detection
4356 */
4357 ret = intel_dp_get_dpcd(intel_dp);
4358
4359 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4360 /* No need to proceed if we are going to do full detect */
4361 return false;
4362 }
4363
4364 /* Try to read the source of the interrupt */
4365 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4366 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4367 sink_irq_vector != 0) {
4368 /* Clear interrupt source */
4369 drm_dp_dpcd_writeb(&intel_dp->aux,
4370 DP_DEVICE_SERVICE_IRQ_VECTOR,
4371 sink_irq_vector);
4372
4373 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4374 intel_dp_handle_test_request(intel_dp);
4375 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4376 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4377 }
4378
4379 intel_dp_check_link_status(intel_dp);
4380
4381 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4382 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4383 /* Send a Hotplug Uevent to userspace to start modeset */
4384 drm_kms_helper_hotplug_event(&dev_priv->drm);
4385 }
4386
4387 return true;
4388 }
4389
4390 /* XXX this is probably wrong for multiple downstream ports */
4391 static enum drm_connector_status
4392 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4393 {
4394 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4395 uint8_t *dpcd = intel_dp->dpcd;
4396 uint8_t type;
4397
4398 if (lspcon->active)
4399 lspcon_resume(lspcon);
4400
4401 if (!intel_dp_get_dpcd(intel_dp))
4402 return connector_status_disconnected;
4403
4404 if (intel_dp_is_edp(intel_dp))
4405 return connector_status_connected;
4406
4407 /* if there's no downstream port, we're done */
4408 if (!drm_dp_is_branch(dpcd))
4409 return connector_status_connected;
4410
4411 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4412 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4413 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4414
4415 return intel_dp->sink_count ?
4416 connector_status_connected : connector_status_disconnected;
4417 }
4418
4419 if (intel_dp_can_mst(intel_dp))
4420 return connector_status_connected;
4421
4422 /* If no HPD, poke DDC gently */
4423 if (drm_probe_ddc(&intel_dp->aux.ddc))
4424 return connector_status_connected;
4425
4426 /* Well we tried, say unknown for unreliable port types */
4427 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4428 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4429 if (type == DP_DS_PORT_TYPE_VGA ||
4430 type == DP_DS_PORT_TYPE_NON_EDID)
4431 return connector_status_unknown;
4432 } else {
4433 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4434 DP_DWN_STRM_PORT_TYPE_MASK;
4435 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4436 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4437 return connector_status_unknown;
4438 }
4439
4440 /* Anything else is out of spec, warn and ignore */
4441 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4442 return connector_status_disconnected;
4443 }
4444
4445 static enum drm_connector_status
4446 edp_detect(struct intel_dp *intel_dp)
4447 {
4448 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4449 enum drm_connector_status status;
4450
4451 status = intel_panel_detect(dev_priv);
4452 if (status == connector_status_unknown)
4453 status = connector_status_connected;
4454
4455 return status;
4456 }
4457
4458 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4459 struct intel_digital_port *port)
4460 {
4461 u32 bit;
4462
4463 switch (port->base.port) {
4464 case PORT_B:
4465 bit = SDE_PORTB_HOTPLUG;
4466 break;
4467 case PORT_C:
4468 bit = SDE_PORTC_HOTPLUG;
4469 break;
4470 case PORT_D:
4471 bit = SDE_PORTD_HOTPLUG;
4472 break;
4473 default:
4474 MISSING_CASE(port->base.port);
4475 return false;
4476 }
4477
4478 return I915_READ(SDEISR) & bit;
4479 }
4480
4481 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4482 struct intel_digital_port *port)
4483 {
4484 u32 bit;
4485
4486 switch (port->base.port) {
4487 case PORT_B:
4488 bit = SDE_PORTB_HOTPLUG_CPT;
4489 break;
4490 case PORT_C:
4491 bit = SDE_PORTC_HOTPLUG_CPT;
4492 break;
4493 case PORT_D:
4494 bit = SDE_PORTD_HOTPLUG_CPT;
4495 break;
4496 default:
4497 MISSING_CASE(port->base.port);
4498 return false;
4499 }
4500
4501 return I915_READ(SDEISR) & bit;
4502 }
4503
4504 static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
4505 struct intel_digital_port *port)
4506 {
4507 u32 bit;
4508
4509 switch (port->base.port) {
4510 case PORT_A:
4511 bit = SDE_PORTA_HOTPLUG_SPT;
4512 break;
4513 case PORT_E:
4514 bit = SDE_PORTE_HOTPLUG_SPT;
4515 break;
4516 default:
4517 return cpt_digital_port_connected(dev_priv, port);
4518 }
4519
4520 return I915_READ(SDEISR) & bit;
4521 }
4522
4523 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4524 struct intel_digital_port *port)
4525 {
4526 u32 bit;
4527
4528 switch (port->base.port) {
4529 case PORT_B:
4530 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4531 break;
4532 case PORT_C:
4533 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4534 break;
4535 case PORT_D:
4536 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4537 break;
4538 default:
4539 MISSING_CASE(port->base.port);
4540 return false;
4541 }
4542
4543 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4544 }
4545
4546 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4547 struct intel_digital_port *port)
4548 {
4549 u32 bit;
4550
4551 switch (port->base.port) {
4552 case PORT_B:
4553 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4554 break;
4555 case PORT_C:
4556 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4557 break;
4558 case PORT_D:
4559 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4560 break;
4561 default:
4562 MISSING_CASE(port->base.port);
4563 return false;
4564 }
4565
4566 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4567 }
4568
4569 static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv,
4570 struct intel_digital_port *port)
4571 {
4572 if (port->base.port == PORT_A)
4573 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4574 else
4575 return ibx_digital_port_connected(dev_priv, port);
4576 }
4577
4578 static bool snb_digital_port_connected(struct drm_i915_private *dev_priv,
4579 struct intel_digital_port *port)
4580 {
4581 if (port->base.port == PORT_A)
4582 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4583 else
4584 return cpt_digital_port_connected(dev_priv, port);
4585 }
4586
4587 static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv,
4588 struct intel_digital_port *port)
4589 {
4590 if (port->base.port == PORT_A)
4591 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4592 else
4593 return cpt_digital_port_connected(dev_priv, port);
4594 }
4595
4596 static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv,
4597 struct intel_digital_port *port)
4598 {
4599 if (port->base.port == PORT_A)
4600 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4601 else
4602 return cpt_digital_port_connected(dev_priv, port);
4603 }
4604
4605 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4606 struct intel_digital_port *intel_dig_port)
4607 {
4608 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4609 enum port port;
4610 u32 bit;
4611
4612 port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
4613 switch (port) {
4614 case PORT_A:
4615 bit = BXT_DE_PORT_HP_DDIA;
4616 break;
4617 case PORT_B:
4618 bit = BXT_DE_PORT_HP_DDIB;
4619 break;
4620 case PORT_C:
4621 bit = BXT_DE_PORT_HP_DDIC;
4622 break;
4623 default:
4624 MISSING_CASE(port);
4625 return false;
4626 }
4627
4628 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4629 }
4630
4631 /*
4632 * intel_digital_port_connected - is the specified port connected?
4633 * @dev_priv: i915 private structure
4634 * @port: the port to test
4635 *
4636 * Return %true if @port is connected, %false otherwise.
4637 */
4638 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4639 struct intel_digital_port *port)
4640 {
4641 if (HAS_GMCH_DISPLAY(dev_priv)) {
4642 if (IS_GM45(dev_priv))
4643 return gm45_digital_port_connected(dev_priv, port);
4644 else
4645 return g4x_digital_port_connected(dev_priv, port);
4646 }
4647
4648 if (IS_GEN5(dev_priv))
4649 return ilk_digital_port_connected(dev_priv, port);
4650 else if (IS_GEN6(dev_priv))
4651 return snb_digital_port_connected(dev_priv, port);
4652 else if (IS_GEN7(dev_priv))
4653 return ivb_digital_port_connected(dev_priv, port);
4654 else if (IS_GEN8(dev_priv))
4655 return bdw_digital_port_connected(dev_priv, port);
4656 else if (IS_GEN9_LP(dev_priv))
4657 return bxt_digital_port_connected(dev_priv, port);
4658 else
4659 return spt_digital_port_connected(dev_priv, port);
4660 }
4661
4662 static struct edid *
4663 intel_dp_get_edid(struct intel_dp *intel_dp)
4664 {
4665 struct intel_connector *intel_connector = intel_dp->attached_connector;
4666
4667 /* use cached edid if we have one */
4668 if (intel_connector->edid) {
4669 /* invalid edid */
4670 if (IS_ERR(intel_connector->edid))
4671 return NULL;
4672
4673 return drm_edid_duplicate(intel_connector->edid);
4674 } else
4675 return drm_get_edid(&intel_connector->base,
4676 &intel_dp->aux.ddc);
4677 }
4678
4679 static void
4680 intel_dp_set_edid(struct intel_dp *intel_dp)
4681 {
4682 struct intel_connector *intel_connector = intel_dp->attached_connector;
4683 struct edid *edid;
4684
4685 intel_dp_unset_edid(intel_dp);
4686 edid = intel_dp_get_edid(intel_dp);
4687 intel_connector->detect_edid = edid;
4688
4689 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4690 }
4691
4692 static void
4693 intel_dp_unset_edid(struct intel_dp *intel_dp)
4694 {
4695 struct intel_connector *intel_connector = intel_dp->attached_connector;
4696
4697 kfree(intel_connector->detect_edid);
4698 intel_connector->detect_edid = NULL;
4699
4700 intel_dp->has_audio = false;
4701 }
4702
4703 static int
4704 intel_dp_long_pulse(struct intel_connector *connector)
4705 {
4706 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4707 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
4708 enum drm_connector_status status;
4709 u8 sink_irq_vector = 0;
4710
4711 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4712
4713 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4714
4715 /* Can't disconnect eDP, but you can close the lid... */
4716 if (intel_dp_is_edp(intel_dp))
4717 status = edp_detect(intel_dp);
4718 else if (intel_digital_port_connected(dev_priv,
4719 dp_to_dig_port(intel_dp)))
4720 status = intel_dp_detect_dpcd(intel_dp);
4721 else
4722 status = connector_status_disconnected;
4723
4724 if (status == connector_status_disconnected) {
4725 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4726
4727 if (intel_dp->is_mst) {
4728 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4729 intel_dp->is_mst,
4730 intel_dp->mst_mgr.mst_state);
4731 intel_dp->is_mst = false;
4732 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4733 intel_dp->is_mst);
4734 }
4735
4736 goto out;
4737 }
4738
4739 if (intel_dp->reset_link_params) {
4740 /* Initial max link lane count */
4741 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4742
4743 /* Initial max link rate */
4744 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4745
4746 intel_dp->reset_link_params = false;
4747 }
4748
4749 intel_dp_print_rates(intel_dp);
4750
4751 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4752 drm_dp_is_branch(intel_dp->dpcd));
4753
4754 intel_dp_configure_mst(intel_dp);
4755
4756 if (intel_dp->is_mst) {
4757 /*
4758 * If we are in MST mode then this connector
4759 * won't appear connected or have anything
4760 * with EDID on it
4761 */
4762 status = connector_status_disconnected;
4763 goto out;
4764 } else {
4765 /*
4766 * If display is now connected check links status,
4767 * there has been known issues of link loss triggerring
4768 * long pulse.
4769 *
4770 * Some sinks (eg. ASUS PB287Q) seem to perform some
4771 * weird HPD ping pong during modesets. So we can apparently
4772 * end up with HPD going low during a modeset, and then
4773 * going back up soon after. And once that happens we must
4774 * retrain the link to get a picture. That's in case no
4775 * userspace component reacted to intermittent HPD dip.
4776 */
4777 intel_dp_check_link_status(intel_dp);
4778 }
4779
4780 /*
4781 * Clearing NACK and defer counts to get their exact values
4782 * while reading EDID which are required by Compliance tests
4783 * 4.2.2.4 and 4.2.2.5
4784 */
4785 intel_dp->aux.i2c_nack_count = 0;
4786 intel_dp->aux.i2c_defer_count = 0;
4787
4788 intel_dp_set_edid(intel_dp);
4789 if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
4790 status = connector_status_connected;
4791 intel_dp->detect_done = true;
4792
4793 /* Try to read the source of the interrupt */
4794 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4795 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4796 sink_irq_vector != 0) {
4797 /* Clear interrupt source */
4798 drm_dp_dpcd_writeb(&intel_dp->aux,
4799 DP_DEVICE_SERVICE_IRQ_VECTOR,
4800 sink_irq_vector);
4801
4802 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4803 intel_dp_handle_test_request(intel_dp);
4804 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4805 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4806 }
4807
4808 out:
4809 if (status != connector_status_connected && !intel_dp->is_mst)
4810 intel_dp_unset_edid(intel_dp);
4811
4812 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4813 return status;
4814 }
4815
4816 static int
4817 intel_dp_detect(struct drm_connector *connector,
4818 struct drm_modeset_acquire_ctx *ctx,
4819 bool force)
4820 {
4821 struct intel_dp *intel_dp = intel_attached_dp(connector);
4822 int status = connector->status;
4823
4824 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4825 connector->base.id, connector->name);
4826
4827 /* If full detect is not performed yet, do a full detect */
4828 if (!intel_dp->detect_done) {
4829 struct drm_crtc *crtc;
4830 int ret;
4831
4832 crtc = connector->state->crtc;
4833 if (crtc) {
4834 ret = drm_modeset_lock(&crtc->mutex, ctx);
4835 if (ret)
4836 return ret;
4837 }
4838
4839 status = intel_dp_long_pulse(intel_dp->attached_connector);
4840 }
4841
4842 intel_dp->detect_done = false;
4843
4844 return status;
4845 }
4846
4847 static void
4848 intel_dp_force(struct drm_connector *connector)
4849 {
4850 struct intel_dp *intel_dp = intel_attached_dp(connector);
4851 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4852 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4853
4854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4855 connector->base.id, connector->name);
4856 intel_dp_unset_edid(intel_dp);
4857
4858 if (connector->status != connector_status_connected)
4859 return;
4860
4861 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4862
4863 intel_dp_set_edid(intel_dp);
4864
4865 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4866 }
4867
4868 static int intel_dp_get_modes(struct drm_connector *connector)
4869 {
4870 struct intel_connector *intel_connector = to_intel_connector(connector);
4871 struct edid *edid;
4872
4873 edid = intel_connector->detect_edid;
4874 if (edid) {
4875 int ret = intel_connector_update_modes(connector, edid);
4876 if (ret)
4877 return ret;
4878 }
4879
4880 /* if eDP has no EDID, fall back to fixed mode */
4881 if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4882 intel_connector->panel.fixed_mode) {
4883 struct drm_display_mode *mode;
4884
4885 mode = drm_mode_duplicate(connector->dev,
4886 intel_connector->panel.fixed_mode);
4887 if (mode) {
4888 drm_mode_probed_add(connector, mode);
4889 return 1;
4890 }
4891 }
4892
4893 return 0;
4894 }
4895
4896 static int
4897 intel_dp_connector_register(struct drm_connector *connector)
4898 {
4899 struct intel_dp *intel_dp = intel_attached_dp(connector);
4900 int ret;
4901
4902 ret = intel_connector_register(connector);
4903 if (ret)
4904 return ret;
4905
4906 i915_debugfs_connector_add(connector);
4907
4908 DRM_DEBUG_KMS("registering %s bus for %s\n",
4909 intel_dp->aux.name, connector->kdev->kobj.name);
4910
4911 intel_dp->aux.dev = connector->kdev;
4912 return drm_dp_aux_register(&intel_dp->aux);
4913 }
4914
4915 static void
4916 intel_dp_connector_unregister(struct drm_connector *connector)
4917 {
4918 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4919 intel_connector_unregister(connector);
4920 }
4921
4922 static void
4923 intel_dp_connector_destroy(struct drm_connector *connector)
4924 {
4925 struct intel_connector *intel_connector = to_intel_connector(connector);
4926
4927 kfree(intel_connector->detect_edid);
4928
4929 if (!IS_ERR_OR_NULL(intel_connector->edid))
4930 kfree(intel_connector->edid);
4931
4932 /*
4933 * Can't call intel_dp_is_edp() since the encoder may have been
4934 * destroyed already.
4935 */
4936 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4937 intel_panel_fini(&intel_connector->panel);
4938
4939 drm_connector_cleanup(connector);
4940 kfree(connector);
4941 }
4942
4943 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4944 {
4945 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4946 struct intel_dp *intel_dp = &intel_dig_port->dp;
4947
4948 intel_dp_mst_encoder_cleanup(intel_dig_port);
4949 if (intel_dp_is_edp(intel_dp)) {
4950 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4951 /*
4952 * vdd might still be enabled do to the delayed vdd off.
4953 * Make sure vdd is actually turned off here.
4954 */
4955 pps_lock(intel_dp);
4956 edp_panel_vdd_off_sync(intel_dp);
4957 pps_unlock(intel_dp);
4958
4959 if (intel_dp->edp_notifier.notifier_call) {
4960 unregister_reboot_notifier(&intel_dp->edp_notifier);
4961 intel_dp->edp_notifier.notifier_call = NULL;
4962 }
4963 }
4964
4965 intel_dp_aux_fini(intel_dp);
4966
4967 drm_encoder_cleanup(encoder);
4968 kfree(intel_dig_port);
4969 }
4970
4971 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4972 {
4973 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4974
4975 if (!intel_dp_is_edp(intel_dp))
4976 return;
4977
4978 /*
4979 * vdd might still be enabled do to the delayed vdd off.
4980 * Make sure vdd is actually turned off here.
4981 */
4982 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4983 pps_lock(intel_dp);
4984 edp_panel_vdd_off_sync(intel_dp);
4985 pps_unlock(intel_dp);
4986 }
4987
4988 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4989 {
4990 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4991
4992 lockdep_assert_held(&dev_priv->pps_mutex);
4993
4994 if (!edp_have_panel_vdd(intel_dp))
4995 return;
4996
4997 /*
4998 * The VDD bit needs a power domain reference, so if the bit is
4999 * already enabled when we boot or resume, grab this reference and
5000 * schedule a vdd off, so we don't hold on to the reference
5001 * indefinitely.
5002 */
5003 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5004 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5005
5006 edp_panel_vdd_schedule_off(intel_dp);
5007 }
5008
5009 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5010 {
5011 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5012
5013 if ((intel_dp->DP & DP_PORT_EN) == 0)
5014 return INVALID_PIPE;
5015
5016 if (IS_CHERRYVIEW(dev_priv))
5017 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5018 else
5019 return PORT_TO_PIPE(intel_dp->DP);
5020 }
5021
5022 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5023 {
5024 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5025 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5026 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5027
5028 if (!HAS_DDI(dev_priv))
5029 intel_dp->DP = I915_READ(intel_dp->output_reg);
5030
5031 if (lspcon->active)
5032 lspcon_resume(lspcon);
5033
5034 intel_dp->reset_link_params = true;
5035
5036 pps_lock(intel_dp);
5037
5038 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5039 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5040
5041 if (intel_dp_is_edp(intel_dp)) {
5042 /* Reinit the power sequencer, in case BIOS did something with it. */
5043 intel_dp_pps_init(intel_dp);
5044 intel_edp_panel_vdd_sanitize(intel_dp);
5045 }
5046
5047 pps_unlock(intel_dp);
5048 }
5049
5050 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5051 .force = intel_dp_force,
5052 .fill_modes = drm_helper_probe_single_connector_modes,
5053 .atomic_get_property = intel_digital_connector_atomic_get_property,
5054 .atomic_set_property = intel_digital_connector_atomic_set_property,
5055 .late_register = intel_dp_connector_register,
5056 .early_unregister = intel_dp_connector_unregister,
5057 .destroy = intel_dp_connector_destroy,
5058 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5059 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5060 };
5061
5062 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5063 .detect_ctx = intel_dp_detect,
5064 .get_modes = intel_dp_get_modes,
5065 .mode_valid = intel_dp_mode_valid,
5066 .atomic_check = intel_digital_connector_atomic_check,
5067 };
5068
5069 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5070 .reset = intel_dp_encoder_reset,
5071 .destroy = intel_dp_encoder_destroy,
5072 };
5073
5074 enum irqreturn
5075 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5076 {
5077 struct intel_dp *intel_dp = &intel_dig_port->dp;
5078 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5079 enum irqreturn ret = IRQ_NONE;
5080
5081 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5082 /*
5083 * vdd off can generate a long pulse on eDP which
5084 * would require vdd on to handle it, and thus we
5085 * would end up in an endless cycle of
5086 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5087 */
5088 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5089 port_name(intel_dig_port->base.port));
5090 return IRQ_HANDLED;
5091 }
5092
5093 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5094 port_name(intel_dig_port->base.port),
5095 long_hpd ? "long" : "short");
5096
5097 if (long_hpd) {
5098 intel_dp->reset_link_params = true;
5099 intel_dp->detect_done = false;
5100 return IRQ_NONE;
5101 }
5102
5103 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5104
5105 if (intel_dp->is_mst) {
5106 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5107 /*
5108 * If we were in MST mode, and device is not
5109 * there, get out of MST mode
5110 */
5111 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5112 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5113 intel_dp->is_mst = false;
5114 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5115 intel_dp->is_mst);
5116 intel_dp->detect_done = false;
5117 goto put_power;
5118 }
5119 }
5120
5121 if (!intel_dp->is_mst) {
5122 struct drm_modeset_acquire_ctx ctx;
5123 struct drm_connector *connector = &intel_dp->attached_connector->base;
5124 struct drm_crtc *crtc;
5125 int iret;
5126 bool handled = false;
5127
5128 drm_modeset_acquire_init(&ctx, 0);
5129 retry:
5130 iret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
5131 if (iret)
5132 goto err;
5133
5134 crtc = connector->state->crtc;
5135 if (crtc) {
5136 iret = drm_modeset_lock(&crtc->mutex, &ctx);
5137 if (iret)
5138 goto err;
5139 }
5140
5141 handled = intel_dp_short_pulse(intel_dp);
5142
5143 err:
5144 if (iret == -EDEADLK) {
5145 drm_modeset_backoff(&ctx);
5146 goto retry;
5147 }
5148
5149 drm_modeset_drop_locks(&ctx);
5150 drm_modeset_acquire_fini(&ctx);
5151 WARN(iret, "Acquiring modeset locks failed with %i\n", iret);
5152
5153 if (!handled) {
5154 intel_dp->detect_done = false;
5155 goto put_power;
5156 }
5157 }
5158
5159 ret = IRQ_HANDLED;
5160
5161 put_power:
5162 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5163
5164 return ret;
5165 }
5166
5167 /* check the VBT to see whether the eDP is on another port */
5168 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5169 {
5170 /*
5171 * eDP not supported on g4x. so bail out early just
5172 * for a bit extra safety in case the VBT is bonkers.
5173 */
5174 if (INTEL_GEN(dev_priv) < 5)
5175 return false;
5176
5177 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5178 return true;
5179
5180 return intel_bios_is_port_edp(dev_priv, port);
5181 }
5182
5183 static void
5184 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5185 {
5186 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5187 enum port port = dp_to_dig_port(intel_dp)->base.port;
5188
5189 if (!IS_G4X(dev_priv) && port != PORT_A)
5190 intel_attach_force_audio_property(connector);
5191
5192 intel_attach_broadcast_rgb_property(connector);
5193
5194 if (intel_dp_is_edp(intel_dp)) {
5195 u32 allowed_scalers;
5196
5197 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5198 if (!HAS_GMCH_DISPLAY(dev_priv))
5199 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5200
5201 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5202
5203 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5204
5205 }
5206 }
5207
5208 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5209 {
5210 intel_dp->panel_power_off_time = ktime_get_boottime();
5211 intel_dp->last_power_on = jiffies;
5212 intel_dp->last_backlight_off = jiffies;
5213 }
5214
5215 static void
5216 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5217 {
5218 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5219 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5220 struct pps_registers regs;
5221
5222 intel_pps_get_registers(intel_dp, &regs);
5223
5224 /* Workaround: Need to write PP_CONTROL with the unlock key as
5225 * the very first thing. */
5226 pp_ctl = ironlake_get_pp_control(intel_dp);
5227
5228 pp_on = I915_READ(regs.pp_on);
5229 pp_off = I915_READ(regs.pp_off);
5230 if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
5231 I915_WRITE(regs.pp_ctrl, pp_ctl);
5232 pp_div = I915_READ(regs.pp_div);
5233 }
5234
5235 /* Pull timing values out of registers */
5236 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5237 PANEL_POWER_UP_DELAY_SHIFT;
5238
5239 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5240 PANEL_LIGHT_ON_DELAY_SHIFT;
5241
5242 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5243 PANEL_LIGHT_OFF_DELAY_SHIFT;
5244
5245 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5246 PANEL_POWER_DOWN_DELAY_SHIFT;
5247
5248 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5249 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5250 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5251 } else {
5252 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5253 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5254 }
5255 }
5256
5257 static void
5258 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5259 {
5260 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5261 state_name,
5262 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5263 }
5264
5265 static void
5266 intel_pps_verify_state(struct intel_dp *intel_dp)
5267 {
5268 struct edp_power_seq hw;
5269 struct edp_power_seq *sw = &intel_dp->pps_delays;
5270
5271 intel_pps_readout_hw_state(intel_dp, &hw);
5272
5273 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5274 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5275 DRM_ERROR("PPS state mismatch\n");
5276 intel_pps_dump_state("sw", sw);
5277 intel_pps_dump_state("hw", &hw);
5278 }
5279 }
5280
5281 static void
5282 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5283 {
5284 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5285 struct edp_power_seq cur, vbt, spec,
5286 *final = &intel_dp->pps_delays;
5287
5288 lockdep_assert_held(&dev_priv->pps_mutex);
5289
5290 /* already initialized? */
5291 if (final->t11_t12 != 0)
5292 return;
5293
5294 intel_pps_readout_hw_state(intel_dp, &cur);
5295
5296 intel_pps_dump_state("cur", &cur);
5297
5298 vbt = dev_priv->vbt.edp.pps;
5299 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5300 * of 500ms appears to be too short. Ocassionally the panel
5301 * just fails to power back on. Increasing the delay to 800ms
5302 * seems sufficient to avoid this problem.
5303 */
5304 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5305 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5306 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5307 vbt.t11_t12);
5308 }
5309 /* T11_T12 delay is special and actually in units of 100ms, but zero
5310 * based in the hw (so we need to add 100 ms). But the sw vbt
5311 * table multiplies it with 1000 to make it in units of 100usec,
5312 * too. */
5313 vbt.t11_t12 += 100 * 10;
5314
5315 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5316 * our hw here, which are all in 100usec. */
5317 spec.t1_t3 = 210 * 10;
5318 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5319 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5320 spec.t10 = 500 * 10;
5321 /* This one is special and actually in units of 100ms, but zero
5322 * based in the hw (so we need to add 100 ms). But the sw vbt
5323 * table multiplies it with 1000 to make it in units of 100usec,
5324 * too. */
5325 spec.t11_t12 = (510 + 100) * 10;
5326
5327 intel_pps_dump_state("vbt", &vbt);
5328
5329 /* Use the max of the register settings and vbt. If both are
5330 * unset, fall back to the spec limits. */
5331 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5332 spec.field : \
5333 max(cur.field, vbt.field))
5334 assign_final(t1_t3);
5335 assign_final(t8);
5336 assign_final(t9);
5337 assign_final(t10);
5338 assign_final(t11_t12);
5339 #undef assign_final
5340
5341 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5342 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5343 intel_dp->backlight_on_delay = get_delay(t8);
5344 intel_dp->backlight_off_delay = get_delay(t9);
5345 intel_dp->panel_power_down_delay = get_delay(t10);
5346 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5347 #undef get_delay
5348
5349 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5350 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5351 intel_dp->panel_power_cycle_delay);
5352
5353 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5354 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5355
5356 /*
5357 * We override the HW backlight delays to 1 because we do manual waits
5358 * on them. For T8, even BSpec recommends doing it. For T9, if we
5359 * don't do this, we'll end up waiting for the backlight off delay
5360 * twice: once when we do the manual sleep, and once when we disable
5361 * the panel and wait for the PP_STATUS bit to become zero.
5362 */
5363 final->t8 = 1;
5364 final->t9 = 1;
5365
5366 /*
5367 * HW has only a 100msec granularity for t11_t12 so round it up
5368 * accordingly.
5369 */
5370 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5371 }
5372
5373 static void
5374 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5375 bool force_disable_vdd)
5376 {
5377 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5378 u32 pp_on, pp_off, pp_div, port_sel = 0;
5379 int div = dev_priv->rawclk_freq / 1000;
5380 struct pps_registers regs;
5381 enum port port = dp_to_dig_port(intel_dp)->base.port;
5382 const struct edp_power_seq *seq = &intel_dp->pps_delays;
5383
5384 lockdep_assert_held(&dev_priv->pps_mutex);
5385
5386 intel_pps_get_registers(intel_dp, &regs);
5387
5388 /*
5389 * On some VLV machines the BIOS can leave the VDD
5390 * enabled even on power seqeuencers which aren't
5391 * hooked up to any port. This would mess up the
5392 * power domain tracking the first time we pick
5393 * one of these power sequencers for use since
5394 * edp_panel_vdd_on() would notice that the VDD was
5395 * already on and therefore wouldn't grab the power
5396 * domain reference. Disable VDD first to avoid this.
5397 * This also avoids spuriously turning the VDD on as
5398 * soon as the new power seqeuencer gets initialized.
5399 */
5400 if (force_disable_vdd) {
5401 u32 pp = ironlake_get_pp_control(intel_dp);
5402
5403 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5404
5405 if (pp & EDP_FORCE_VDD)
5406 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5407
5408 pp &= ~EDP_FORCE_VDD;
5409
5410 I915_WRITE(regs.pp_ctrl, pp);
5411 }
5412
5413 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5414 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5415 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5416 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5417 /* Compute the divisor for the pp clock, simply match the Bspec
5418 * formula. */
5419 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5420 pp_div = I915_READ(regs.pp_ctrl);
5421 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5422 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5423 << BXT_POWER_CYCLE_DELAY_SHIFT);
5424 } else {
5425 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5426 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5427 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5428 }
5429
5430 /* Haswell doesn't have any port selection bits for the panel
5431 * power sequencer any more. */
5432 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5433 port_sel = PANEL_PORT_SELECT_VLV(port);
5434 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5435 if (port == PORT_A)
5436 port_sel = PANEL_PORT_SELECT_DPA;
5437 else
5438 port_sel = PANEL_PORT_SELECT_DPD;
5439 }
5440
5441 pp_on |= port_sel;
5442
5443 I915_WRITE(regs.pp_on, pp_on);
5444 I915_WRITE(regs.pp_off, pp_off);
5445 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
5446 I915_WRITE(regs.pp_ctrl, pp_div);
5447 else
5448 I915_WRITE(regs.pp_div, pp_div);
5449
5450 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5451 I915_READ(regs.pp_on),
5452 I915_READ(regs.pp_off),
5453 (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
5454 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5455 I915_READ(regs.pp_div));
5456 }
5457
5458 static void intel_dp_pps_init(struct intel_dp *intel_dp)
5459 {
5460 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5461
5462 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5463 vlv_initial_power_sequencer_setup(intel_dp);
5464 } else {
5465 intel_dp_init_panel_power_sequencer(intel_dp);
5466 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
5467 }
5468 }
5469
5470 /**
5471 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5472 * @dev_priv: i915 device
5473 * @crtc_state: a pointer to the active intel_crtc_state
5474 * @refresh_rate: RR to be programmed
5475 *
5476 * This function gets called when refresh rate (RR) has to be changed from
5477 * one frequency to another. Switches can be between high and low RR
5478 * supported by the panel or to any other RR based on media playback (in
5479 * this case, RR value needs to be passed from user space).
5480 *
5481 * The caller of this function needs to take a lock on dev_priv->drrs.
5482 */
5483 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5484 const struct intel_crtc_state *crtc_state,
5485 int refresh_rate)
5486 {
5487 struct intel_encoder *encoder;
5488 struct intel_digital_port *dig_port = NULL;
5489 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5491 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5492
5493 if (refresh_rate <= 0) {
5494 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5495 return;
5496 }
5497
5498 if (intel_dp == NULL) {
5499 DRM_DEBUG_KMS("DRRS not supported.\n");
5500 return;
5501 }
5502
5503 dig_port = dp_to_dig_port(intel_dp);
5504 encoder = &dig_port->base;
5505
5506 if (!intel_crtc) {
5507 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5508 return;
5509 }
5510
5511 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5512 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5513 return;
5514 }
5515
5516 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5517 refresh_rate)
5518 index = DRRS_LOW_RR;
5519
5520 if (index == dev_priv->drrs.refresh_rate_type) {
5521 DRM_DEBUG_KMS(
5522 "DRRS requested for previously set RR...ignoring\n");
5523 return;
5524 }
5525
5526 if (!crtc_state->base.active) {
5527 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5528 return;
5529 }
5530
5531 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5532 switch (index) {
5533 case DRRS_HIGH_RR:
5534 intel_dp_set_m_n(intel_crtc, M1_N1);
5535 break;
5536 case DRRS_LOW_RR:
5537 intel_dp_set_m_n(intel_crtc, M2_N2);
5538 break;
5539 case DRRS_MAX_RR:
5540 default:
5541 DRM_ERROR("Unsupported refreshrate type\n");
5542 }
5543 } else if (INTEL_GEN(dev_priv) > 6) {
5544 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5545 u32 val;
5546
5547 val = I915_READ(reg);
5548 if (index > DRRS_HIGH_RR) {
5549 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5550 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5551 else
5552 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5553 } else {
5554 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5555 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5556 else
5557 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5558 }
5559 I915_WRITE(reg, val);
5560 }
5561
5562 dev_priv->drrs.refresh_rate_type = index;
5563
5564 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5565 }
5566
5567 /**
5568 * intel_edp_drrs_enable - init drrs struct if supported
5569 * @intel_dp: DP struct
5570 * @crtc_state: A pointer to the active crtc state.
5571 *
5572 * Initializes frontbuffer_bits and drrs.dp
5573 */
5574 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5575 const struct intel_crtc_state *crtc_state)
5576 {
5577 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5578
5579 if (!crtc_state->has_drrs) {
5580 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5581 return;
5582 }
5583
5584 if (dev_priv->psr.enabled) {
5585 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5586 return;
5587 }
5588
5589 mutex_lock(&dev_priv->drrs.mutex);
5590 if (WARN_ON(dev_priv->drrs.dp)) {
5591 DRM_ERROR("DRRS already enabled\n");
5592 goto unlock;
5593 }
5594
5595 dev_priv->drrs.busy_frontbuffer_bits = 0;
5596
5597 dev_priv->drrs.dp = intel_dp;
5598
5599 unlock:
5600 mutex_unlock(&dev_priv->drrs.mutex);
5601 }
5602
5603 /**
5604 * intel_edp_drrs_disable - Disable DRRS
5605 * @intel_dp: DP struct
5606 * @old_crtc_state: Pointer to old crtc_state.
5607 *
5608 */
5609 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5610 const struct intel_crtc_state *old_crtc_state)
5611 {
5612 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5613
5614 if (!old_crtc_state->has_drrs)
5615 return;
5616
5617 mutex_lock(&dev_priv->drrs.mutex);
5618 if (!dev_priv->drrs.dp) {
5619 mutex_unlock(&dev_priv->drrs.mutex);
5620 return;
5621 }
5622
5623 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5624 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5625 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5626
5627 dev_priv->drrs.dp = NULL;
5628 mutex_unlock(&dev_priv->drrs.mutex);
5629
5630 cancel_delayed_work_sync(&dev_priv->drrs.work);
5631 }
5632
5633 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5634 {
5635 struct drm_i915_private *dev_priv =
5636 container_of(work, typeof(*dev_priv), drrs.work.work);
5637 struct intel_dp *intel_dp;
5638
5639 mutex_lock(&dev_priv->drrs.mutex);
5640
5641 intel_dp = dev_priv->drrs.dp;
5642
5643 if (!intel_dp)
5644 goto unlock;
5645
5646 /*
5647 * The delayed work can race with an invalidate hence we need to
5648 * recheck.
5649 */
5650
5651 if (dev_priv->drrs.busy_frontbuffer_bits)
5652 goto unlock;
5653
5654 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5655 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5656
5657 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5658 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5659 }
5660
5661 unlock:
5662 mutex_unlock(&dev_priv->drrs.mutex);
5663 }
5664
5665 /**
5666 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5667 * @dev_priv: i915 device
5668 * @frontbuffer_bits: frontbuffer plane tracking bits
5669 *
5670 * This function gets called everytime rendering on the given planes start.
5671 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5672 *
5673 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5674 */
5675 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5676 unsigned int frontbuffer_bits)
5677 {
5678 struct drm_crtc *crtc;
5679 enum pipe pipe;
5680
5681 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5682 return;
5683
5684 cancel_delayed_work(&dev_priv->drrs.work);
5685
5686 mutex_lock(&dev_priv->drrs.mutex);
5687 if (!dev_priv->drrs.dp) {
5688 mutex_unlock(&dev_priv->drrs.mutex);
5689 return;
5690 }
5691
5692 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5693 pipe = to_intel_crtc(crtc)->pipe;
5694
5695 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5696 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5697
5698 /* invalidate means busy screen hence upclock */
5699 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5700 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5701 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5702
5703 mutex_unlock(&dev_priv->drrs.mutex);
5704 }
5705
5706 /**
5707 * intel_edp_drrs_flush - Restart Idleness DRRS
5708 * @dev_priv: i915 device
5709 * @frontbuffer_bits: frontbuffer plane tracking bits
5710 *
5711 * This function gets called every time rendering on the given planes has
5712 * completed or flip on a crtc is completed. So DRRS should be upclocked
5713 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5714 * if no other planes are dirty.
5715 *
5716 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5717 */
5718 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5719 unsigned int frontbuffer_bits)
5720 {
5721 struct drm_crtc *crtc;
5722 enum pipe pipe;
5723
5724 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5725 return;
5726
5727 cancel_delayed_work(&dev_priv->drrs.work);
5728
5729 mutex_lock(&dev_priv->drrs.mutex);
5730 if (!dev_priv->drrs.dp) {
5731 mutex_unlock(&dev_priv->drrs.mutex);
5732 return;
5733 }
5734
5735 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5736 pipe = to_intel_crtc(crtc)->pipe;
5737
5738 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5739 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5740
5741 /* flush means busy screen hence upclock */
5742 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5743 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5744 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5745
5746 /*
5747 * flush also means no more activity hence schedule downclock, if all
5748 * other fbs are quiescent too
5749 */
5750 if (!dev_priv->drrs.busy_frontbuffer_bits)
5751 schedule_delayed_work(&dev_priv->drrs.work,
5752 msecs_to_jiffies(1000));
5753 mutex_unlock(&dev_priv->drrs.mutex);
5754 }
5755
5756 /**
5757 * DOC: Display Refresh Rate Switching (DRRS)
5758 *
5759 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5760 * which enables swtching between low and high refresh rates,
5761 * dynamically, based on the usage scenario. This feature is applicable
5762 * for internal panels.
5763 *
5764 * Indication that the panel supports DRRS is given by the panel EDID, which
5765 * would list multiple refresh rates for one resolution.
5766 *
5767 * DRRS is of 2 types - static and seamless.
5768 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5769 * (may appear as a blink on screen) and is used in dock-undock scenario.
5770 * Seamless DRRS involves changing RR without any visual effect to the user
5771 * and can be used during normal system usage. This is done by programming
5772 * certain registers.
5773 *
5774 * Support for static/seamless DRRS may be indicated in the VBT based on
5775 * inputs from the panel spec.
5776 *
5777 * DRRS saves power by switching to low RR based on usage scenarios.
5778 *
5779 * The implementation is based on frontbuffer tracking implementation. When
5780 * there is a disturbance on the screen triggered by user activity or a periodic
5781 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5782 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5783 * made.
5784 *
5785 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5786 * and intel_edp_drrs_flush() are called.
5787 *
5788 * DRRS can be further extended to support other internal panels and also
5789 * the scenario of video playback wherein RR is set based on the rate
5790 * requested by userspace.
5791 */
5792
5793 /**
5794 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5795 * @connector: eDP connector
5796 * @fixed_mode: preferred mode of panel
5797 *
5798 * This function is called only once at driver load to initialize basic
5799 * DRRS stuff.
5800 *
5801 * Returns:
5802 * Downclock mode if panel supports it, else return NULL.
5803 * DRRS support is determined by the presence of downclock mode (apart
5804 * from VBT setting).
5805 */
5806 static struct drm_display_mode *
5807 intel_dp_drrs_init(struct intel_connector *connector,
5808 struct drm_display_mode *fixed_mode)
5809 {
5810 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5811 struct drm_display_mode *downclock_mode = NULL;
5812
5813 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5814 mutex_init(&dev_priv->drrs.mutex);
5815
5816 if (INTEL_GEN(dev_priv) <= 6) {
5817 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5818 return NULL;
5819 }
5820
5821 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5822 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5823 return NULL;
5824 }
5825
5826 downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
5827 &connector->base);
5828
5829 if (!downclock_mode) {
5830 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5831 return NULL;
5832 }
5833
5834 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5835
5836 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5837 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5838 return downclock_mode;
5839 }
5840
5841 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5842 struct intel_connector *intel_connector)
5843 {
5844 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5845 struct drm_i915_private *dev_priv = to_i915(dev);
5846 struct drm_connector *connector = &intel_connector->base;
5847 struct drm_display_mode *fixed_mode = NULL;
5848 struct drm_display_mode *alt_fixed_mode = NULL;
5849 struct drm_display_mode *downclock_mode = NULL;
5850 bool has_dpcd;
5851 struct drm_display_mode *scan;
5852 struct edid *edid;
5853 enum pipe pipe = INVALID_PIPE;
5854
5855 if (!intel_dp_is_edp(intel_dp))
5856 return true;
5857
5858 /*
5859 * On IBX/CPT we may get here with LVDS already registered. Since the
5860 * driver uses the only internal power sequencer available for both
5861 * eDP and LVDS bail out early in this case to prevent interfering
5862 * with an already powered-on LVDS power sequencer.
5863 */
5864 if (intel_get_lvds_encoder(&dev_priv->drm)) {
5865 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5866 DRM_INFO("LVDS was detected, not registering eDP\n");
5867
5868 return false;
5869 }
5870
5871 pps_lock(intel_dp);
5872
5873 intel_dp_init_panel_power_timestamps(intel_dp);
5874 intel_dp_pps_init(intel_dp);
5875 intel_edp_panel_vdd_sanitize(intel_dp);
5876
5877 pps_unlock(intel_dp);
5878
5879 /* Cache DPCD and EDID for edp. */
5880 has_dpcd = intel_edp_init_dpcd(intel_dp);
5881
5882 if (!has_dpcd) {
5883 /* if this fails, presume the device is a ghost */
5884 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5885 goto out_vdd_off;
5886 }
5887
5888 mutex_lock(&dev->mode_config.mutex);
5889 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5890 if (edid) {
5891 if (drm_add_edid_modes(connector, edid)) {
5892 drm_mode_connector_update_edid_property(connector,
5893 edid);
5894 } else {
5895 kfree(edid);
5896 edid = ERR_PTR(-EINVAL);
5897 }
5898 } else {
5899 edid = ERR_PTR(-ENOENT);
5900 }
5901 intel_connector->edid = edid;
5902
5903 /* prefer fixed mode from EDID if available, save an alt mode also */
5904 list_for_each_entry(scan, &connector->probed_modes, head) {
5905 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5906 fixed_mode = drm_mode_duplicate(dev, scan);
5907 downclock_mode = intel_dp_drrs_init(
5908 intel_connector, fixed_mode);
5909 } else if (!alt_fixed_mode) {
5910 alt_fixed_mode = drm_mode_duplicate(dev, scan);
5911 }
5912 }
5913
5914 /* fallback to VBT if available for eDP */
5915 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5916 fixed_mode = drm_mode_duplicate(dev,
5917 dev_priv->vbt.lfp_lvds_vbt_mode);
5918 if (fixed_mode) {
5919 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5920 connector->display_info.width_mm = fixed_mode->width_mm;
5921 connector->display_info.height_mm = fixed_mode->height_mm;
5922 }
5923 }
5924 mutex_unlock(&dev->mode_config.mutex);
5925
5926 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5927 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5928 register_reboot_notifier(&intel_dp->edp_notifier);
5929
5930 /*
5931 * Figure out the current pipe for the initial backlight setup.
5932 * If the current pipe isn't valid, try the PPS pipe, and if that
5933 * fails just assume pipe A.
5934 */
5935 pipe = vlv_active_pipe(intel_dp);
5936
5937 if (pipe != PIPE_A && pipe != PIPE_B)
5938 pipe = intel_dp->pps_pipe;
5939
5940 if (pipe != PIPE_A && pipe != PIPE_B)
5941 pipe = PIPE_A;
5942
5943 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5944 pipe_name(pipe));
5945 }
5946
5947 intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
5948 downclock_mode);
5949 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5950 intel_panel_setup_backlight(connector, pipe);
5951
5952 return true;
5953
5954 out_vdd_off:
5955 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5956 /*
5957 * vdd might still be enabled do to the delayed vdd off.
5958 * Make sure vdd is actually turned off here.
5959 */
5960 pps_lock(intel_dp);
5961 edp_panel_vdd_off_sync(intel_dp);
5962 pps_unlock(intel_dp);
5963
5964 return false;
5965 }
5966
5967 /* Set up the hotplug pin and aux power domain. */
5968 static void
5969 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5970 {
5971 struct intel_encoder *encoder = &intel_dig_port->base;
5972 struct intel_dp *intel_dp = &intel_dig_port->dp;
5973
5974 encoder->hpd_pin = intel_hpd_pin(encoder->port);
5975
5976 switch (encoder->port) {
5977 case PORT_A:
5978 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5979 break;
5980 case PORT_B:
5981 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5982 break;
5983 case PORT_C:
5984 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5985 break;
5986 case PORT_D:
5987 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5988 break;
5989 case PORT_E:
5990 /* FIXME: Check VBT for actual wiring of PORT E */
5991 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5992 break;
5993 default:
5994 MISSING_CASE(encoder->port);
5995 }
5996 }
5997
5998 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5999 {
6000 struct intel_connector *intel_connector;
6001 struct drm_connector *connector;
6002
6003 intel_connector = container_of(work, typeof(*intel_connector),
6004 modeset_retry_work);
6005 connector = &intel_connector->base;
6006 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6007 connector->name);
6008
6009 /* Grab the locks before changing connector property*/
6010 mutex_lock(&connector->dev->mode_config.mutex);
6011 /* Set connector link status to BAD and send a Uevent to notify
6012 * userspace to do a modeset.
6013 */
6014 drm_mode_connector_set_link_status_property(connector,
6015 DRM_MODE_LINK_STATUS_BAD);
6016 mutex_unlock(&connector->dev->mode_config.mutex);
6017 /* Send Hotplug uevent so userspace can reprobe */
6018 drm_kms_helper_hotplug_event(connector->dev);
6019 }
6020
6021 bool
6022 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6023 struct intel_connector *intel_connector)
6024 {
6025 struct drm_connector *connector = &intel_connector->base;
6026 struct intel_dp *intel_dp = &intel_dig_port->dp;
6027 struct intel_encoder *intel_encoder = &intel_dig_port->base;
6028 struct drm_device *dev = intel_encoder->base.dev;
6029 struct drm_i915_private *dev_priv = to_i915(dev);
6030 enum port port = intel_encoder->port;
6031 int type;
6032
6033 /* Initialize the work for modeset in case of link train failure */
6034 INIT_WORK(&intel_connector->modeset_retry_work,
6035 intel_dp_modeset_retry_work_fn);
6036
6037 if (WARN(intel_dig_port->max_lanes < 1,
6038 "Not enough lanes (%d) for DP on port %c\n",
6039 intel_dig_port->max_lanes, port_name(port)))
6040 return false;
6041
6042 intel_dp_set_source_rates(intel_dp);
6043
6044 intel_dp->reset_link_params = true;
6045 intel_dp->pps_pipe = INVALID_PIPE;
6046 intel_dp->active_pipe = INVALID_PIPE;
6047
6048 /* intel_dp vfuncs */
6049 if (INTEL_GEN(dev_priv) >= 9)
6050 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6051 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6052 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6053 else if (HAS_PCH_SPLIT(dev_priv))
6054 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6055 else
6056 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
6057
6058 if (INTEL_GEN(dev_priv) >= 9)
6059 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6060 else
6061 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
6062
6063 if (HAS_DDI(dev_priv))
6064 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6065
6066 /* Preserve the current hw state. */
6067 intel_dp->DP = I915_READ(intel_dp->output_reg);
6068 intel_dp->attached_connector = intel_connector;
6069
6070 if (intel_dp_is_port_edp(dev_priv, port))
6071 type = DRM_MODE_CONNECTOR_eDP;
6072 else
6073 type = DRM_MODE_CONNECTOR_DisplayPort;
6074
6075 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6076 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6077
6078 /*
6079 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6080 * for DP the encoder type can be set by the caller to
6081 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6082 */
6083 if (type == DRM_MODE_CONNECTOR_eDP)
6084 intel_encoder->type = INTEL_OUTPUT_EDP;
6085
6086 /* eDP only on port B and/or C on vlv/chv */
6087 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6088 intel_dp_is_edp(intel_dp) &&
6089 port != PORT_B && port != PORT_C))
6090 return false;
6091
6092 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6093 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6094 port_name(port));
6095
6096 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6097 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6098
6099 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6100 connector->interlace_allowed = true;
6101 connector->doublescan_allowed = 0;
6102
6103 intel_dp_init_connector_port_info(intel_dig_port);
6104
6105 intel_dp_aux_init(intel_dp);
6106
6107 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6108 edp_panel_vdd_work);
6109
6110 intel_connector_attach_encoder(intel_connector, intel_encoder);
6111
6112 if (HAS_DDI(dev_priv))
6113 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6114 else
6115 intel_connector->get_hw_state = intel_connector_get_hw_state;
6116
6117 /* init MST on ports that can support it */
6118 if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6119 (port == PORT_B || port == PORT_C || port == PORT_D))
6120 intel_dp_mst_encoder_init(intel_dig_port,
6121 intel_connector->base.base.id);
6122
6123 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6124 intel_dp_aux_fini(intel_dp);
6125 intel_dp_mst_encoder_cleanup(intel_dig_port);
6126 goto fail;
6127 }
6128
6129 intel_dp_add_properties(intel_dp, connector);
6130
6131 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6132 * 0xd. Failure to do so will result in spurious interrupts being
6133 * generated on the port when a cable is not attached.
6134 */
6135 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6136 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6137 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6138 }
6139
6140 return true;
6141
6142 fail:
6143 drm_connector_cleanup(connector);
6144
6145 return false;
6146 }
6147
6148 bool intel_dp_init(struct drm_i915_private *dev_priv,
6149 i915_reg_t output_reg,
6150 enum port port)
6151 {
6152 struct intel_digital_port *intel_dig_port;
6153 struct intel_encoder *intel_encoder;
6154 struct drm_encoder *encoder;
6155 struct intel_connector *intel_connector;
6156
6157 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6158 if (!intel_dig_port)
6159 return false;
6160
6161 intel_connector = intel_connector_alloc();
6162 if (!intel_connector)
6163 goto err_connector_alloc;
6164
6165 intel_encoder = &intel_dig_port->base;
6166 encoder = &intel_encoder->base;
6167
6168 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6169 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6170 "DP %c", port_name(port)))
6171 goto err_encoder_init;
6172
6173 intel_encoder->compute_config = intel_dp_compute_config;
6174 intel_encoder->get_hw_state = intel_dp_get_hw_state;
6175 intel_encoder->get_config = intel_dp_get_config;
6176 intel_encoder->suspend = intel_dp_encoder_suspend;
6177 if (IS_CHERRYVIEW(dev_priv)) {
6178 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6179 intel_encoder->pre_enable = chv_pre_enable_dp;
6180 intel_encoder->enable = vlv_enable_dp;
6181 intel_encoder->disable = vlv_disable_dp;
6182 intel_encoder->post_disable = chv_post_disable_dp;
6183 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6184 } else if (IS_VALLEYVIEW(dev_priv)) {
6185 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6186 intel_encoder->pre_enable = vlv_pre_enable_dp;
6187 intel_encoder->enable = vlv_enable_dp;
6188 intel_encoder->disable = vlv_disable_dp;
6189 intel_encoder->post_disable = vlv_post_disable_dp;
6190 } else if (INTEL_GEN(dev_priv) >= 5) {
6191 intel_encoder->pre_enable = g4x_pre_enable_dp;
6192 intel_encoder->enable = g4x_enable_dp;
6193 intel_encoder->disable = ilk_disable_dp;
6194 intel_encoder->post_disable = ilk_post_disable_dp;
6195 } else {
6196 intel_encoder->pre_enable = g4x_pre_enable_dp;
6197 intel_encoder->enable = g4x_enable_dp;
6198 intel_encoder->disable = g4x_disable_dp;
6199 }
6200
6201 intel_dig_port->dp.output_reg = output_reg;
6202 intel_dig_port->max_lanes = 4;
6203
6204 intel_encoder->type = INTEL_OUTPUT_DP;
6205 intel_encoder->power_domain = intel_port_to_power_domain(port);
6206 if (IS_CHERRYVIEW(dev_priv)) {
6207 if (port == PORT_D)
6208 intel_encoder->crtc_mask = 1 << 2;
6209 else
6210 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6211 } else {
6212 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6213 }
6214 intel_encoder->cloneable = 0;
6215 intel_encoder->port = port;
6216
6217 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6218 dev_priv->hotplug.irq_port[port] = intel_dig_port;
6219
6220 if (port != PORT_A)
6221 intel_infoframe_init(intel_dig_port);
6222
6223 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6224 goto err_init_connector;
6225
6226 return true;
6227
6228 err_init_connector:
6229 drm_encoder_cleanup(encoder);
6230 err_encoder_init:
6231 kfree(intel_connector);
6232 err_connector_alloc:
6233 kfree(intel_dig_port);
6234 return false;
6235 }
6236
6237 void intel_dp_mst_suspend(struct drm_device *dev)
6238 {
6239 struct drm_i915_private *dev_priv = to_i915(dev);
6240 int i;
6241
6242 /* disable MST */
6243 for (i = 0; i < I915_MAX_PORTS; i++) {
6244 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6245
6246 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6247 continue;
6248
6249 if (intel_dig_port->dp.is_mst)
6250 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6251 }
6252 }
6253
6254 void intel_dp_mst_resume(struct drm_device *dev)
6255 {
6256 struct drm_i915_private *dev_priv = to_i915(dev);
6257 int i;
6258
6259 for (i = 0; i < I915_MAX_PORTS; i++) {
6260 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6261 int ret;
6262
6263 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6264 continue;
6265
6266 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6267 if (ret)
6268 intel_dp_check_mst_status(&intel_dig_port->dp);
6269 }
6270 }
CRIS linux kernel tree