drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include <linux/export.h>
  32 #include <drm/drmP.h>
  33 #include "intel_drv.h"
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36
  37 struct gmbus_pin {
  38         const char *name;
  39         i915_reg_t reg;
  40 };
  41
  42 /* Map gmbus pin pairs to names and registers. */
  43 static const struct gmbus_pin gmbus_pins[] = {
  44         [GMBUS_PIN_SSC] = { "ssc", GPIOB },
  45         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  46         [GMBUS_PIN_PANEL] = { "panel", GPIOC },
  47         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  48         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  49         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  50 };
  51
  52 static const struct gmbus_pin gmbus_pins_bdw[] = {
  53         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  54         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  55         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  56         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  57 };
  58
  59 static const struct gmbus_pin gmbus_pins_skl[] = {
  60         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  61         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  62         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  63 };
  64
  65 static const struct gmbus_pin gmbus_pins_bxt[] = {
  66         [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
  67         [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
  68         [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
  69 };
  70
  71 static const struct gmbus_pin gmbus_pins_cnp[] = {
  72         [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
  73         [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
  74         [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
  75         [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
  76 };
  77
  78 /* pin is expected to be valid */
  79 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
  80                                              unsigned int pin)
  81 {
  82         if (HAS_PCH_CNP(dev_priv))
  83                 return &gmbus_pins_cnp[pin];
  84         else if (IS_GEN9_LP(dev_priv))
  85                 return &gmbus_pins_bxt[pin];
  86         else if (IS_GEN9_BC(dev_priv))
  87                 return &gmbus_pins_skl[pin];
  88         else if (IS_BROADWELL(dev_priv))
  89                 return &gmbus_pins_bdw[pin];
  90         else
  91                 return &gmbus_pins[pin];
  92 }
  93
  94 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
  95                               unsigned int pin)
  96 {
  97         unsigned int size;
  98
  99         if (HAS_PCH_CNP(dev_priv))
 100                 size = ARRAY_SIZE(gmbus_pins_cnp);
 101         else if (IS_GEN9_LP(dev_priv))
 102                 size = ARRAY_SIZE(gmbus_pins_bxt);
 103         else if (IS_GEN9_BC(dev_priv))
 104                 size = ARRAY_SIZE(gmbus_pins_skl);
 105         else if (IS_BROADWELL(dev_priv))
 106                 size = ARRAY_SIZE(gmbus_pins_bdw);
 107         else
 108                 size = ARRAY_SIZE(gmbus_pins);
 109
 110         return pin < size &&
 111                 i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
 112 }
 113
 114 /* Intel GPIO access functions */
 115
 116 #define I2C_RISEFALL_TIME 10
 117
 118 static inline struct intel_gmbus *
 119 to_intel_gmbus(struct i2c_adapter *i2c)
 120 {
 121         return container_of(i2c, struct intel_gmbus, adapter);
 122 }
 123
 124 void
 125 intel_i2c_reset(struct drm_i915_private *dev_priv)
 126 {
 127         I915_WRITE(GMBUS0, 0);
 128         I915_WRITE(GMBUS4, 0);
 129 }
 130
 131 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 132                                    bool enable)
 133 {
 134         u32 val;
 135
 136         /* When using bit bashing for I2C, this bit needs to be set to 1 */
 137         val = I915_READ(DSPCLK_GATE_D);
 138         if (!enable)
 139                 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
 140         else
 141                 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
 142         I915_WRITE(DSPCLK_GATE_D, val);
 143 }
 144
 145 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 146                                    bool enable)
 147 {
 148         u32 val;
 149
 150         val = I915_READ(SOUTH_DSPCLK_GATE_D);
 151         if (!enable)
 152                 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
 153         else
 154                 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
 155         I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
 156 }
 157
 158 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 159                                    bool enable)
 160 {
 161         u32 val;
 162
 163         val = I915_READ(GEN9_CLKGATE_DIS_4);
 164         if (!enable)
 165                 val |= BXT_GMBUS_GATING_DIS;
 166         else
 167                 val &= ~BXT_GMBUS_GATING_DIS;
 168         I915_WRITE(GEN9_CLKGATE_DIS_4, val);
 169 }
 170
 171 static u32 get_reserved(struct intel_gmbus *bus)
 172 {
 173         struct drm_i915_private *dev_priv = bus->dev_priv;
 174         u32 reserved = 0;
 175
 176         /* On most chips, these bits must be preserved in software. */
 177         if (!IS_I830(dev_priv) && !IS_I845G(dev_priv))
 178                 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
 179                                              (GPIO_DATA_PULLUP_DISABLE |
 180                                               GPIO_CLOCK_PULLUP_DISABLE);
 181
 182         return reserved;
 183 }
 184
 185 static int get_clock(void *data)
 186 {
 187         struct intel_gmbus *bus = data;
 188         struct drm_i915_private *dev_priv = bus->dev_priv;
 189         u32 reserved = get_reserved(bus);
 190         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
 191         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 192         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
 193 }
 194
 195 static int get_data(void *data)
 196 {
 197         struct intel_gmbus *bus = data;
 198         struct drm_i915_private *dev_priv = bus->dev_priv;
 199         u32 reserved = get_reserved(bus);
 200         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
 201         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 202         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
 203 }
 204
 205 static void set_clock(void *data, int state_high)
 206 {
 207         struct intel_gmbus *bus = data;
 208         struct drm_i915_private *dev_priv = bus->dev_priv;
 209         u32 reserved = get_reserved(bus);
 210         u32 clock_bits;
 211
 212         if (state_high)
 213                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 214         else
 215                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 216                         GPIO_CLOCK_VAL_MASK;
 217
 218         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
 219         POSTING_READ(bus->gpio_reg);
 220 }
 221
 222 static void set_data(void *data, int state_high)
 223 {
 224         struct intel_gmbus *bus = data;
 225         struct drm_i915_private *dev_priv = bus->dev_priv;
 226         u32 reserved = get_reserved(bus);
 227         u32 data_bits;
 228
 229         if (state_high)
 230                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 231         else
 232                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 233                         GPIO_DATA_VAL_MASK;
 234
 235         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
 236         POSTING_READ(bus->gpio_reg);
 237 }
 238
 239 static int
 240 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 241 {
 242         struct intel_gmbus *bus = container_of(adapter,
 243                                                struct intel_gmbus,
 244                                                adapter);
 245         struct drm_i915_private *dev_priv = bus->dev_priv;
 246
 247         intel_i2c_reset(dev_priv);
 248
 249         if (IS_PINEVIEW(dev_priv))
 250                 pnv_gmbus_clock_gating(dev_priv, false);
 251
 252         set_data(bus, 1);
 253         set_clock(bus, 1);
 254         udelay(I2C_RISEFALL_TIME);
 255         return 0;
 256 }
 257
 258 static void
 259 intel_gpio_post_xfer(struct i2c_adapter *adapter)
 260 {
 261         struct intel_gmbus *bus = container_of(adapter,
 262                                                struct intel_gmbus,
 263                                                adapter);
 264         struct drm_i915_private *dev_priv = bus->dev_priv;
 265
 266         set_data(bus, 1);
 267         set_clock(bus, 1);
 268
 269         if (IS_PINEVIEW(dev_priv))
 270                 pnv_gmbus_clock_gating(dev_priv, true);
 271 }
 272
 273 static void
 274 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
 275 {
 276         struct drm_i915_private *dev_priv = bus->dev_priv;
 277         struct i2c_algo_bit_data *algo;
 278
 279         algo = &bus->bit_algo;
 280
 281         bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
 282                               i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
 283         bus->adapter.algo_data = algo;
 284         algo->setsda = set_data;
 285         algo->setscl = set_clock;
 286         algo->getsda = get_data;
 287         algo->getscl = get_clock;
 288         algo->pre_xfer = intel_gpio_pre_xfer;
 289         algo->post_xfer = intel_gpio_post_xfer;
 290         algo->udelay = I2C_RISEFALL_TIME;
 291         algo->timeout = usecs_to_jiffies(2200);
 292         algo->data = bus;
 293 }
 294
 295 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
 296 {
 297         DEFINE_WAIT(wait);
 298         u32 gmbus2;
 299         int ret;
 300
 301         /* Important: The hw handles only the first bit, so set only one! Since
 302          * we also need to check for NAKs besides the hw ready/idle signal, we
 303          * need to wake up periodically and check that ourselves.
 304          */
 305         if (!HAS_GMBUS_IRQ(dev_priv))
 306                 irq_en = 0;
 307
 308         add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 309         I915_WRITE_FW(GMBUS4, irq_en);
 310
 311         status |= GMBUS_SATOER;
 312         ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
 313         if (ret)
 314                 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
 315
 316         I915_WRITE_FW(GMBUS4, 0);
 317         remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 318
 319         if (gmbus2 & GMBUS_SATOER)
 320                 return -ENXIO;
 321
 322         return ret;
 323 }
 324
 325 static int
 326 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 327 {
 328         DEFINE_WAIT(wait);
 329         u32 irq_enable;
 330         int ret;
 331
 332         /* Important: The hw handles only the first bit, so set only one! */
 333         irq_enable = 0;
 334         if (HAS_GMBUS_IRQ(dev_priv))
 335                 irq_enable = GMBUS_IDLE_EN;
 336
 337         add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 338         I915_WRITE_FW(GMBUS4, irq_enable);
 339
 340         ret = intel_wait_for_register_fw(dev_priv,
 341                                          GMBUS2, GMBUS_ACTIVE, 0,
 342                                          10);
 343
 344         I915_WRITE_FW(GMBUS4, 0);
 345         remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 346
 347         return ret;
 348 }
 349
 350 static int
 351 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 352                       unsigned short addr, u8 *buf, unsigned int len,
 353                       u32 gmbus1_index)
 354 {
 355         I915_WRITE_FW(GMBUS1,
 356                       gmbus1_index |
 357                       GMBUS_CYCLE_WAIT |
 358                       (len << GMBUS_BYTE_COUNT_SHIFT) |
 359                       (addr << GMBUS_SLAVE_ADDR_SHIFT) |
 360                       GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 361         while (len) {
 362                 int ret;
 363                 u32 val, loop = 0;
 364
 365                 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
 366                 if (ret)
 367                         return ret;
 368
 369                 val = I915_READ_FW(GMBUS3);
 370                 do {
 371                         *buf++ = val & 0xff;
 372                         val >>= 8;
 373                 } while (--len && ++loop < 4);
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int
 380 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 381                 u32 gmbus1_index)
 382 {
 383         u8 *buf = msg->buf;
 384         unsigned int rx_size = msg->len;
 385         unsigned int len;
 386         int ret;
 387
 388         do {
 389                 len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
 390
 391                 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
 392                                             buf, len, gmbus1_index);
 393                 if (ret)
 394                         return ret;
 395
 396                 rx_size -= len;
 397                 buf += len;
 398         } while (rx_size != 0);
 399
 400         return 0;
 401 }
 402
 403 static int
 404 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
 405                        unsigned short addr, u8 *buf, unsigned int len)
 406 {
 407         unsigned int chunk_size = len;
 408         u32 val, loop;
 409
 410         val = loop = 0;
 411         while (len && loop < 4) {
 412                 val |= *buf++ << (8 * loop++);
 413                 len -= 1;
 414         }
 415
 416         I915_WRITE_FW(GMBUS3, val);
 417         I915_WRITE_FW(GMBUS1,
 418                       GMBUS_CYCLE_WAIT |
 419                       (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
 420                       (addr << GMBUS_SLAVE_ADDR_SHIFT) |
 421                       GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 422         while (len) {
 423                 int ret;
 424
 425                 val = loop = 0;
 426                 do {
 427                         val |= *buf++ << (8 * loop);
 428                 } while (--len && ++loop < 4);
 429
 430                 I915_WRITE_FW(GMBUS3, val);
 431
 432                 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
 433                 if (ret)
 434                         return ret;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static int
 441 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
 442 {
 443         u8 *buf = msg->buf;
 444         unsigned int tx_size = msg->len;
 445         unsigned int len;
 446         int ret;
 447
 448         do {
 449                 len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
 450
 451                 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
 452                 if (ret)
 453                         return ret;
 454
 455                 buf += len;
 456                 tx_size -= len;
 457         } while (tx_size != 0);
 458
 459         return 0;
 460 }
 461
 462 /*
 463  * The gmbus controller can combine a 1 or 2 byte write with a read that
 464  * immediately follows it by using an "INDEX" cycle.
 465  */
 466 static bool
 467 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
 468 {
 469         return (i + 1 < num &&
 470                 msgs[i].addr == msgs[i + 1].addr &&
 471                 !(msgs[i].flags & I2C_M_RD) &&
 472                 (msgs[i].len == 1 || msgs[i].len == 2) &&
 473                 (msgs[i + 1].flags & I2C_M_RD));
 474 }
 475
 476 static int
 477 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 478 {
 479         u32 gmbus1_index = 0;
 480         u32 gmbus5 = 0;
 481         int ret;
 482
 483         if (msgs[0].len == 2)
 484                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
 485                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
 486         if (msgs[0].len == 1)
 487                 gmbus1_index = GMBUS_CYCLE_INDEX |
 488                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 489
 490         /* GMBUS5 holds 16-bit index */
 491         if (gmbus5)
 492                 I915_WRITE_FW(GMBUS5, gmbus5);
 493
 494         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
 495
 496         /* Clear GMBUS5 after each index transfer */
 497         if (gmbus5)
 498                 I915_WRITE_FW(GMBUS5, 0);
 499
 500         return ret;
 501 }
 502
 503 static int
 504 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 505 {
 506         struct intel_gmbus *bus = container_of(adapter,
 507                                                struct intel_gmbus,
 508                                                adapter);
 509         struct drm_i915_private *dev_priv = bus->dev_priv;
 510         int i = 0, inc, try = 0;
 511         int ret = 0;
 512
 513         /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
 514         if (IS_GEN9_LP(dev_priv))
 515                 bxt_gmbus_clock_gating(dev_priv, false);
 516         else if (HAS_PCH_SPT(dev_priv) ||
 517                  HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
 518                 pch_gmbus_clock_gating(dev_priv, false);
 519
 520 retry:
 521         I915_WRITE_FW(GMBUS0, bus->reg0);
 522
 523         for (; i < num; i += inc) {
 524                 inc = 1;
 525                 if (gmbus_is_index_read(msgs, i, num)) {
 526                         ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
 527                         inc = 2; /* an index read is two msgs */
 528                 } else if (msgs[i].flags & I2C_M_RD) {
 529                         ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
 530                 } else {
 531                         ret = gmbus_xfer_write(dev_priv, &msgs[i]);
 532                 }
 533
 534                 if (!ret)
 535                         ret = gmbus_wait(dev_priv,
 536                                          GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
 537                 if (ret == -ETIMEDOUT)
 538                         goto timeout;
 539                 else if (ret)
 540                         goto clear_err;
 541         }
 542
 543         /* Generate a STOP condition on the bus. Note that gmbus can't generata
 544          * a STOP on the very first cycle. To simplify the code we
 545          * unconditionally generate the STOP condition with an additional gmbus
 546          * cycle. */
 547         I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 548
 549         /* Mark the GMBUS interface as disabled after waiting for idle.
 550          * We will re-enable it at the start of the next xfer,
 551          * till then let it sleep.
 552          */
 553         if (gmbus_wait_idle(dev_priv)) {
 554                 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
 555                          adapter->name);
 556                 ret = -ETIMEDOUT;
 557         }
 558         I915_WRITE_FW(GMBUS0, 0);
 559         ret = ret ?: i;
 560         goto out;
 561
 562 clear_err:
 563         /*
 564          * Wait for bus to IDLE before clearing NAK.
 565          * If we clear the NAK while bus is still active, then it will stay
 566          * active and the next transaction may fail.
 567          *
 568          * If no ACK is received during the address phase of a transaction, the
 569          * adapter must report -ENXIO. It is not clear what to return if no ACK
 570          * is received at other times. But we have to be careful to not return
 571          * spurious -ENXIO because that will prevent i2c and drm edid functions
 572          * from retrying. So return -ENXIO only when gmbus properly quiescents -
 573          * timing out seems to happen when there _is_ a ddc chip present, but
 574          * it's slow responding and only answers on the 2nd retry.
 575          */
 576         ret = -ENXIO;
 577         if (gmbus_wait_idle(dev_priv)) {
 578                 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
 579                               adapter->name);
 580                 ret = -ETIMEDOUT;
 581         }
 582
 583         /* Toggle the Software Clear Interrupt bit. This has the effect
 584          * of resetting the GMBUS controller and so clearing the
 585          * BUS_ERROR raised by the slave's NAK.
 586          */
 587         I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
 588         I915_WRITE_FW(GMBUS1, 0);
 589         I915_WRITE_FW(GMBUS0, 0);
 590
 591         DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 592                          adapter->name, msgs[i].addr,
 593                          (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 594
 595         /*
 596          * Passive adapters sometimes NAK the first probe. Retry the first
 597          * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
 598          * has retries internally. See also the retry loop in
 599          * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
 600          */
 601         if (ret == -ENXIO && i == 0 && try++ == 0) {
 602                 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
 603                               adapter->name);
 604                 goto retry;
 605         }
 606
 607         goto out;
 608
 609 timeout:
 610         DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 611                       bus->adapter.name, bus->reg0 & 0xff);
 612         I915_WRITE_FW(GMBUS0, 0);
 613
 614         /*
 615          * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
 616          * instead. Use EAGAIN to have i2c core retry.
 617          */
 618         ret = -EAGAIN;
 619
 620 out:
 621         /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
 622         if (IS_GEN9_LP(dev_priv))
 623                 bxt_gmbus_clock_gating(dev_priv, true);
 624         else if (HAS_PCH_SPT(dev_priv) ||
 625                  HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
 626                 pch_gmbus_clock_gating(dev_priv, true);
 627
 628         return ret;
 629 }
 630
 631 static int
 632 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 633 {
 634         struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
 635                                                adapter);
 636         struct drm_i915_private *dev_priv = bus->dev_priv;
 637         int ret;
 638
 639         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 640
 641         if (bus->force_bit) {
 642                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 643                 if (ret < 0)
 644                         bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
 645         } else {
 646                 ret = do_gmbus_xfer(adapter, msgs, num);
 647                 if (ret == -EAGAIN)
 648                         bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
 649         }
 650
 651         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
 652
 653         return ret;
 654 }
 655
 656 static u32 gmbus_func(struct i2c_adapter *adapter)
 657 {
 658         return i2c_bit_algo.functionality(adapter) &
 659                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 660                 /* I2C_FUNC_10BIT_ADDR | */
 661                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 662                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 663 }
 664
 665 static const struct i2c_algorithm gmbus_algorithm = {
 666         .master_xfer    = gmbus_xfer,
 667         .functionality  = gmbus_func
 668 };
 669
 670 static void gmbus_lock_bus(struct i2c_adapter *adapter,
 671                            unsigned int flags)
 672 {
 673         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 674         struct drm_i915_private *dev_priv = bus->dev_priv;
 675
 676         mutex_lock(&dev_priv->gmbus_mutex);
 677 }
 678
 679 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
 680                              unsigned int flags)
 681 {
 682         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 683         struct drm_i915_private *dev_priv = bus->dev_priv;
 684
 685         return mutex_trylock(&dev_priv->gmbus_mutex);
 686 }
 687
 688 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
 689                              unsigned int flags)
 690 {
 691         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 692         struct drm_i915_private *dev_priv = bus->dev_priv;
 693
 694         mutex_unlock(&dev_priv->gmbus_mutex);
 695 }
 696
 697 static const struct i2c_lock_operations gmbus_lock_ops = {
 698         .lock_bus =    gmbus_lock_bus,
 699         .trylock_bus = gmbus_trylock_bus,
 700         .unlock_bus =  gmbus_unlock_bus,
 701 };
 702
 703 /**
 704  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 705  * @dev_priv: i915 device private
 706  */
 707 int intel_setup_gmbus(struct drm_i915_private *dev_priv)
 708 {
 709         struct pci_dev *pdev = dev_priv->drm.pdev;
 710         struct intel_gmbus *bus;
 711         unsigned int pin;
 712         int ret;
 713
 714         if (HAS_PCH_NOP(dev_priv))
 715                 return 0;
 716
 717         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 718                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 719         else if (!HAS_GMCH_DISPLAY(dev_priv))
 720                 dev_priv->gpio_mmio_base =
 721                         i915_mmio_reg_offset(PCH_GPIOA) -
 722                         i915_mmio_reg_offset(GPIOA);
 723
 724         mutex_init(&dev_priv->gmbus_mutex);
 725         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
 726
 727         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
 728                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 729                         continue;
 730
 731                 bus = &dev_priv->gmbus[pin];
 732
 733                 bus->adapter.owner = THIS_MODULE;
 734                 bus->adapter.class = I2C_CLASS_DDC;
 735                 snprintf(bus->adapter.name,
 736                          sizeof(bus->adapter.name),
 737                          "i915 gmbus %s",
 738                          get_gmbus_pin(dev_priv, pin)->name);
 739
 740                 bus->adapter.dev.parent = &pdev->dev;
 741                 bus->dev_priv = dev_priv;
 742
 743                 bus->adapter.algo = &gmbus_algorithm;
 744                 bus->adapter.lock_ops = &gmbus_lock_ops;
 745
 746                 /*
 747                  * We wish to retry with bit banging
 748                  * after a timed out GMBUS attempt.
 749                  */
 750                 bus->adapter.retries = 1;
 751
 752                 /* By default use a conservative clock rate */
 753                 bus->reg0 = pin | GMBUS_RATE_100KHZ;
 754
 755                 /* gmbus seems to be broken on i830 */
 756                 if (IS_I830(dev_priv))
 757                         bus->force_bit = 1;
 758
 759                 intel_gpio_setup(bus, pin);
 760
 761                 ret = i2c_add_adapter(&bus->adapter);
 762                 if (ret)
 763                         goto err;
 764         }
 765
 766         intel_i2c_reset(dev_priv);
 767
 768         return 0;
 769
 770 err:
 771         while (pin--) {
 772                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 773                         continue;
 774
 775                 bus = &dev_priv->gmbus[pin];
 776                 i2c_del_adapter(&bus->adapter);
 777         }
 778         return ret;
 779 }
 780
 781 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
 782                                             unsigned int pin)
 783 {
 784         if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
 785                 return NULL;
 786
 787         return &dev_priv->gmbus[pin].adapter;
 788 }
 789
 790 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 791 {
 792         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 793
 794         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
 795 }
 796
 797 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 798 {
 799         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 800         struct drm_i915_private *dev_priv = bus->dev_priv;
 801
 802         mutex_lock(&dev_priv->gmbus_mutex);
 803
 804         bus->force_bit += force_bit ? 1 : -1;
 805         DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
 806                       force_bit ? "en" : "dis", adapter->name,
 807                       bus->force_bit);
 808
 809         mutex_unlock(&dev_priv->gmbus_mutex);
 810 }
 811
 812 void intel_teardown_gmbus(struct drm_i915_private *dev_priv)
 813 {
 814         struct intel_gmbus *bus;
 815         unsigned int pin;
 816
 817         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
 818                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 819                         continue;
 820
 821                 bus = &dev_priv->gmbus[pin];
 822                 i2c_del_adapter(&bus->adapter);
 823         }
 824 }