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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
blob80fa68d54bd370eb156432ef66700e5354f0c04d
1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include <linux/dma-mapping.h>
31 #include <linux/swiotlb.h>
32
33 #include "nouveau_drv.h"
34 #include "nouveau_dma.h"
35 #include "nouveau_fence.h"
36
37 #include "nouveau_bo.h"
38 #include "nouveau_ttm.h"
39 #include "nouveau_gem.h"
40 #include "nouveau_mem.h"
41 #include "nouveau_vmm.h"
42
43 #include <nvif/class.h>
44 #include <nvif/if500b.h>
45 #include <nvif/if900b.h>
46
47 /*
48 * NV10-NV40 tiling helpers
49 */
50
51 static void
52 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
53 u32 addr, u32 size, u32 pitch, u32 flags)
54 {
55 struct nouveau_drm *drm = nouveau_drm(dev);
56 int i = reg - drm->tile.reg;
57 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
58 struct nvkm_fb_tile *tile = &fb->tile.region[i];
59
60 nouveau_fence_unref(&reg->fence);
61
62 if (tile->pitch)
63 nvkm_fb_tile_fini(fb, i, tile);
64
65 if (pitch)
66 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
67
68 nvkm_fb_tile_prog(fb, i, tile);
69 }
70
71 static struct nouveau_drm_tile *
72 nv10_bo_get_tile_region(struct drm_device *dev, int i)
73 {
74 struct nouveau_drm *drm = nouveau_drm(dev);
75 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
76
77 spin_lock(&drm->tile.lock);
78
79 if (!tile->used &&
80 (!tile->fence || nouveau_fence_done(tile->fence)))
81 tile->used = true;
82 else
83 tile = NULL;
84
85 spin_unlock(&drm->tile.lock);
86 return tile;
87 }
88
89 static void
90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
91 struct dma_fence *fence)
92 {
93 struct nouveau_drm *drm = nouveau_drm(dev);
94
95 if (tile) {
96 spin_lock(&drm->tile.lock);
97 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
98 tile->used = false;
99 spin_unlock(&drm->tile.lock);
100 }
101 }
102
103 static struct nouveau_drm_tile *
104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
105 u32 size, u32 pitch, u32 zeta)
106 {
107 struct nouveau_drm *drm = nouveau_drm(dev);
108 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
109 struct nouveau_drm_tile *tile, *found = NULL;
110 int i;
111
112 for (i = 0; i < fb->tile.regions; i++) {
113 tile = nv10_bo_get_tile_region(dev, i);
114
115 if (pitch && !found) {
116 found = tile;
117 continue;
118
119 } else if (tile && fb->tile.region[i].pitch) {
120 /* Kill an unused tile region. */
121 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
122 }
123
124 nv10_bo_put_tile_region(dev, tile, NULL);
125 }
126
127 if (found)
128 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
129 return found;
130 }
131
132 static void
133 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
134 {
135 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
136 struct drm_device *dev = drm->dev;
137 struct nouveau_bo *nvbo = nouveau_bo(bo);
138
139 if (unlikely(nvbo->gem.filp))
140 DRM_ERROR("bo %p still attached to GEM object\n", bo);
141 WARN_ON(nvbo->pin_refcnt > 0);
142 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
143 kfree(nvbo);
144 }
145
146 static inline u64
147 roundup_64(u64 x, u32 y)
148 {
149 x += y - 1;
150 do_div(x, y);
151 return x * y;
152 }
153
154 static void
155 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
156 int *align, u64 *size)
157 {
158 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
159 struct nvif_device *device = &drm->client.device;
160
161 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
162 if (nvbo->mode) {
163 if (device->info.chipset >= 0x40) {
164 *align = 65536;
165 *size = roundup_64(*size, 64 * nvbo->mode);
166
167 } else if (device->info.chipset >= 0x30) {
168 *align = 32768;
169 *size = roundup_64(*size, 64 * nvbo->mode);
170
171 } else if (device->info.chipset >= 0x20) {
172 *align = 16384;
173 *size = roundup_64(*size, 64 * nvbo->mode);
174
175 } else if (device->info.chipset >= 0x10) {
176 *align = 16384;
177 *size = roundup_64(*size, 32 * nvbo->mode);
178 }
179 }
180 } else {
181 *size = roundup_64(*size, (1 << nvbo->page));
182 *align = max((1 << nvbo->page), *align);
183 }
184
185 *size = roundup_64(*size, PAGE_SIZE);
186 }
187
188 int
189 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
190 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
191 struct sg_table *sg, struct reservation_object *robj,
192 struct nouveau_bo **pnvbo)
193 {
194 struct nouveau_drm *drm = cli->drm;
195 struct nouveau_bo *nvbo;
196 struct nvif_mmu *mmu = &cli->mmu;
197 struct nvif_vmm *vmm = &cli->vmm.vmm;
198 size_t acc_size;
199 int type = ttm_bo_type_device;
200 int ret, i, pi = -1;
201
202 if (!size) {
203 NV_WARN(drm, "skipped size %016llx\n", size);
204 return -EINVAL;
205 }
206
207 if (sg)
208 type = ttm_bo_type_sg;
209
210 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
211 if (!nvbo)
212 return -ENOMEM;
213 INIT_LIST_HEAD(&nvbo->head);
214 INIT_LIST_HEAD(&nvbo->entry);
215 INIT_LIST_HEAD(&nvbo->vma_list);
216 nvbo->bo.bdev = &drm->ttm.bdev;
217 nvbo->cli = cli;
218
219 /* This is confusing, and doesn't actually mean we want an uncached
220 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
221 * into in nouveau_gem_new().
222 */
223 if (flags & TTM_PL_FLAG_UNCACHED) {
224 /* Determine if we can get a cache-coherent map, forcing
225 * uncached mapping if we can't.
226 */
227 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
228 nvbo->force_coherent = true;
229 }
230
231 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
232 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
233 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
234 kfree(nvbo);
235 return -EINVAL;
236 }
237
238 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
239 } else
240 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
241 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
242 nvbo->comp = (tile_flags & 0x00030000) >> 16;
243 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
244 kfree(nvbo);
245 return -EINVAL;
246 }
247 } else {
248 nvbo->zeta = (tile_flags & 0x00000007);
249 }
250 nvbo->mode = tile_mode;
251 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
252
253 /* Determine the desirable target GPU page size for the buffer. */
254 for (i = 0; i < vmm->page_nr; i++) {
255 /* Because we cannot currently allow VMM maps to fail
256 * during buffer migration, we need to determine page
257 * size for the buffer up-front, and pre-allocate its
258 * page tables.
259 *
260 * Skip page sizes that can't support needed domains.
261 */
262 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
263 (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram)
264 continue;
265 if ((flags & TTM_PL_FLAG_TT) &&
266 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
267 continue;
268
269 /* Select this page size if it's the first that supports
270 * the potential memory domains, or when it's compatible
271 * with the requested compression settings.
272 */
273 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
274 pi = i;
275
276 /* Stop once the buffer is larger than the current page size. */
277 if (size >= 1ULL << vmm->page[i].shift)
278 break;
279 }
280
281 if (WARN_ON(pi < 0))
282 return -EINVAL;
283
284 /* Disable compression if suitable settings couldn't be found. */
285 if (nvbo->comp && !vmm->page[pi].comp) {
286 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
287 nvbo->kind = mmu->kind[nvbo->kind];
288 nvbo->comp = 0;
289 }
290 nvbo->page = vmm->page[pi].shift;
291
292 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
293 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
294 nouveau_bo_placement_set(nvbo, flags, 0);
295
296 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
297 sizeof(struct nouveau_bo));
298
299 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
300 type, &nvbo->placement,
301 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
302 robj, nouveau_bo_del_ttm);
303 if (ret) {
304 /* ttm will call nouveau_bo_del_ttm if it fails.. */
305 return ret;
306 }
307
308 *pnvbo = nvbo;
309 return 0;
310 }
311
312 static void
313 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
314 {
315 *n = 0;
316
317 if (type & TTM_PL_FLAG_VRAM)
318 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
319 if (type & TTM_PL_FLAG_TT)
320 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
321 if (type & TTM_PL_FLAG_SYSTEM)
322 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
323 }
324
325 static void
326 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
327 {
328 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
329 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
330 unsigned i, fpfn, lpfn;
331
332 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
333 nvbo->mode && (type & TTM_PL_FLAG_VRAM) &&
334 nvbo->bo.mem.num_pages < vram_pages / 4) {
335 /*
336 * Make sure that the color and depth buffers are handled
337 * by independent memory controller units. Up to a 9x
338 * speed up when alpha-blending and depth-test are enabled
339 * at the same time.
340 */
341 if (nvbo->zeta) {
342 fpfn = vram_pages / 2;
343 lpfn = ~0;
344 } else {
345 fpfn = 0;
346 lpfn = vram_pages / 2;
347 }
348 for (i = 0; i < nvbo->placement.num_placement; ++i) {
349 nvbo->placements[i].fpfn = fpfn;
350 nvbo->placements[i].lpfn = lpfn;
351 }
352 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
353 nvbo->busy_placements[i].fpfn = fpfn;
354 nvbo->busy_placements[i].lpfn = lpfn;
355 }
356 }
357 }
358
359 void
360 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
361 {
362 struct ttm_placement *pl = &nvbo->placement;
363 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
364 TTM_PL_MASK_CACHING) |
365 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
366
367 pl->placement = nvbo->placements;
368 set_placement_list(nvbo->placements, &pl->num_placement,
369 type, flags);
370
371 pl->busy_placement = nvbo->busy_placements;
372 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
373 type | busy, flags);
374
375 set_placement_range(nvbo, type);
376 }
377
378 int
379 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
380 {
381 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
382 struct ttm_buffer_object *bo = &nvbo->bo;
383 bool force = false, evict = false;
384 int ret;
385
386 ret = ttm_bo_reserve(bo, false, false, NULL);
387 if (ret)
388 return ret;
389
390 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
391 memtype == TTM_PL_FLAG_VRAM && contig) {
392 if (!nvbo->contig) {
393 nvbo->contig = true;
394 force = true;
395 evict = true;
396 }
397 }
398
399 if (nvbo->pin_refcnt) {
400 if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
401 NV_ERROR(drm, "bo %p pinned elsewhere: "
402 "0x%08x vs 0x%08x\n", bo,
403 1 << bo->mem.mem_type, memtype);
404 ret = -EBUSY;
405 }
406 nvbo->pin_refcnt++;
407 goto out;
408 }
409
410 if (evict) {
411 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
412 ret = nouveau_bo_validate(nvbo, false, false);
413 if (ret)
414 goto out;
415 }
416
417 nvbo->pin_refcnt++;
418 nouveau_bo_placement_set(nvbo, memtype, 0);
419
420 /* drop pin_refcnt temporarily, so we don't trip the assertion
421 * in nouveau_bo_move() that makes sure we're not trying to
422 * move a pinned buffer
423 */
424 nvbo->pin_refcnt--;
425 ret = nouveau_bo_validate(nvbo, false, false);
426 if (ret)
427 goto out;
428 nvbo->pin_refcnt++;
429
430 switch (bo->mem.mem_type) {
431 case TTM_PL_VRAM:
432 drm->gem.vram_available -= bo->mem.size;
433 break;
434 case TTM_PL_TT:
435 drm->gem.gart_available -= bo->mem.size;
436 break;
437 default:
438 break;
439 }
440
441 out:
442 if (force && ret)
443 nvbo->contig = false;
444 ttm_bo_unreserve(bo);
445 return ret;
446 }
447
448 int
449 nouveau_bo_unpin(struct nouveau_bo *nvbo)
450 {
451 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
452 struct ttm_buffer_object *bo = &nvbo->bo;
453 int ret, ref;
454
455 ret = ttm_bo_reserve(bo, false, false, NULL);
456 if (ret)
457 return ret;
458
459 ref = --nvbo->pin_refcnt;
460 WARN_ON_ONCE(ref < 0);
461 if (ref)
462 goto out;
463
464 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
465
466 ret = nouveau_bo_validate(nvbo, false, false);
467 if (ret == 0) {
468 switch (bo->mem.mem_type) {
469 case TTM_PL_VRAM:
470 drm->gem.vram_available += bo->mem.size;
471 break;
472 case TTM_PL_TT:
473 drm->gem.gart_available += bo->mem.size;
474 break;
475 default:
476 break;
477 }
478 }
479
480 out:
481 ttm_bo_unreserve(bo);
482 return ret;
483 }
484
485 int
486 nouveau_bo_map(struct nouveau_bo *nvbo)
487 {
488 int ret;
489
490 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
491 if (ret)
492 return ret;
493
494 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
495
496 ttm_bo_unreserve(&nvbo->bo);
497 return ret;
498 }
499
500 void
501 nouveau_bo_unmap(struct nouveau_bo *nvbo)
502 {
503 if (!nvbo)
504 return;
505
506 ttm_bo_kunmap(&nvbo->kmap);
507 }
508
509 void
510 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
511 {
512 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
513 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
514 int i;
515
516 if (!ttm_dma)
517 return;
518
519 /* Don't waste time looping if the object is coherent */
520 if (nvbo->force_coherent)
521 return;
522
523 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
524 dma_sync_single_for_device(drm->dev->dev,
525 ttm_dma->dma_address[i],
526 PAGE_SIZE, DMA_TO_DEVICE);
527 }
528
529 void
530 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
531 {
532 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
533 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
534 int i;
535
536 if (!ttm_dma)
537 return;
538
539 /* Don't waste time looping if the object is coherent */
540 if (nvbo->force_coherent)
541 return;
542
543 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
544 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
545 PAGE_SIZE, DMA_FROM_DEVICE);
546 }
547
548 int
549 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
550 bool no_wait_gpu)
551 {
552 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
553 int ret;
554
555 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
556 if (ret)
557 return ret;
558
559 nouveau_bo_sync_for_device(nvbo);
560
561 return 0;
562 }
563
564 void
565 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
566 {
567 bool is_iomem;
568 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
569
570 mem += index;
571
572 if (is_iomem)
573 iowrite16_native(val, (void __force __iomem *)mem);
574 else
575 *mem = val;
576 }
577
578 u32
579 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
580 {
581 bool is_iomem;
582 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
583
584 mem += index;
585
586 if (is_iomem)
587 return ioread32_native((void __force __iomem *)mem);
588 else
589 return *mem;
590 }
591
592 void
593 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
594 {
595 bool is_iomem;
596 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
597
598 mem += index;
599
600 if (is_iomem)
601 iowrite32_native(val, (void __force __iomem *)mem);
602 else
603 *mem = val;
604 }
605
606 static struct ttm_tt *
607 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
608 uint32_t page_flags, struct page *dummy_read)
609 {
610 #if IS_ENABLED(CONFIG_AGP)
611 struct nouveau_drm *drm = nouveau_bdev(bdev);
612
613 if (drm->agp.bridge) {
614 return ttm_agp_tt_create(bdev, drm->agp.bridge, size,
615 page_flags, dummy_read);
616 }
617 #endif
618
619 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
620 }
621
622 static int
623 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
624 {
625 /* We'll do this from user space. */
626 return 0;
627 }
628
629 static int
630 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
631 struct ttm_mem_type_manager *man)
632 {
633 struct nouveau_drm *drm = nouveau_bdev(bdev);
634 struct nvif_mmu *mmu = &drm->client.mmu;
635
636 switch (type) {
637 case TTM_PL_SYSTEM:
638 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
639 man->available_caching = TTM_PL_MASK_CACHING;
640 man->default_caching = TTM_PL_FLAG_CACHED;
641 break;
642 case TTM_PL_VRAM:
643 man->flags = TTM_MEMTYPE_FLAG_FIXED |
644 TTM_MEMTYPE_FLAG_MAPPABLE;
645 man->available_caching = TTM_PL_FLAG_UNCACHED |
646 TTM_PL_FLAG_WC;
647 man->default_caching = TTM_PL_FLAG_WC;
648
649 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
650 /* Some BARs do not support being ioremapped WC */
651 const u8 type = mmu->type[drm->ttm.type_vram].type;
652 if (type & NVIF_MEM_UNCACHED) {
653 man->available_caching = TTM_PL_FLAG_UNCACHED;
654 man->default_caching = TTM_PL_FLAG_UNCACHED;
655 }
656
657 man->func = &nouveau_vram_manager;
658 man->io_reserve_fastpath = false;
659 man->use_io_reserve_lru = true;
660 } else {
661 man->func = &ttm_bo_manager_func;
662 }
663 break;
664 case TTM_PL_TT:
665 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA)
666 man->func = &nouveau_gart_manager;
667 else
668 if (!drm->agp.bridge)
669 man->func = &nv04_gart_manager;
670 else
671 man->func = &ttm_bo_manager_func;
672
673 if (drm->agp.bridge) {
674 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
675 man->available_caching = TTM_PL_FLAG_UNCACHED |
676 TTM_PL_FLAG_WC;
677 man->default_caching = TTM_PL_FLAG_WC;
678 } else {
679 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
680 TTM_MEMTYPE_FLAG_CMA;
681 man->available_caching = TTM_PL_MASK_CACHING;
682 man->default_caching = TTM_PL_FLAG_CACHED;
683 }
684
685 break;
686 default:
687 return -EINVAL;
688 }
689 return 0;
690 }
691
692 static void
693 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
694 {
695 struct nouveau_bo *nvbo = nouveau_bo(bo);
696
697 switch (bo->mem.mem_type) {
698 case TTM_PL_VRAM:
699 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
700 TTM_PL_FLAG_SYSTEM);
701 break;
702 default:
703 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
704 break;
705 }
706
707 *pl = nvbo->placement;
708 }
709
710
711 static int
712 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
713 {
714 int ret = RING_SPACE(chan, 2);
715 if (ret == 0) {
716 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
717 OUT_RING (chan, handle & 0x0000ffff);
718 FIRE_RING (chan);
719 }
720 return ret;
721 }
722
723 static int
724 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
725 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
726 {
727 struct nouveau_mem *mem = nouveau_mem(old_reg);
728 int ret = RING_SPACE(chan, 10);
729 if (ret == 0) {
730 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
731 OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
732 OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
733 OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
734 OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
735 OUT_RING (chan, PAGE_SIZE);
736 OUT_RING (chan, PAGE_SIZE);
737 OUT_RING (chan, PAGE_SIZE);
738 OUT_RING (chan, new_reg->num_pages);
739 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
740 }
741 return ret;
742 }
743
744 static int
745 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
746 {
747 int ret = RING_SPACE(chan, 2);
748 if (ret == 0) {
749 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
750 OUT_RING (chan, handle);
751 }
752 return ret;
753 }
754
755 static int
756 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
757 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
758 {
759 struct nouveau_mem *mem = nouveau_mem(old_reg);
760 u64 src_offset = mem->vma[0].addr;
761 u64 dst_offset = mem->vma[1].addr;
762 u32 page_count = new_reg->num_pages;
763 int ret;
764
765 page_count = new_reg->num_pages;
766 while (page_count) {
767 int line_count = (page_count > 8191) ? 8191 : page_count;
768
769 ret = RING_SPACE(chan, 11);
770 if (ret)
771 return ret;
772
773 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
774 OUT_RING (chan, upper_32_bits(src_offset));
775 OUT_RING (chan, lower_32_bits(src_offset));
776 OUT_RING (chan, upper_32_bits(dst_offset));
777 OUT_RING (chan, lower_32_bits(dst_offset));
778 OUT_RING (chan, PAGE_SIZE);
779 OUT_RING (chan, PAGE_SIZE);
780 OUT_RING (chan, PAGE_SIZE);
781 OUT_RING (chan, line_count);
782 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
783 OUT_RING (chan, 0x00000110);
784
785 page_count -= line_count;
786 src_offset += (PAGE_SIZE * line_count);
787 dst_offset += (PAGE_SIZE * line_count);
788 }
789
790 return 0;
791 }
792
793 static int
794 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
795 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
796 {
797 struct nouveau_mem *mem = nouveau_mem(old_reg);
798 u64 src_offset = mem->vma[0].addr;
799 u64 dst_offset = mem->vma[1].addr;
800 u32 page_count = new_reg->num_pages;
801 int ret;
802
803 page_count = new_reg->num_pages;
804 while (page_count) {
805 int line_count = (page_count > 2047) ? 2047 : page_count;
806
807 ret = RING_SPACE(chan, 12);
808 if (ret)
809 return ret;
810
811 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
812 OUT_RING (chan, upper_32_bits(dst_offset));
813 OUT_RING (chan, lower_32_bits(dst_offset));
814 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
815 OUT_RING (chan, upper_32_bits(src_offset));
816 OUT_RING (chan, lower_32_bits(src_offset));
817 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
818 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
819 OUT_RING (chan, PAGE_SIZE); /* line_length */
820 OUT_RING (chan, line_count);
821 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
822 OUT_RING (chan, 0x00100110);
823
824 page_count -= line_count;
825 src_offset += (PAGE_SIZE * line_count);
826 dst_offset += (PAGE_SIZE * line_count);
827 }
828
829 return 0;
830 }
831
832 static int
833 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
834 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
835 {
836 struct nouveau_mem *mem = nouveau_mem(old_reg);
837 u64 src_offset = mem->vma[0].addr;
838 u64 dst_offset = mem->vma[1].addr;
839 u32 page_count = new_reg->num_pages;
840 int ret;
841
842 page_count = new_reg->num_pages;
843 while (page_count) {
844 int line_count = (page_count > 8191) ? 8191 : page_count;
845
846 ret = RING_SPACE(chan, 11);
847 if (ret)
848 return ret;
849
850 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
851 OUT_RING (chan, upper_32_bits(src_offset));
852 OUT_RING (chan, lower_32_bits(src_offset));
853 OUT_RING (chan, upper_32_bits(dst_offset));
854 OUT_RING (chan, lower_32_bits(dst_offset));
855 OUT_RING (chan, PAGE_SIZE);
856 OUT_RING (chan, PAGE_SIZE);
857 OUT_RING (chan, PAGE_SIZE);
858 OUT_RING (chan, line_count);
859 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
860 OUT_RING (chan, 0x00000110);
861
862 page_count -= line_count;
863 src_offset += (PAGE_SIZE * line_count);
864 dst_offset += (PAGE_SIZE * line_count);
865 }
866
867 return 0;
868 }
869
870 static int
871 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
872 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
873 {
874 struct nouveau_mem *mem = nouveau_mem(old_reg);
875 int ret = RING_SPACE(chan, 7);
876 if (ret == 0) {
877 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
878 OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
879 OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
880 OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
881 OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
882 OUT_RING (chan, 0x00000000 /* COPY */);
883 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT);
884 }
885 return ret;
886 }
887
888 static int
889 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
890 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
891 {
892 struct nouveau_mem *mem = nouveau_mem(old_reg);
893 int ret = RING_SPACE(chan, 7);
894 if (ret == 0) {
895 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
896 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT);
897 OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
898 OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
899 OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
900 OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
901 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
902 }
903 return ret;
904 }
905
906 static int
907 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
908 {
909 int ret = RING_SPACE(chan, 6);
910 if (ret == 0) {
911 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
912 OUT_RING (chan, handle);
913 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
914 OUT_RING (chan, chan->drm->ntfy.handle);
915 OUT_RING (chan, chan->vram.handle);
916 OUT_RING (chan, chan->vram.handle);
917 }
918
919 return ret;
920 }
921
922 static int
923 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
924 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
925 {
926 struct nouveau_mem *mem = nouveau_mem(old_reg);
927 u64 length = (new_reg->num_pages << PAGE_SHIFT);
928 u64 src_offset = mem->vma[0].addr;
929 u64 dst_offset = mem->vma[1].addr;
930 int src_tiled = !!mem->kind;
931 int dst_tiled = !!nouveau_mem(new_reg)->kind;
932 int ret;
933
934 while (length) {
935 u32 amount, stride, height;
936
937 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
938 if (ret)
939 return ret;
940
941 amount = min(length, (u64)(4 * 1024 * 1024));
942 stride = 16 * 4;
943 height = amount / stride;
944
945 if (src_tiled) {
946 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
947 OUT_RING (chan, 0);
948 OUT_RING (chan, 0);
949 OUT_RING (chan, stride);
950 OUT_RING (chan, height);
951 OUT_RING (chan, 1);
952 OUT_RING (chan, 0);
953 OUT_RING (chan, 0);
954 } else {
955 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
956 OUT_RING (chan, 1);
957 }
958 if (dst_tiled) {
959 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
960 OUT_RING (chan, 0);
961 OUT_RING (chan, 0);
962 OUT_RING (chan, stride);
963 OUT_RING (chan, height);
964 OUT_RING (chan, 1);
965 OUT_RING (chan, 0);
966 OUT_RING (chan, 0);
967 } else {
968 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
969 OUT_RING (chan, 1);
970 }
971
972 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
973 OUT_RING (chan, upper_32_bits(src_offset));
974 OUT_RING (chan, upper_32_bits(dst_offset));
975 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
976 OUT_RING (chan, lower_32_bits(src_offset));
977 OUT_RING (chan, lower_32_bits(dst_offset));
978 OUT_RING (chan, stride);
979 OUT_RING (chan, stride);
980 OUT_RING (chan, stride);
981 OUT_RING (chan, height);
982 OUT_RING (chan, 0x00000101);
983 OUT_RING (chan, 0x00000000);
984 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
985 OUT_RING (chan, 0);
986
987 length -= amount;
988 src_offset += amount;
989 dst_offset += amount;
990 }
991
992 return 0;
993 }
994
995 static int
996 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
997 {
998 int ret = RING_SPACE(chan, 4);
999 if (ret == 0) {
1000 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
1001 OUT_RING (chan, handle);
1002 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
1003 OUT_RING (chan, chan->drm->ntfy.handle);
1004 }
1005
1006 return ret;
1007 }
1008
1009 static inline uint32_t
1010 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
1011 struct nouveau_channel *chan, struct ttm_mem_reg *reg)
1012 {
1013 if (reg->mem_type == TTM_PL_TT)
1014 return NvDmaTT;
1015 return chan->vram.handle;
1016 }
1017
1018 static int
1019 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
1020 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
1021 {
1022 u32 src_offset = old_reg->start << PAGE_SHIFT;
1023 u32 dst_offset = new_reg->start << PAGE_SHIFT;
1024 u32 page_count = new_reg->num_pages;
1025 int ret;
1026
1027 ret = RING_SPACE(chan, 3);
1028 if (ret)
1029 return ret;
1030
1031 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
1032 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg));
1033 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg));
1034
1035 page_count = new_reg->num_pages;
1036 while (page_count) {
1037 int line_count = (page_count > 2047) ? 2047 : page_count;
1038
1039 ret = RING_SPACE(chan, 11);
1040 if (ret)
1041 return ret;
1042
1043 BEGIN_NV04(chan, NvSubCopy,
1044 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
1045 OUT_RING (chan, src_offset);
1046 OUT_RING (chan, dst_offset);
1047 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
1048 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
1049 OUT_RING (chan, PAGE_SIZE); /* line_length */
1050 OUT_RING (chan, line_count);
1051 OUT_RING (chan, 0x00000101);
1052 OUT_RING (chan, 0x00000000);
1053 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
1054 OUT_RING (chan, 0);
1055
1056 page_count -= line_count;
1057 src_offset += (PAGE_SIZE * line_count);
1058 dst_offset += (PAGE_SIZE * line_count);
1059 }
1060
1061 return 0;
1062 }
1063
1064 static int
1065 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
1066 struct ttm_mem_reg *reg)
1067 {
1068 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
1069 struct nouveau_mem *new_mem = nouveau_mem(reg);
1070 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
1071 int ret;
1072
1073 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
1074 old_mem->mem.size, &old_mem->vma[0]);
1075 if (ret)
1076 return ret;
1077
1078 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
1079 new_mem->mem.size, &old_mem->vma[1]);
1080 if (ret)
1081 goto done;
1082
1083 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
1084 if (ret)
1085 goto done;
1086
1087 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
1088 done:
1089 if (ret) {
1090 nvif_vmm_put(vmm, &old_mem->vma[1]);
1091 nvif_vmm_put(vmm, &old_mem->vma[0]);
1092 }
1093 return 0;
1094 }
1095
1096 static int
1097 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
1098 bool no_wait_gpu, struct ttm_mem_reg *new_reg)
1099 {
1100 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1101 struct nouveau_channel *chan = drm->ttm.chan;
1102 struct nouveau_cli *cli = (void *)chan->user.client;
1103 struct nouveau_fence *fence;
1104 int ret;
1105
1106 /* create temporary vmas for the transfer and attach them to the
1107 * old nvkm_mem node, these will get cleaned up after ttm has
1108 * destroyed the ttm_mem_reg
1109 */
1110 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1111 ret = nouveau_bo_move_prep(drm, bo, new_reg);
1112 if (ret)
1113 return ret;
1114 }
1115
1116 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
1117 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
1118 if (ret == 0) {
1119 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
1120 if (ret == 0) {
1121 ret = nouveau_fence_new(chan, false, &fence);
1122 if (ret == 0) {
1123 ret = ttm_bo_move_accel_cleanup(bo,
1124 &fence->base,
1125 evict,
1126 new_reg);
1127 nouveau_fence_unref(&fence);
1128 }
1129 }
1130 }
1131 mutex_unlock(&cli->mutex);
1132 return ret;
1133 }
1134
1135 void
1136 nouveau_bo_move_init(struct nouveau_drm *drm)
1137 {
1138 static const struct {
1139 const char *name;
1140 int engine;
1141 s32 oclass;
1142 int (*exec)(struct nouveau_channel *,
1143 struct ttm_buffer_object *,
1144 struct ttm_mem_reg *, struct ttm_mem_reg *);
1145 int (*init)(struct nouveau_channel *, u32 handle);
1146 } _methods[] = {
1147 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
1148 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
1149 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
1150 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1151 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
1152 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1153 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1154 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1155 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1156 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1157 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1158 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1159 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1160 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1161 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1162 {},
1163 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1164 }, *mthd = _methods;
1165 const char *name = "CPU";
1166 int ret;
1167
1168 do {
1169 struct nouveau_channel *chan;
1170
1171 if (mthd->engine)
1172 chan = drm->cechan;
1173 else
1174 chan = drm->channel;
1175 if (chan == NULL)
1176 continue;
1177
1178 ret = nvif_object_init(&chan->user,
1179 mthd->oclass | (mthd->engine << 16),
1180 mthd->oclass, NULL, 0,
1181 &drm->ttm.copy);
1182 if (ret == 0) {
1183 ret = mthd->init(chan, drm->ttm.copy.handle);
1184 if (ret) {
1185 nvif_object_fini(&drm->ttm.copy);
1186 continue;
1187 }
1188
1189 drm->ttm.move = mthd->exec;
1190 drm->ttm.chan = chan;
1191 name = mthd->name;
1192 break;
1193 }
1194 } while ((++mthd)->exec);
1195
1196 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1197 }
1198
1199 static int
1200 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1201 bool no_wait_gpu, struct ttm_mem_reg *new_reg)
1202 {
1203 struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
1204 struct ttm_place placement_memtype = {
1205 .fpfn = 0,
1206 .lpfn = 0,
1207 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1208 };
1209 struct ttm_placement placement;
1210 struct ttm_mem_reg tmp_reg;
1211 int ret;
1212
1213 placement.num_placement = placement.num_busy_placement = 1;
1214 placement.placement = placement.busy_placement = &placement_memtype;
1215
1216 tmp_reg = *new_reg;
1217 tmp_reg.mm_node = NULL;
1218 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
1219 if (ret)
1220 return ret;
1221
1222 ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx);
1223 if (ret)
1224 goto out;
1225
1226 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg);
1227 if (ret)
1228 goto out;
1229
1230 ret = ttm_bo_move_ttm(bo, &ctx, new_reg);
1231 out:
1232 ttm_bo_mem_put(bo, &tmp_reg);
1233 return ret;
1234 }
1235
1236 static int
1237 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1238 bool no_wait_gpu, struct ttm_mem_reg *new_reg)
1239 {
1240 struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
1241 struct ttm_place placement_memtype = {
1242 .fpfn = 0,
1243 .lpfn = 0,
1244 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1245 };
1246 struct ttm_placement placement;
1247 struct ttm_mem_reg tmp_reg;
1248 int ret;
1249
1250 placement.num_placement = placement.num_busy_placement = 1;
1251 placement.placement = placement.busy_placement = &placement_memtype;
1252
1253 tmp_reg = *new_reg;
1254 tmp_reg.mm_node = NULL;
1255 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
1256 if (ret)
1257 return ret;
1258
1259 ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg);
1260 if (ret)
1261 goto out;
1262
1263 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg);
1264 if (ret)
1265 goto out;
1266
1267 out:
1268 ttm_bo_mem_put(bo, &tmp_reg);
1269 return ret;
1270 }
1271
1272 static void
1273 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
1274 struct ttm_mem_reg *new_reg)
1275 {
1276 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
1277 struct nouveau_bo *nvbo = nouveau_bo(bo);
1278 struct nouveau_vma *vma;
1279
1280 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1281 if (bo->destroy != nouveau_bo_del_ttm)
1282 return;
1283
1284 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
1285 mem->mem.page == nvbo->page) {
1286 list_for_each_entry(vma, &nvbo->vma_list, head) {
1287 nouveau_vma_map(vma, mem);
1288 }
1289 } else {
1290 list_for_each_entry(vma, &nvbo->vma_list, head) {
1291 WARN_ON(ttm_bo_wait(bo, false, false));
1292 nouveau_vma_unmap(vma);
1293 }
1294 }
1295 }
1296
1297 static int
1298 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg,
1299 struct nouveau_drm_tile **new_tile)
1300 {
1301 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1302 struct drm_device *dev = drm->dev;
1303 struct nouveau_bo *nvbo = nouveau_bo(bo);
1304 u64 offset = new_reg->start << PAGE_SHIFT;
1305
1306 *new_tile = NULL;
1307 if (new_reg->mem_type != TTM_PL_VRAM)
1308 return 0;
1309
1310 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1311 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
1312 nvbo->mode, nvbo->zeta);
1313 }
1314
1315 return 0;
1316 }
1317
1318 static void
1319 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1320 struct nouveau_drm_tile *new_tile,
1321 struct nouveau_drm_tile **old_tile)
1322 {
1323 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1324 struct drm_device *dev = drm->dev;
1325 struct dma_fence *fence = reservation_object_get_excl(bo->resv);
1326
1327 nv10_bo_put_tile_region(dev, *old_tile, fence);
1328 *old_tile = new_tile;
1329 }
1330
1331 static int
1332 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1333 struct ttm_operation_ctx *ctx,
1334 struct ttm_mem_reg *new_reg)
1335 {
1336 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1337 struct nouveau_bo *nvbo = nouveau_bo(bo);
1338 struct ttm_mem_reg *old_reg = &bo->mem;
1339 struct nouveau_drm_tile *new_tile = NULL;
1340 int ret = 0;
1341
1342 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1343 if (ret)
1344 return ret;
1345
1346 if (nvbo->pin_refcnt)
1347 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1348
1349 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1350 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1351 if (ret)
1352 return ret;
1353 }
1354
1355 /* Fake bo copy. */
1356 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1357 BUG_ON(bo->mem.mm_node != NULL);
1358 bo->mem = *new_reg;
1359 new_reg->mm_node = NULL;
1360 goto out;
1361 }
1362
1363 /* Hardware assisted copy. */
1364 if (drm->ttm.move) {
1365 if (new_reg->mem_type == TTM_PL_SYSTEM)
1366 ret = nouveau_bo_move_flipd(bo, evict,
1367 ctx->interruptible,
1368 ctx->no_wait_gpu, new_reg);
1369 else if (old_reg->mem_type == TTM_PL_SYSTEM)
1370 ret = nouveau_bo_move_flips(bo, evict,
1371 ctx->interruptible,
1372 ctx->no_wait_gpu, new_reg);
1373 else
1374 ret = nouveau_bo_move_m2mf(bo, evict,
1375 ctx->interruptible,
1376 ctx->no_wait_gpu, new_reg);
1377 if (!ret)
1378 goto out;
1379 }
1380
1381 /* Fallback to software copy. */
1382 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1383 if (ret == 0)
1384 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1385
1386 out:
1387 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1388 if (ret)
1389 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1390 else
1391 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1392 }
1393
1394 return ret;
1395 }
1396
1397 static int
1398 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1399 {
1400 struct nouveau_bo *nvbo = nouveau_bo(bo);
1401
1402 return drm_vma_node_verify_access(&nvbo->gem.vma_node,
1403 filp->private_data);
1404 }
1405
1406 static int
1407 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
1408 {
1409 struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type];
1410 struct nouveau_drm *drm = nouveau_bdev(bdev);
1411 struct nvkm_device *device = nvxx_device(&drm->client.device);
1412 struct nouveau_mem *mem = nouveau_mem(reg);
1413
1414 reg->bus.addr = NULL;
1415 reg->bus.offset = 0;
1416 reg->bus.size = reg->num_pages << PAGE_SHIFT;
1417 reg->bus.base = 0;
1418 reg->bus.is_iomem = false;
1419 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1420 return -EINVAL;
1421 switch (reg->mem_type) {
1422 case TTM_PL_SYSTEM:
1423 /* System memory */
1424 return 0;
1425 case TTM_PL_TT:
1426 #if IS_ENABLED(CONFIG_AGP)
1427 if (drm->agp.bridge) {
1428 reg->bus.offset = reg->start << PAGE_SHIFT;
1429 reg->bus.base = drm->agp.base;
1430 reg->bus.is_iomem = !drm->agp.cma;
1431 }
1432 #endif
1433 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind)
1434 /* untiled */
1435 break;
1436 /* fallthrough, tiled memory */
1437 case TTM_PL_VRAM:
1438 reg->bus.offset = reg->start << PAGE_SHIFT;
1439 reg->bus.base = device->func->resource_addr(device, 1);
1440 reg->bus.is_iomem = true;
1441 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1442 union {
1443 struct nv50_mem_map_v0 nv50;
1444 struct gf100_mem_map_v0 gf100;
1445 } args;
1446 u64 handle, length;
1447 u32 argc = 0;
1448 int ret;
1449
1450 switch (mem->mem.object.oclass) {
1451 case NVIF_CLASS_MEM_NV50:
1452 args.nv50.version = 0;
1453 args.nv50.ro = 0;
1454 args.nv50.kind = mem->kind;
1455 args.nv50.comp = mem->comp;
1456 argc = sizeof(args.nv50);
1457 break;
1458 case NVIF_CLASS_MEM_GF100:
1459 args.gf100.version = 0;
1460 args.gf100.ro = 0;
1461 args.gf100.kind = mem->kind;
1462 argc = sizeof(args.gf100);
1463 break;
1464 default:
1465 WARN_ON(1);
1466 break;
1467 }
1468
1469 ret = nvif_object_map_handle(&mem->mem.object,
1470 &args, argc,
1471 &handle, &length);
1472 if (ret != 1)
1473 return ret ? ret : -EINVAL;
1474
1475 reg->bus.base = 0;
1476 reg->bus.offset = handle;
1477 }
1478 break;
1479 default:
1480 return -EINVAL;
1481 }
1482 return 0;
1483 }
1484
1485 static void
1486 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
1487 {
1488 struct nouveau_drm *drm = nouveau_bdev(bdev);
1489 struct nouveau_mem *mem = nouveau_mem(reg);
1490
1491 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1492 switch (reg->mem_type) {
1493 case TTM_PL_TT:
1494 if (mem->kind)
1495 nvif_object_unmap_handle(&mem->mem.object);
1496 break;
1497 case TTM_PL_VRAM:
1498 nvif_object_unmap_handle(&mem->mem.object);
1499 break;
1500 default:
1501 break;
1502 }
1503 }
1504 }
1505
1506 static int
1507 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1508 {
1509 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1510 struct nouveau_bo *nvbo = nouveau_bo(bo);
1511 struct nvkm_device *device = nvxx_device(&drm->client.device);
1512 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1513 int i, ret;
1514
1515 /* as long as the bo isn't in vram, and isn't tiled, we've got
1516 * nothing to do here.
1517 */
1518 if (bo->mem.mem_type != TTM_PL_VRAM) {
1519 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1520 !nvbo->kind)
1521 return 0;
1522
1523 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1524 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1525
1526 ret = nouveau_bo_validate(nvbo, false, false);
1527 if (ret)
1528 return ret;
1529 }
1530 return 0;
1531 }
1532
1533 /* make sure bo is in mappable vram */
1534 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1535 bo->mem.start + bo->mem.num_pages < mappable)
1536 return 0;
1537
1538 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1539 nvbo->placements[i].fpfn = 0;
1540 nvbo->placements[i].lpfn = mappable;
1541 }
1542
1543 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1544 nvbo->busy_placements[i].fpfn = 0;
1545 nvbo->busy_placements[i].lpfn = mappable;
1546 }
1547
1548 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1549 return nouveau_bo_validate(nvbo, false, false);
1550 }
1551
1552 static int
1553 nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1554 {
1555 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1556 struct nouveau_drm *drm;
1557 struct device *dev;
1558 unsigned i;
1559 int r;
1560 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1561
1562 if (ttm->state != tt_unpopulated)
1563 return 0;
1564
1565 if (slave && ttm->sg) {
1566 /* make userspace faulting work */
1567 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1568 ttm_dma->dma_address, ttm->num_pages);
1569 ttm->state = tt_unbound;
1570 return 0;
1571 }
1572
1573 drm = nouveau_bdev(ttm->bdev);
1574 dev = drm->dev->dev;
1575
1576 #if IS_ENABLED(CONFIG_AGP)
1577 if (drm->agp.bridge) {
1578 return ttm_agp_tt_populate(ttm, ctx);
1579 }
1580 #endif
1581
1582 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1583 if (swiotlb_nr_tbl()) {
1584 return ttm_dma_populate((void *)ttm, dev, ctx);
1585 }
1586 #endif
1587
1588 r = ttm_pool_populate(ttm, ctx);
1589 if (r) {
1590 return r;
1591 }
1592
1593 for (i = 0; i < ttm->num_pages; i++) {
1594 dma_addr_t addr;
1595
1596 addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE,
1597 DMA_BIDIRECTIONAL);
1598
1599 if (dma_mapping_error(dev, addr)) {
1600 while (i--) {
1601 dma_unmap_page(dev, ttm_dma->dma_address[i],
1602 PAGE_SIZE, DMA_BIDIRECTIONAL);
1603 ttm_dma->dma_address[i] = 0;
1604 }
1605 ttm_pool_unpopulate(ttm);
1606 return -EFAULT;
1607 }
1608
1609 ttm_dma->dma_address[i] = addr;
1610 }
1611 return 0;
1612 }
1613
1614 static void
1615 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1616 {
1617 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1618 struct nouveau_drm *drm;
1619 struct device *dev;
1620 unsigned i;
1621 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1622
1623 if (slave)
1624 return;
1625
1626 drm = nouveau_bdev(ttm->bdev);
1627 dev = drm->dev->dev;
1628
1629 #if IS_ENABLED(CONFIG_AGP)
1630 if (drm->agp.bridge) {
1631 ttm_agp_tt_unpopulate(ttm);
1632 return;
1633 }
1634 #endif
1635
1636 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1637 if (swiotlb_nr_tbl()) {
1638 ttm_dma_unpopulate((void *)ttm, dev);
1639 return;
1640 }
1641 #endif
1642
1643 for (i = 0; i < ttm->num_pages; i++) {
1644 if (ttm_dma->dma_address[i]) {
1645 dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE,
1646 DMA_BIDIRECTIONAL);
1647 }
1648 }
1649
1650 ttm_pool_unpopulate(ttm);
1651 }
1652
1653 void
1654 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1655 {
1656 struct reservation_object *resv = nvbo->bo.resv;
1657
1658 if (exclusive)
1659 reservation_object_add_excl_fence(resv, &fence->base);
1660 else if (fence)
1661 reservation_object_add_shared_fence(resv, &fence->base);
1662 }
1663
1664 struct ttm_bo_driver nouveau_bo_driver = {
1665 .ttm_tt_create = &nouveau_ttm_tt_create,
1666 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1667 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1668 .invalidate_caches = nouveau_bo_invalidate_caches,
1669 .init_mem_type = nouveau_bo_init_mem_type,
1670 .eviction_valuable = ttm_bo_eviction_valuable,
1671 .evict_flags = nouveau_bo_evict_flags,
1672 .move_notify = nouveau_bo_move_ntfy,
1673 .move = nouveau_bo_move,
1674 .verify_access = nouveau_bo_verify_access,
1675 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1676 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1677 .io_mem_free = &nouveau_ttm_io_mem_free,
1678 };
CRIS linux kernel tree