drivers/gpu/drm/nouveau/nv84_fence.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "nouveau_drv.h"
  26 #include "nouveau_dma.h"
  27 #include "nouveau_fence.h"
  28 #include "nouveau_vmm.h"
  29
  30 #include "nv50_display.h"
  31
  32 static int
  33 nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  34 {
  35         int ret = RING_SPACE(chan, 8);
  36         if (ret == 0) {
  37                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  38                 OUT_RING  (chan, chan->vram.handle);
  39                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
  40                 OUT_RING  (chan, upper_32_bits(virtual));
  41                 OUT_RING  (chan, lower_32_bits(virtual));
  42                 OUT_RING  (chan, sequence);
  43                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
  44                 OUT_RING  (chan, 0x00000000);
  45                 FIRE_RING (chan);
  46         }
  47         return ret;
  48 }
  49
  50 static int
  51 nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  52 {
  53         int ret = RING_SPACE(chan, 7);
  54         if (ret == 0) {
  55                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  56                 OUT_RING  (chan, chan->vram.handle);
  57                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  58                 OUT_RING  (chan, upper_32_bits(virtual));
  59                 OUT_RING  (chan, lower_32_bits(virtual));
  60                 OUT_RING  (chan, sequence);
  61                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
  62                 FIRE_RING (chan);
  63         }
  64         return ret;
  65 }
  66
  67 static int
  68 nv84_fence_emit(struct nouveau_fence *fence)
  69 {
  70         struct nouveau_channel *chan = fence->channel;
  71         struct nv84_fence_chan *fctx = chan->fence;
  72         u64 addr = fctx->vma->addr + chan->chid * 16;
  73
  74         return fctx->base.emit32(chan, addr, fence->base.seqno);
  75 }
  76
  77 static int
  78 nv84_fence_sync(struct nouveau_fence *fence,
  79                 struct nouveau_channel *prev, struct nouveau_channel *chan)
  80 {
  81         struct nv84_fence_chan *fctx = chan->fence;
  82         u64 addr = fctx->vma->addr + prev->chid * 16;
  83
  84         return fctx->base.sync32(chan, addr, fence->base.seqno);
  85 }
  86
  87 static u32
  88 nv84_fence_read(struct nouveau_channel *chan)
  89 {
  90         struct nv84_fence_priv *priv = chan->drm->fence;
  91         return nouveau_bo_rd32(priv->bo, chan->chid * 16/4);
  92 }
  93
  94 static void
  95 nv84_fence_context_del(struct nouveau_channel *chan)
  96 {
  97         struct nv84_fence_priv *priv = chan->drm->fence;
  98         struct nv84_fence_chan *fctx = chan->fence;
  99
 100         nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
 101         mutex_lock(&priv->mutex);
 102         nouveau_vma_del(&fctx->vma);
 103         mutex_unlock(&priv->mutex);
 104         nouveau_fence_context_del(&fctx->base);
 105         chan->fence = NULL;
 106         nouveau_fence_context_free(&fctx->base);
 107 }
 108
 109 int
 110 nv84_fence_context_new(struct nouveau_channel *chan)
 111 {
 112         struct nouveau_cli *cli = (void *)chan->user.client;
 113         struct nv84_fence_priv *priv = chan->drm->fence;
 114         struct nv84_fence_chan *fctx;
 115         int ret;
 116
 117         fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
 118         if (!fctx)
 119                 return -ENOMEM;
 120
 121         nouveau_fence_context_new(chan, &fctx->base);
 122         fctx->base.emit = nv84_fence_emit;
 123         fctx->base.sync = nv84_fence_sync;
 124         fctx->base.read = nv84_fence_read;
 125         fctx->base.emit32 = nv84_fence_emit32;
 126         fctx->base.sync32 = nv84_fence_sync32;
 127         fctx->base.sequence = nv84_fence_read(chan);
 128
 129         mutex_lock(&priv->mutex);
 130         ret = nouveau_vma_new(priv->bo, &cli->vmm, &fctx->vma);
 131         mutex_unlock(&priv->mutex);
 132
 133         if (ret)
 134                 nv84_fence_context_del(chan);
 135         return ret;
 136 }
 137
 138 static bool
 139 nv84_fence_suspend(struct nouveau_drm *drm)
 140 {
 141         struct nv84_fence_priv *priv = drm->fence;
 142         int i;
 143
 144         priv->suspend = vmalloc(priv->base.contexts * sizeof(u32));
 145         if (priv->suspend) {
 146                 for (i = 0; i < priv->base.contexts; i++)
 147                         priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
 148         }
 149
 150         return priv->suspend != NULL;
 151 }
 152
 153 static void
 154 nv84_fence_resume(struct nouveau_drm *drm)
 155 {
 156         struct nv84_fence_priv *priv = drm->fence;
 157         int i;
 158
 159         if (priv->suspend) {
 160                 for (i = 0; i < priv->base.contexts; i++)
 161                         nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
 162                 vfree(priv->suspend);
 163                 priv->suspend = NULL;
 164         }
 165 }
 166
 167 static void
 168 nv84_fence_destroy(struct nouveau_drm *drm)
 169 {
 170         struct nv84_fence_priv *priv = drm->fence;
 171         nouveau_bo_unmap(priv->bo);
 172         if (priv->bo)
 173                 nouveau_bo_unpin(priv->bo);
 174         nouveau_bo_ref(NULL, &priv->bo);
 175         drm->fence = NULL;
 176         kfree(priv);
 177 }
 178
 179 int
 180 nv84_fence_create(struct nouveau_drm *drm)
 181 {
 182         struct nvkm_fifo *fifo = nvxx_fifo(&drm->client.device);
 183         struct nv84_fence_priv *priv;
 184         u32 domain;
 185         int ret;
 186
 187         priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
 188         if (!priv)
 189                 return -ENOMEM;
 190
 191         priv->base.dtor = nv84_fence_destroy;
 192         priv->base.suspend = nv84_fence_suspend;
 193         priv->base.resume = nv84_fence_resume;
 194         priv->base.context_new = nv84_fence_context_new;
 195         priv->base.context_del = nv84_fence_context_del;
 196
 197         priv->base.contexts = fifo->nr;
 198         priv->base.context_base = dma_fence_context_alloc(priv->base.contexts);
 199         priv->base.uevent = true;
 200
 201         mutex_init(&priv->mutex);
 202
 203         /* Use VRAM if there is any ; otherwise fallback to system memory */
 204         domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
 205                          /*
 206                           * fences created in sysmem must be non-cached or we
 207                           * will lose CPU/GPU coherency!
 208                           */
 209                          TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
 210         ret = nouveau_bo_new(&drm->client, 16 * priv->base.contexts, 0,
 211                              domain, 0, 0, NULL, NULL, &priv->bo);
 212         if (ret == 0) {
 213                 ret = nouveau_bo_pin(priv->bo, domain, false);
 214                 if (ret == 0) {
 215                         ret = nouveau_bo_map(priv->bo);
 216                         if (ret)
 217                                 nouveau_bo_unpin(priv->bo);
 218                 }
 219                 if (ret)
 220                         nouveau_bo_ref(NULL, &priv->bo);
 221         }
 222
 223         if (ret)
 224                 nv84_fence_destroy(drm);
 225         return ret;
 226 }