drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25 #include "fuc/gt215.fuc3.h"
  26
  27 #include <core/client.h>
  28 #include <core/enum.h>
  29 #include <core/gpuobj.h>
  30 #include <engine/fifo.h>
  31
  32 #include <nvif/class.h>
  33
  34 static const struct nvkm_enum
  35 gt215_ce_isr_error_name[] = {
  36         { 0x0001, "ILLEGAL_MTHD" },
  37         { 0x0002, "INVALID_ENUM" },
  38         { 0x0003, "INVALID_BITFIELD" },
  39         {}
  40 };
  41
  42 void
  43 gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan)
  44 {
  45         struct nvkm_subdev *subdev = &ce->engine.subdev;
  46         struct nvkm_device *device = subdev->device;
  47         const u32 base = (subdev->index - NVKM_ENGINE_CE0) * 0x1000;
  48         u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff;
  49         u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16;
  50         u32 mthd = (addr & 0x07ff) << 2;
  51         u32 subc = (addr & 0x3800) >> 11;
  52         u32 data = nvkm_rd32(device, 0x104044 + base);
  53         const struct nvkm_enum *en =
  54                 nvkm_enum_find(gt215_ce_isr_error_name, ssta);
  55
  56         nvkm_error(subdev, "DISPATCH_ERROR %04x [%s] ch %d [%010llx %s] "
  57                            "subc %d mthd %04x data %08x\n", ssta,
  58                    en ? en->name : "", chan ? chan->chid : -1,
  59                    chan ? chan->inst->addr : 0,
  60                    chan ? chan->object.client->name : "unknown",
  61                    subc, mthd, data);
  62 }
  63
  64 static const struct nvkm_falcon_func
  65 gt215_ce = {
  66         .code.data = gt215_ce_code,
  67         .code.size = sizeof(gt215_ce_code),
  68         .data.data = gt215_ce_data,
  69         .data.size = sizeof(gt215_ce_data),
  70         .intr = gt215_ce_intr,
  71         .sclass = {
  72                 { -1, -1, GT212_DMA },
  73                 {}
  74         }
  75 };
  76
  77 int
  78 gt215_ce_new(struct nvkm_device *device, int index,
  79              struct nvkm_engine **pengine)
  80 {
  81         return nvkm_falcon_new_(&gt215_ce, device, index,
  82                                 (device->chipset != 0xaf), 0x104000, pengine);
  83 }