drivers/gpu/drm/nouveau/nvkm/engine/disp/baseg84.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "dmacnv50.h"
  25 #include "rootnv50.h"
  26
  27 #include <nvif/class.h>
  28
  29 static const struct nv50_disp_mthd_list
  30 g84_disp_base_mthd_base = {
  31         .mthd = 0x0000,
  32         .addr = 0x000000,
  33         .data = {
  34                 { 0x0080, 0x000000 },
  35                 { 0x0084, 0x0008c4 },
  36                 { 0x0088, 0x0008d0 },
  37                 { 0x008c, 0x0008dc },
  38                 { 0x0090, 0x0008e4 },
  39                 { 0x0094, 0x610884 },
  40                 { 0x00a0, 0x6108a0 },
  41                 { 0x00a4, 0x610878 },
  42                 { 0x00c0, 0x61086c },
  43                 { 0x00c4, 0x610800 },
  44                 { 0x00c8, 0x61080c },
  45                 { 0x00cc, 0x610818 },
  46                 { 0x00e0, 0x610858 },
  47                 { 0x00e4, 0x610860 },
  48                 { 0x00e8, 0x6108ac },
  49                 { 0x00ec, 0x6108b4 },
  50                 { 0x00fc, 0x610824 },
  51                 { 0x0100, 0x610894 },
  52                 { 0x0104, 0x61082c },
  53                 { 0x0110, 0x6108bc },
  54                 { 0x0114, 0x61088c },
  55                 {}
  56         }
  57 };
  58
  59 const struct nv50_disp_chan_mthd
  60 g84_disp_base_chan_mthd = {
  61         .name = "Base",
  62         .addr = 0x000540,
  63         .prev = 0x000004,
  64         .data = {
  65                 { "Global", 1, &g84_disp_base_mthd_base },
  66                 {  "Image", 2, &nv50_disp_base_mthd_image },
  67                 {}
  68         }
  69 };
  70
  71 const struct nv50_disp_dmac_oclass
  72 g84_disp_base_oclass = {
  73         .base.oclass = G82_DISP_BASE_CHANNEL_DMA,
  74         .base.minver = 0,
  75         .base.maxver = 0,
  76         .ctor = nv50_disp_base_new,
  77         .func = &nv50_disp_dmac_func,
  78         .mthd = &g84_disp_base_chan_mthd,
  79         .chid = 1,
  80 };