drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "dmacnv50.h"
  25 #include "rootnv50.h"
  26
  27 #include <nvif/class.h>
  28
  29 static const struct nv50_disp_mthd_list
  30 gf119_disp_base_mthd_base = {
  31         .mthd = 0x0000,
  32         .addr = 0x000000,
  33         .data = {
  34                 { 0x0080, 0x661080 },
  35                 { 0x0084, 0x661084 },
  36                 { 0x0088, 0x661088 },
  37                 { 0x008c, 0x66108c },
  38                 { 0x0090, 0x661090 },
  39                 { 0x0094, 0x661094 },
  40                 { 0x00a0, 0x6610a0 },
  41                 { 0x00a4, 0x6610a4 },
  42                 { 0x00c0, 0x6610c0 },
  43                 { 0x00c4, 0x6610c4 },
  44                 { 0x00c8, 0x6610c8 },
  45                 { 0x00cc, 0x6610cc },
  46                 { 0x00e0, 0x6610e0 },
  47                 { 0x00e4, 0x6610e4 },
  48                 { 0x00e8, 0x6610e8 },
  49                 { 0x00ec, 0x6610ec },
  50                 { 0x00fc, 0x6610fc },
  51                 { 0x0100, 0x661100 },
  52                 { 0x0104, 0x661104 },
  53                 { 0x0108, 0x661108 },
  54                 { 0x010c, 0x66110c },
  55                 { 0x0110, 0x661110 },
  56                 { 0x0114, 0x661114 },
  57                 { 0x0118, 0x661118 },
  58                 { 0x011c, 0x66111c },
  59                 { 0x0130, 0x661130 },
  60                 { 0x0134, 0x661134 },
  61                 { 0x0138, 0x661138 },
  62                 { 0x013c, 0x66113c },
  63                 { 0x0140, 0x661140 },
  64                 { 0x0144, 0x661144 },
  65                 { 0x0148, 0x661148 },
  66                 { 0x014c, 0x66114c },
  67                 { 0x0150, 0x661150 },
  68                 { 0x0154, 0x661154 },
  69                 { 0x0158, 0x661158 },
  70                 { 0x015c, 0x66115c },
  71                 { 0x0160, 0x661160 },
  72                 { 0x0164, 0x661164 },
  73                 { 0x0168, 0x661168 },
  74                 { 0x016c, 0x66116c },
  75                 {}
  76         }
  77 };
  78
  79 static const struct nv50_disp_mthd_list
  80 gf119_disp_base_mthd_image = {
  81         .mthd = 0x0020,
  82         .addr = 0x000020,
  83         .data = {
  84                 { 0x0400, 0x661400 },
  85                 { 0x0404, 0x661404 },
  86                 { 0x0408, 0x661408 },
  87                 { 0x040c, 0x66140c },
  88                 { 0x0410, 0x661410 },
  89                 {}
  90         }
  91 };
  92
  93 const struct nv50_disp_chan_mthd
  94 gf119_disp_base_chan_mthd = {
  95         .name = "Base",
  96         .addr = 0x001000,
  97         .prev = -0x020000,
  98         .data = {
  99                 { "Global", 1, &gf119_disp_base_mthd_base },
 100                 {  "Image", 2, &gf119_disp_base_mthd_image },
 101                 {}
 102         }
 103 };
 104
 105 const struct nv50_disp_dmac_oclass
 106 gf119_disp_base_oclass = {
 107         .base.oclass = GF110_DISP_BASE_CHANNEL_DMA,
 108         .base.minver = 0,
 109         .base.maxver = 0,
 110         .ctor = nv50_disp_base_new,
 111         .func = &gf119_disp_dmac_func,
 112         .mthd = &gf119_disp_base_chan_mthd,
 113         .chid = 1,
 114 };