drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "dmacnv50.h"
  25 #include "head.h"
  26 #include "rootnv50.h"
  27
  28 #include <core/client.h>
  29
  30 #include <nvif/class.h>
  31 #include <nvif/cl507c.h>
  32 #include <nvif/unpack.h>
  33
  34 int
  35 nv50_disp_base_new(const struct nv50_disp_dmac_func *func,
  36                    const struct nv50_disp_chan_mthd *mthd,
  37                    struct nv50_disp_root *root, int chid,
  38                    const struct nvkm_oclass *oclass, void *data, u32 size,
  39                    struct nvkm_object **pobject)
  40 {
  41         union {
  42                 struct nv50_disp_base_channel_dma_v0 v0;
  43         } *args = data;
  44         struct nvkm_object *parent = oclass->parent;
  45         struct nv50_disp *disp = root->disp;
  46         int head, ret = -ENOSYS;
  47         u64 push;
  48
  49         nvif_ioctl(parent, "create disp base channel dma size %d\n", size);
  50         if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
  51                 nvif_ioctl(parent, "create disp base channel dma vers %d "
  52                                    "pushbuf %016llx head %d\n",
  53                            args->v0.version, args->v0.pushbuf, args->v0.head);
  54                 if (!nvkm_head_find(&disp->base, args->v0.head))
  55                         return -EINVAL;
  56                 push = args->v0.pushbuf;
  57                 head = args->v0.head;
  58         } else
  59                 return ret;
  60
  61         return nv50_disp_dmac_new_(func, mthd, root, chid + head,
  62                                    head, push, oclass, pobject);
  63 }
  64
  65 static const struct nv50_disp_mthd_list
  66 nv50_disp_base_mthd_base = {
  67         .mthd = 0x0000,
  68         .addr = 0x000000,
  69         .data = {
  70                 { 0x0080, 0x000000 },
  71                 { 0x0084, 0x0008c4 },
  72                 { 0x0088, 0x0008d0 },
  73                 { 0x008c, 0x0008dc },
  74                 { 0x0090, 0x0008e4 },
  75                 { 0x0094, 0x610884 },
  76                 { 0x00a0, 0x6108a0 },
  77                 { 0x00a4, 0x610878 },
  78                 { 0x00c0, 0x61086c },
  79                 { 0x00e0, 0x610858 },
  80                 { 0x00e4, 0x610860 },
  81                 { 0x00e8, 0x6108ac },
  82                 { 0x00ec, 0x6108b4 },
  83                 { 0x0100, 0x610894 },
  84                 { 0x0110, 0x6108bc },
  85                 { 0x0114, 0x61088c },
  86                 {}
  87         }
  88 };
  89
  90 const struct nv50_disp_mthd_list
  91 nv50_disp_base_mthd_image = {
  92         .mthd = 0x0400,
  93         .addr = 0x000000,
  94         .data = {
  95                 { 0x0800, 0x6108f0 },
  96                 { 0x0804, 0x6108fc },
  97                 { 0x0808, 0x61090c },
  98                 { 0x080c, 0x610914 },
  99                 { 0x0810, 0x610904 },
 100                 {}
 101         }
 102 };
 103
 104 static const struct nv50_disp_chan_mthd
 105 nv50_disp_base_chan_mthd = {
 106         .name = "Base",
 107         .addr = 0x000540,
 108         .prev = 0x000004,
 109         .data = {
 110                 { "Global", 1, &nv50_disp_base_mthd_base },
 111                 {  "Image", 2, &nv50_disp_base_mthd_image },
 112                 {}
 113         }
 114 };
 115
 116 const struct nv50_disp_dmac_oclass
 117 nv50_disp_base_oclass = {
 118         .base.oclass = NV50_DISP_BASE_CHANNEL_DMA,
 119         .base.minver = 0,
 120         .base.maxver = 0,
 121         .ctor = nv50_disp_base_new,
 122         .func = &nv50_disp_dmac_func,
 123         .mthd = &nv50_disp_base_chan_mthd,
 124         .chid = 1,
 125 };