drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c

   1 /*
   2  * Copyright 2016 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "dmacnv50.h"
  25 #include "rootnv50.h"
  26
  27 #include <subdev/timer.h>
  28
  29 static int
  30 gp102_disp_dmac_init(struct nv50_disp_dmac *chan)
  31 {
  32         struct nv50_disp *disp = chan->base.root->disp;
  33         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
  34         struct nvkm_device *device = subdev->device;
  35         int ctrl = chan->base.chid.ctrl;
  36         int user = chan->base.chid.user;
  37
  38         /* enable error reporting */
  39         nvkm_mask(device, 0x6100a0, 0x00000001 << user, 0x00000001 << user);
  40
  41         /* initialise channel for dma command submission */
  42         nvkm_wr32(device, 0x611494 + (ctrl * 0x0010), chan->push);
  43         nvkm_wr32(device, 0x611498 + (ctrl * 0x0010), 0x00010000);
  44         nvkm_wr32(device, 0x61149c + (ctrl * 0x0010), 0x00000001);
  45         nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010);
  46         nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000);
  47         nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013);
  48
  49         /* wait for it to go inactive */
  50         if (nvkm_msec(device, 2000,
  51                 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x80000000))
  52                         break;
  53         ) < 0) {
  54                 nvkm_error(subdev, "ch %d init: %08x\n", user,
  55                            nvkm_rd32(device, 0x610490 + (ctrl * 0x10)));
  56                 return -EBUSY;
  57         }
  58
  59         return 0;
  60 }
  61
  62 const struct nv50_disp_dmac_func
  63 gp102_disp_dmac_func = {
  64         .init = gp102_disp_dmac_init,
  65         .fini = gf119_disp_dmac_fini,
  66         .bind = gf119_disp_dmac_bind,
  67 };