drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c

   1 /*
   2  * Copyright 2016 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "nv50.h"
  25 #include "head.h"
  26 #include "ior.h"
  27 #include "rootnv50.h"
  28
  29 static void
  30 gp102_disp_intr_error(struct nv50_disp *disp, int chid)
  31 {
  32         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
  33         struct nvkm_device *device = subdev->device;
  34         u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12));
  35         u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12));
  36         u32 unkn = nvkm_rd32(device, 0x6111f8 + (chid * 12));
  37
  38         nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n",
  39                    chid, (mthd & 0x0000ffc), data, mthd, unkn);
  40
  41         if (chid < ARRAY_SIZE(disp->chan)) {
  42                 switch (mthd & 0xffc) {
  43                 case 0x0080:
  44                         nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
  45                         break;
  46                 default:
  47                         break;
  48                 }
  49         }
  50
  51         nvkm_wr32(device, 0x61009c, (1 << chid));
  52         nvkm_wr32(device, 0x6111f0 + (chid * 12), 0x90000000);
  53 }
  54
  55 static const struct nv50_disp_func
  56 gp102_disp = {
  57         .intr = gf119_disp_intr,
  58         .intr_error = gp102_disp_intr_error,
  59         .uevent = &gf119_disp_chan_uevent,
  60         .super = gf119_disp_super,
  61         .root = &gp102_disp_root_oclass,
  62         .head.new = gf119_head_new,
  63         .sor = { .nr = 4, .new = gm200_sor_new },
  64 };
  65
  66 int
  67 gp102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
  68 {
  69         return gf119_disp_new_(&gp102_disp, device, index, pdisp);
  70 }