drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlyg84.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "dmacnv50.h"
  25 #include "rootnv50.h"
  26
  27 #include <nvif/class.h>
  28
  29 static const struct nv50_disp_mthd_list
  30 g84_disp_ovly_mthd_base = {
  31         .mthd = 0x0000,
  32         .addr = 0x000000,
  33         .data = {
  34                 { 0x0080, 0x000000 },
  35                 { 0x0084, 0x6109a0 },
  36                 { 0x0088, 0x6109c0 },
  37                 { 0x008c, 0x6109c8 },
  38                 { 0x0090, 0x6109b4 },
  39                 { 0x0094, 0x610970 },
  40                 { 0x00a0, 0x610998 },
  41                 { 0x00a4, 0x610964 },
  42                 { 0x00c0, 0x610958 },
  43                 { 0x00e0, 0x6109a8 },
  44                 { 0x00e4, 0x6109d0 },
  45                 { 0x00e8, 0x6109d8 },
  46                 { 0x0100, 0x61094c },
  47                 { 0x0104, 0x610984 },
  48                 { 0x0108, 0x61098c },
  49                 { 0x0800, 0x6109f8 },
  50                 { 0x0808, 0x610a08 },
  51                 { 0x080c, 0x610a10 },
  52                 { 0x0810, 0x610a00 },
  53                 {}
  54         }
  55 };
  56
  57 const struct nv50_disp_chan_mthd
  58 g84_disp_ovly_chan_mthd = {
  59         .name = "Overlay",
  60         .addr = 0x000540,
  61         .prev = 0x000004,
  62         .data = {
  63                 { "Global", 1, &g84_disp_ovly_mthd_base },
  64                 {}
  65         }
  66 };
  67
  68 const struct nv50_disp_dmac_oclass
  69 g84_disp_ovly_oclass = {
  70         .base.oclass = G82_DISP_OVERLAY_CHANNEL_DMA,
  71         .base.minver = 0,
  72         .base.maxver = 0,
  73         .ctor = nv50_disp_ovly_new,
  74         .func = &nv50_disp_dmac_func,
  75         .mthd = &g84_disp_ovly_chan_mthd,
  76         .chid = 3,
  77 };